diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF549.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/defBF549.h | 763 |
1 files changed, 13 insertions, 750 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index b1cc1c073b41..c2f4734da48d 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h | |||
| @@ -1070,21 +1070,13 @@ | |||
| 1070 | /* Bit masks for PIXC_CTL */ | 1070 | /* Bit masks for PIXC_CTL */ |
| 1071 | 1071 | ||
| 1072 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ | 1072 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ |
| 1073 | #define nPIXC_EN 0x0 | ||
| 1074 | #define OVR_A_EN 0x2 /* Overlay A Enable */ | 1073 | #define OVR_A_EN 0x2 /* Overlay A Enable */ |
| 1075 | #define nOVR_A_EN 0x0 | ||
| 1076 | #define OVR_B_EN 0x4 /* Overlay B Enable */ | 1074 | #define OVR_B_EN 0x4 /* Overlay B Enable */ |
| 1077 | #define nOVR_B_EN 0x0 | ||
| 1078 | #define IMG_FORM 0x8 /* Image Data Format */ | 1075 | #define IMG_FORM 0x8 /* Image Data Format */ |
| 1079 | #define nIMG_FORM 0x0 | ||
| 1080 | #define OVR_FORM 0x10 /* Overlay Data Format */ | 1076 | #define OVR_FORM 0x10 /* Overlay Data Format */ |
| 1081 | #define nOVR_FORM 0x0 | ||
| 1082 | #define OUT_FORM 0x20 /* Output Data Format */ | 1077 | #define OUT_FORM 0x20 /* Output Data Format */ |
| 1083 | #define nOUT_FORM 0x0 | ||
| 1084 | #define UDS_MOD 0x40 /* Resampling Mode */ | 1078 | #define UDS_MOD 0x40 /* Resampling Mode */ |
| 1085 | #define nUDS_MOD 0x0 | ||
| 1086 | #define TC_EN 0x80 /* Transparent Color Enable */ | 1079 | #define TC_EN 0x80 /* Transparent Color Enable */ |
| 1087 | #define nTC_EN 0x0 | ||
| 1088 | #define IMG_STAT 0x300 /* Image FIFO Status */ | 1080 | #define IMG_STAT 0x300 /* Image FIFO Status */ |
| 1089 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ | 1081 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ |
| 1090 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ | 1082 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ |
| @@ -1132,13 +1124,9 @@ | |||
| 1132 | /* Bit masks for PIXC_INTRSTAT */ | 1124 | /* Bit masks for PIXC_INTRSTAT */ |
| 1133 | 1125 | ||
| 1134 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ | 1126 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ |
| 1135 | #define nOVR_INT_EN 0x0 | ||
| 1136 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ | 1127 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ |
| 1137 | #define nFRM_INT_EN 0x0 | ||
| 1138 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ | 1128 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ |
| 1139 | #define nOVR_INT_STAT 0x0 | ||
| 1140 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ | 1129 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ |
| 1141 | #define nFRM_INT_STAT 0x0 | ||
| 1142 | 1130 | ||
| 1143 | /* Bit masks for PIXC_RYCON */ | 1131 | /* Bit masks for PIXC_RYCON */ |
| 1144 | 1132 | ||
| @@ -1146,7 +1134,6 @@ | |||
| 1146 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ | 1134 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ |
| 1147 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ | 1135 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ |
| 1148 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ | 1136 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 1149 | #define nRY_MULT4 0x0 | ||
| 1150 | 1137 | ||
| 1151 | /* Bit masks for PIXC_GUCON */ | 1138 | /* Bit masks for PIXC_GUCON */ |
| 1152 | 1139 | ||
| @@ -1154,7 +1141,6 @@ | |||
| 1154 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ | 1141 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ |
| 1155 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ | 1142 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ |
| 1156 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ | 1143 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 1157 | #define nGU_MULT4 0x0 | ||
| 1158 | 1144 | ||
| 1159 | /* Bit masks for PIXC_BVCON */ | 1145 | /* Bit masks for PIXC_BVCON */ |
| 1160 | 1146 | ||
| @@ -1162,7 +1148,6 @@ | |||
| 1162 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ | 1148 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ |
| 1163 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ | 1149 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ |
| 1164 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ | 1150 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 1165 | #define nBV_MULT4 0x0 | ||
| 1166 | 1151 | ||
| 1167 | /* Bit masks for PIXC_CCBIAS */ | 1152 | /* Bit masks for PIXC_CCBIAS */ |
| 1168 | 1153 | ||
| @@ -1179,48 +1164,28 @@ | |||
| 1179 | /* Bit masks for HOST_CONTROL */ | 1164 | /* Bit masks for HOST_CONTROL */ |
| 1180 | 1165 | ||
| 1181 | #define HOST_EN 0x1 /* Host Enable */ | 1166 | #define HOST_EN 0x1 /* Host Enable */ |
| 1182 | #define nHOST_EN 0x0 | ||
| 1183 | #define HOST_END 0x2 /* Host Endianess */ | 1167 | #define HOST_END 0x2 /* Host Endianess */ |
| 1184 | #define nHOST_END 0x0 | ||
| 1185 | #define DATA_SIZE 0x4 /* Data Size */ | 1168 | #define DATA_SIZE 0x4 /* Data Size */ |
| 1186 | #define nDATA_SIZE 0x0 | ||
| 1187 | #define HOST_RST 0x8 /* Host Reset */ | 1169 | #define HOST_RST 0x8 /* Host Reset */ |
| 1188 | #define nHOST_RST 0x0 | ||
| 1189 | #define HRDY_OVR 0x20 /* Host Ready Override */ | 1170 | #define HRDY_OVR 0x20 /* Host Ready Override */ |
| 1190 | #define nHRDY_OVR 0x0 | ||
| 1191 | #define INT_MODE 0x40 /* Interrupt Mode */ | 1171 | #define INT_MODE 0x40 /* Interrupt Mode */ |
| 1192 | #define nINT_MODE 0x0 | ||
| 1193 | #define BT_EN 0x80 /* Bus Timeout Enable */ | 1172 | #define BT_EN 0x80 /* Bus Timeout Enable */ |
| 1194 | #define nBT_EN 0x0 | ||
| 1195 | #define EHW 0x100 /* Enable Host Write */ | 1173 | #define EHW 0x100 /* Enable Host Write */ |
| 1196 | #define nEHW 0x0 | ||
| 1197 | #define EHR 0x200 /* Enable Host Read */ | 1174 | #define EHR 0x200 /* Enable Host Read */ |
| 1198 | #define nEHR 0x0 | ||
| 1199 | #define BDR 0x400 /* Burst DMA Requests */ | 1175 | #define BDR 0x400 /* Burst DMA Requests */ |
| 1200 | #define nBDR 0x0 | ||
| 1201 | 1176 | ||
| 1202 | /* Bit masks for HOST_STATUS */ | 1177 | /* Bit masks for HOST_STATUS */ |
| 1203 | 1178 | ||
| 1204 | #define READY 0x1 /* DMA Ready */ | 1179 | #define READY 0x1 /* DMA Ready */ |
| 1205 | #define nREADY 0x0 | ||
| 1206 | #define FIFOFULL 0x2 /* FIFO Full */ | 1180 | #define FIFOFULL 0x2 /* FIFO Full */ |
| 1207 | #define nFIFOFULL 0x0 | ||
| 1208 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | 1181 | #define FIFOEMPTY 0x4 /* FIFO Empty */ |
| 1209 | #define nFIFOEMPTY 0x0 | 1182 | #define DMA_COMPLETE 0x8 /* DMA Complete */ |
| 1210 | #define COMPLETE 0x8 /* DMA Complete */ | ||
| 1211 | #define nCOMPLETE 0x0 | ||
| 1212 | #define HSHK 0x10 /* Host Handshake */ | 1183 | #define HSHK 0x10 /* Host Handshake */ |
| 1213 | #define nHSHK 0x0 | ||
| 1214 | #define TIMEOUT 0x20 /* Host Timeout */ | 1184 | #define TIMEOUT 0x20 /* Host Timeout */ |
| 1215 | #define nTIMEOUT 0x0 | ||
| 1216 | #define HIRQ 0x40 /* Host Interrupt Request */ | 1185 | #define HIRQ 0x40 /* Host Interrupt Request */ |
| 1217 | #define nHIRQ 0x0 | ||
| 1218 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | 1186 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ |
| 1219 | #define nALLOW_CNFG 0x0 | ||
| 1220 | #define DMA_DIR 0x100 /* DMA Direction */ | 1187 | #define DMA_DIR 0x100 /* DMA Direction */ |
| 1221 | #define nDMA_DIR 0x0 | ||
| 1222 | #define BTE 0x200 /* Bus Timeout Enabled */ | 1188 | #define BTE 0x200 /* Bus Timeout Enabled */ |
| 1223 | #define nBTE 0x0 | ||
| 1224 | 1189 | ||
| 1225 | /* Bit masks for HOST_TIMEOUT */ | 1190 | /* Bit masks for HOST_TIMEOUT */ |
| 1226 | 1191 | ||
| @@ -1229,71 +1194,41 @@ | |||
| 1229 | /* Bit masks for MXVR_CONFIG */ | 1194 | /* Bit masks for MXVR_CONFIG */ |
| 1230 | 1195 | ||
| 1231 | #define MXVREN 0x1 /* MXVR Enable */ | 1196 | #define MXVREN 0x1 /* MXVR Enable */ |
| 1232 | #define nMXVREN 0x0 | ||
| 1233 | #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ | 1197 | #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ |
| 1234 | #define nMMSM 0x0 | ||
| 1235 | #define ACTIVE 0x4 /* Active Mode */ | 1198 | #define ACTIVE 0x4 /* Active Mode */ |
| 1236 | #define nACTIVE 0x0 | ||
| 1237 | #define SDELAY 0x8 /* Synchronous Data Delay */ | 1199 | #define SDELAY 0x8 /* Synchronous Data Delay */ |
| 1238 | #define nSDELAY 0x0 | ||
| 1239 | #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ | 1200 | #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ |
| 1240 | #define nNCMRXEN 0x0 | ||
| 1241 | #define RWRRXEN 0x20 /* Remote Write Receive Enable */ | 1201 | #define RWRRXEN 0x20 /* Remote Write Receive Enable */ |
| 1242 | #define nRWRRXEN 0x0 | ||
| 1243 | #define MTXEN 0x40 /* MXVR Transmit Data Enable */ | 1202 | #define MTXEN 0x40 /* MXVR Transmit Data Enable */ |
| 1244 | #define nMTXEN 0x0 | ||
| 1245 | #define MTXONB 0x80 /* MXVR Phy Transmitter On */ | 1203 | #define MTXONB 0x80 /* MXVR Phy Transmitter On */ |
| 1246 | #define nMTXONB 0x0 | ||
| 1247 | #define EPARITY 0x100 /* Even Parity Select */ | 1204 | #define EPARITY 0x100 /* Even Parity Select */ |
| 1248 | #define nEPARITY 0x0 | ||
| 1249 | #define MSB 0x1e00 /* Master Synchronous Boundary */ | 1205 | #define MSB 0x1e00 /* Master Synchronous Boundary */ |
| 1250 | #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ | 1206 | #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ |
| 1251 | #define nAPRXEN 0x0 | ||
| 1252 | #define WAKEUP 0x4000 /* Wake-Up */ | 1207 | #define WAKEUP 0x4000 /* Wake-Up */ |
| 1253 | #define nWAKEUP 0x0 | ||
| 1254 | #define LMECH 0x8000 /* Lock Mechanism Select */ | 1208 | #define LMECH 0x8000 /* Lock Mechanism Select */ |
| 1255 | #define nLMECH 0x0 | ||
| 1256 | 1209 | ||
| 1257 | /* Bit masks for MXVR_STATE_0 */ | 1210 | /* Bit masks for MXVR_STATE_0 */ |
| 1258 | 1211 | ||
| 1259 | #define NACT 0x1 /* Network Activity */ | 1212 | #define NACT 0x1 /* Network Activity */ |
| 1260 | #define nNACT 0x0 | ||
| 1261 | #define SBLOCK 0x2 /* Super Block Lock */ | 1213 | #define SBLOCK 0x2 /* Super Block Lock */ |
| 1262 | #define nSBLOCK 0x0 | ||
| 1263 | #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ | 1214 | #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ |
| 1264 | #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ | 1215 | #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ |
| 1265 | #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ | 1216 | #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ |
| 1266 | #define nAPBSY 0x0 | ||
| 1267 | #define APARB 0x200 /* Asynchronous Packet Arbitrating */ | 1217 | #define APARB 0x200 /* Asynchronous Packet Arbitrating */ |
| 1268 | #define nAPARB 0x0 | ||
| 1269 | #define APTX 0x400 /* Asynchronous Packet Transmitting */ | 1218 | #define APTX 0x400 /* Asynchronous Packet Transmitting */ |
| 1270 | #define nAPTX 0x0 | ||
| 1271 | #define APRX 0x800 /* Receiving Asynchronous Packet */ | 1219 | #define APRX 0x800 /* Receiving Asynchronous Packet */ |
| 1272 | #define nAPRX 0x0 | ||
| 1273 | #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ | 1220 | #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ |
| 1274 | #define nCMBSY 0x0 | ||
| 1275 | #define CMARB 0x2000 /* Control Message Arbitrating */ | 1221 | #define CMARB 0x2000 /* Control Message Arbitrating */ |
| 1276 | #define nCMARB 0x0 | ||
| 1277 | #define CMTX 0x4000 /* Control Message Transmitting */ | 1222 | #define CMTX 0x4000 /* Control Message Transmitting */ |
| 1278 | #define nCMTX 0x0 | ||
| 1279 | #define CMRX 0x8000 /* Receiving Control Message */ | 1223 | #define CMRX 0x8000 /* Receiving Control Message */ |
| 1280 | #define nCMRX 0x0 | ||
| 1281 | #define MRXONB 0x10000 /* MRXONB Pin State */ | 1224 | #define MRXONB 0x10000 /* MRXONB Pin State */ |
| 1282 | #define nMRXONB 0x0 | ||
| 1283 | #define RGSIP 0x20000 /* Remote Get Source In Progress */ | 1225 | #define RGSIP 0x20000 /* Remote Get Source In Progress */ |
| 1284 | #define nRGSIP 0x0 | ||
| 1285 | #define DALIP 0x40000 /* Resource Deallocate In Progress */ | 1226 | #define DALIP 0x40000 /* Resource Deallocate In Progress */ |
| 1286 | #define nDALIP 0x0 | ||
| 1287 | #define ALIP 0x80000 /* Resource Allocate In Progress */ | 1227 | #define ALIP 0x80000 /* Resource Allocate In Progress */ |
| 1288 | #define nALIP 0x0 | ||
| 1289 | #define RRDIP 0x100000 /* Remote Read In Progress */ | 1228 | #define RRDIP 0x100000 /* Remote Read In Progress */ |
| 1290 | #define nRRDIP 0x0 | ||
| 1291 | #define RWRIP 0x200000 /* Remote Write In Progress */ | 1229 | #define RWRIP 0x200000 /* Remote Write In Progress */ |
| 1292 | #define nRWRIP 0x0 | ||
| 1293 | #define FLOCK 0x400000 /* Frame Lock */ | 1230 | #define FLOCK 0x400000 /* Frame Lock */ |
| 1294 | #define nFLOCK 0x0 | ||
| 1295 | #define BLOCK 0x800000 /* Block Lock */ | 1231 | #define BLOCK 0x800000 /* Block Lock */ |
| 1296 | #define nBLOCK 0x0 | ||
| 1297 | #define RSB 0xf000000 /* Received Synchronous Boundary */ | 1232 | #define RSB 0xf000000 /* Received Synchronous Boundary */ |
| 1298 | #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ | 1233 | #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ |
| 1299 | 1234 | ||
| @@ -1302,535 +1237,343 @@ | |||
| 1302 | #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ | 1237 | #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ |
| 1303 | #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ | 1238 | #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ |
| 1304 | #define APCONT 0x100 /* Asynchronous Packet Continuation */ | 1239 | #define APCONT 0x100 /* Asynchronous Packet Continuation */ |
| 1305 | #define nAPCONT 0x0 | ||
| 1306 | #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ | 1240 | #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ |
| 1307 | #define DMAACTIVE0 0x10000 /* DMA0 Active */ | 1241 | #define DMAACTIVE0 0x10000 /* DMA0 Active */ |
| 1308 | #define nDMAACTIVE0 0x0 | ||
| 1309 | #define DMAACTIVE1 0x20000 /* DMA1 Active */ | 1242 | #define DMAACTIVE1 0x20000 /* DMA1 Active */ |
| 1310 | #define nDMAACTIVE1 0x0 | ||
| 1311 | #define DMAACTIVE2 0x40000 /* DMA2 Active */ | 1243 | #define DMAACTIVE2 0x40000 /* DMA2 Active */ |
| 1312 | #define nDMAACTIVE2 0x0 | ||
| 1313 | #define DMAACTIVE3 0x80000 /* DMA3 Active */ | 1244 | #define DMAACTIVE3 0x80000 /* DMA3 Active */ |
| 1314 | #define nDMAACTIVE3 0x0 | ||
| 1315 | #define DMAACTIVE4 0x100000 /* DMA4 Active */ | 1245 | #define DMAACTIVE4 0x100000 /* DMA4 Active */ |
| 1316 | #define nDMAACTIVE4 0x0 | ||
| 1317 | #define DMAACTIVE5 0x200000 /* DMA5 Active */ | 1246 | #define DMAACTIVE5 0x200000 /* DMA5 Active */ |
| 1318 | #define nDMAACTIVE5 0x0 | ||
| 1319 | #define DMAACTIVE6 0x400000 /* DMA6 Active */ | 1247 | #define DMAACTIVE6 0x400000 /* DMA6 Active */ |
| 1320 | #define nDMAACTIVE6 0x0 | ||
| 1321 | #define DMAACTIVE7 0x800000 /* DMA7 Active */ | 1248 | #define DMAACTIVE7 0x800000 /* DMA7 Active */ |
| 1322 | #define nDMAACTIVE7 0x0 | ||
| 1323 | #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ | 1249 | #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ |
| 1324 | #define nDMAPMEN0 0x0 | ||
| 1325 | #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ | 1250 | #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ |
| 1326 | #define nDMAPMEN1 0x0 | ||
| 1327 | #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ | 1251 | #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ |
| 1328 | #define nDMAPMEN2 0x0 | ||
| 1329 | #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ | 1252 | #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ |
| 1330 | #define nDMAPMEN3 0x0 | ||
| 1331 | #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ | 1253 | #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ |
| 1332 | #define nDMAPMEN4 0x0 | ||
| 1333 | #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ | 1254 | #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ |
| 1334 | #define nDMAPMEN5 0x0 | ||
| 1335 | #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ | 1255 | #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ |
| 1336 | #define nDMAPMEN6 0x0 | ||
| 1337 | #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ | 1256 | #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ |
| 1338 | #define nDMAPMEN7 0x0 | ||
| 1339 | 1257 | ||
| 1340 | /* Bit masks for MXVR_INT_STAT_0 */ | 1258 | /* Bit masks for MXVR_INT_STAT_0 */ |
| 1341 | 1259 | ||
| 1342 | #define NI2A 0x1 /* Network Inactive to Active */ | 1260 | #define NI2A 0x1 /* Network Inactive to Active */ |
| 1343 | #define nNI2A 0x0 | ||
| 1344 | #define NA2I 0x2 /* Network Active to Inactive */ | 1261 | #define NA2I 0x2 /* Network Active to Inactive */ |
| 1345 | #define nNA2I 0x0 | ||
| 1346 | #define SBU2L 0x4 /* Super Block Unlock to Lock */ | 1262 | #define SBU2L 0x4 /* Super Block Unlock to Lock */ |
| 1347 | #define nSBU2L 0x0 | ||
| 1348 | #define SBL2U 0x8 /* Super Block Lock to Unlock */ | 1263 | #define SBL2U 0x8 /* Super Block Lock to Unlock */ |
| 1349 | #define nSBL2U 0x0 | ||
| 1350 | #define PRU 0x10 /* Position Register Updated */ | 1264 | #define PRU 0x10 /* Position Register Updated */ |
| 1351 | #define nPRU 0x0 | ||
| 1352 | #define MPRU 0x20 /* Maximum Position Register Updated */ | 1265 | #define MPRU 0x20 /* Maximum Position Register Updated */ |
| 1353 | #define nMPRU 0x0 | ||
| 1354 | #define DRU 0x40 /* Delay Register Updated */ | 1266 | #define DRU 0x40 /* Delay Register Updated */ |
| 1355 | #define nDRU 0x0 | ||
| 1356 | #define MDRU 0x80 /* Maximum Delay Register Updated */ | 1267 | #define MDRU 0x80 /* Maximum Delay Register Updated */ |
| 1357 | #define nMDRU 0x0 | ||
| 1358 | #define SBU 0x100 /* Synchronous Boundary Updated */ | 1268 | #define SBU 0x100 /* Synchronous Boundary Updated */ |
| 1359 | #define nSBU 0x0 | ||
| 1360 | #define ATU 0x200 /* Allocation Table Updated */ | 1269 | #define ATU 0x200 /* Allocation Table Updated */ |
| 1361 | #define nATU 0x0 | ||
| 1362 | #define FCZ0 0x400 /* Frame Counter 0 Zero */ | 1270 | #define FCZ0 0x400 /* Frame Counter 0 Zero */ |
| 1363 | #define nFCZ0 0x0 | ||
| 1364 | #define FCZ1 0x800 /* Frame Counter 1 Zero */ | 1271 | #define FCZ1 0x800 /* Frame Counter 1 Zero */ |
| 1365 | #define nFCZ1 0x0 | ||
| 1366 | #define PERR 0x1000 /* Parity Error */ | 1272 | #define PERR 0x1000 /* Parity Error */ |
| 1367 | #define nPERR 0x0 | ||
| 1368 | #define MH2L 0x2000 /* MRXONB High to Low */ | 1273 | #define MH2L 0x2000 /* MRXONB High to Low */ |
| 1369 | #define nMH2L 0x0 | ||
| 1370 | #define ML2H 0x4000 /* MRXONB Low to High */ | 1274 | #define ML2H 0x4000 /* MRXONB Low to High */ |
| 1371 | #define nML2H 0x0 | ||
| 1372 | #define WUP 0x8000 /* Wake-Up Preamble Received */ | 1275 | #define WUP 0x8000 /* Wake-Up Preamble Received */ |
| 1373 | #define nWUP 0x0 | ||
| 1374 | #define FU2L 0x10000 /* Frame Unlock to Lock */ | 1276 | #define FU2L 0x10000 /* Frame Unlock to Lock */ |
| 1375 | #define nFU2L 0x0 | ||
| 1376 | #define FL2U 0x20000 /* Frame Lock to Unlock */ | 1277 | #define FL2U 0x20000 /* Frame Lock to Unlock */ |
| 1377 | #define nFL2U 0x0 | ||
| 1378 | #define BU2L 0x40000 /* Block Unlock to Lock */ | 1278 | #define BU2L 0x40000 /* Block Unlock to Lock */ |
| 1379 | #define nBU2L 0x0 | ||
| 1380 | #define BL2U 0x80000 /* Block Lock to Unlock */ | 1279 | #define BL2U 0x80000 /* Block Lock to Unlock */ |
| 1381 | #define nBL2U 0x0 | ||
| 1382 | #define OBERR 0x100000 /* DMA Out of Bounds Error */ | 1280 | #define OBERR 0x100000 /* DMA Out of Bounds Error */ |
| 1383 | #define nOBERR 0x0 | ||
| 1384 | #define PFL 0x200000 /* PLL Frequency Locked */ | 1281 | #define PFL 0x200000 /* PLL Frequency Locked */ |
| 1385 | #define nPFL 0x0 | ||
| 1386 | #define SCZ 0x400000 /* System Clock Counter Zero */ | 1282 | #define SCZ 0x400000 /* System Clock Counter Zero */ |
| 1387 | #define nSCZ 0x0 | ||
| 1388 | #define FERR 0x800000 /* FIFO Error */ | 1283 | #define FERR 0x800000 /* FIFO Error */ |
| 1389 | #define nFERR 0x0 | ||
| 1390 | #define CMR 0x1000000 /* Control Message Received */ | 1284 | #define CMR 0x1000000 /* Control Message Received */ |
| 1391 | #define nCMR 0x0 | ||
| 1392 | #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ | 1285 | #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ |
| 1393 | #define nCMROF 0x0 | ||
| 1394 | #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ | 1286 | #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ |
| 1395 | #define nCMTS 0x0 | ||
| 1396 | #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ | 1287 | #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ |
| 1397 | #define nCMTC 0x0 | ||
| 1398 | #define RWRC 0x10000000 /* Remote Write Control Message Completed */ | 1288 | #define RWRC 0x10000000 /* Remote Write Control Message Completed */ |
| 1399 | #define nRWRC 0x0 | ||
| 1400 | #define BCZ 0x20000000 /* Block Counter Zero */ | 1289 | #define BCZ 0x20000000 /* Block Counter Zero */ |
| 1401 | #define nBCZ 0x0 | ||
| 1402 | #define BMERR 0x40000000 /* Biphase Mark Coding Error */ | 1290 | #define BMERR 0x40000000 /* Biphase Mark Coding Error */ |
| 1403 | #define nBMERR 0x0 | ||
| 1404 | #define DERR 0x80000000 /* DMA Error */ | 1291 | #define DERR 0x80000000 /* DMA Error */ |
| 1405 | #define nDERR 0x0 | ||
| 1406 | 1292 | ||
| 1407 | /* Bit masks for MXVR_INT_STAT_1 */ | 1293 | /* Bit masks for MXVR_INT_STAT_1 */ |
| 1408 | 1294 | ||
| 1409 | #define HDONE0 0x1 /* DMA0 Half Done */ | 1295 | #define HDONE0 0x1 /* DMA0 Half Done */ |
| 1410 | #define nHDONE0 0x0 | ||
| 1411 | #define DONE0 0x2 /* DMA0 Done */ | 1296 | #define DONE0 0x2 /* DMA0 Done */ |
| 1412 | #define nDONE0 0x0 | ||
| 1413 | #define APR 0x4 /* Asynchronous Packet Received */ | 1297 | #define APR 0x4 /* Asynchronous Packet Received */ |
| 1414 | #define nAPR 0x0 | ||
| 1415 | #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ | 1298 | #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ |
| 1416 | #define nAPROF 0x0 | ||
| 1417 | #define HDONE1 0x10 /* DMA1 Half Done */ | 1299 | #define HDONE1 0x10 /* DMA1 Half Done */ |
| 1418 | #define nHDONE1 0x0 | ||
| 1419 | #define DONE1 0x20 /* DMA1 Done */ | 1300 | #define DONE1 0x20 /* DMA1 Done */ |
| 1420 | #define nDONE1 0x0 | ||
| 1421 | #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ | 1301 | #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ |
| 1422 | #define nAPTS 0x0 | ||
| 1423 | #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ | 1302 | #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ |
| 1424 | #define nAPTC 0x0 | ||
| 1425 | #define HDONE2 0x100 /* DMA2 Half Done */ | 1303 | #define HDONE2 0x100 /* DMA2 Half Done */ |
| 1426 | #define nHDONE2 0x0 | ||
| 1427 | #define DONE2 0x200 /* DMA2 Done */ | 1304 | #define DONE2 0x200 /* DMA2 Done */ |
| 1428 | #define nDONE2 0x0 | ||
| 1429 | #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ | 1305 | #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ |
| 1430 | #define nAPRCE 0x0 | ||
| 1431 | #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ | 1306 | #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ |
| 1432 | #define nAPRPE 0x0 | ||
| 1433 | #define HDONE3 0x1000 /* DMA3 Half Done */ | 1307 | #define HDONE3 0x1000 /* DMA3 Half Done */ |
| 1434 | #define nHDONE3 0x0 | ||
| 1435 | #define DONE3 0x2000 /* DMA3 Done */ | 1308 | #define DONE3 0x2000 /* DMA3 Done */ |
| 1436 | #define nDONE3 0x0 | ||
| 1437 | #define HDONE4 0x10000 /* DMA4 Half Done */ | 1309 | #define HDONE4 0x10000 /* DMA4 Half Done */ |
| 1438 | #define nHDONE4 0x0 | ||
| 1439 | #define DONE4 0x20000 /* DMA4 Done */ | 1310 | #define DONE4 0x20000 /* DMA4 Done */ |
| 1440 | #define nDONE4 0x0 | ||
| 1441 | #define HDONE5 0x100000 /* DMA5 Half Done */ | 1311 | #define HDONE5 0x100000 /* DMA5 Half Done */ |
| 1442 | #define nHDONE5 0x0 | ||
| 1443 | #define DONE5 0x200000 /* DMA5 Done */ | 1312 | #define DONE5 0x200000 /* DMA5 Done */ |
| 1444 | #define nDONE5 0x0 | ||
| 1445 | #define HDONE6 0x1000000 /* DMA6 Half Done */ | 1313 | #define HDONE6 0x1000000 /* DMA6 Half Done */ |
| 1446 | #define nHDONE6 0x0 | ||
| 1447 | #define DONE6 0x2000000 /* DMA6 Done */ | 1314 | #define DONE6 0x2000000 /* DMA6 Done */ |
| 1448 | #define nDONE6 0x0 | ||
| 1449 | #define HDONE7 0x10000000 /* DMA7 Half Done */ | 1315 | #define HDONE7 0x10000000 /* DMA7 Half Done */ |
| 1450 | #define nHDONE7 0x0 | ||
| 1451 | #define DONE7 0x20000000 /* DMA7 Done */ | 1316 | #define DONE7 0x20000000 /* DMA7 Done */ |
| 1452 | #define nDONE7 0x0 | ||
| 1453 | 1317 | ||
| 1454 | /* Bit masks for MXVR_INT_EN_0 */ | 1318 | /* Bit masks for MXVR_INT_EN_0 */ |
| 1455 | 1319 | ||
| 1456 | #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ | 1320 | #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ |
| 1457 | #define nNI2AEN 0x0 | ||
| 1458 | #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ | 1321 | #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ |
| 1459 | #define nNA2IEN 0x0 | ||
| 1460 | #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ | 1322 | #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ |
| 1461 | #define nSBU2LEN 0x0 | ||
| 1462 | #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ | 1323 | #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ |
| 1463 | #define nSBL2UEN 0x0 | ||
| 1464 | #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ | 1324 | #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ |
| 1465 | #define nPRUEN 0x0 | ||
| 1466 | #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ | 1325 | #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ |
| 1467 | #define nMPRUEN 0x0 | ||
| 1468 | #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ | 1326 | #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ |
| 1469 | #define nDRUEN 0x0 | ||
| 1470 | #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ | 1327 | #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ |
| 1471 | #define nMDRUEN 0x0 | ||
| 1472 | #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ | 1328 | #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ |
| 1473 | #define nSBUEN 0x0 | ||
| 1474 | #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ | 1329 | #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ |
| 1475 | #define nATUEN 0x0 | ||
| 1476 | #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ | 1330 | #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ |
| 1477 | #define nFCZ0EN 0x0 | ||
| 1478 | #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ | 1331 | #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ |
| 1479 | #define nFCZ1EN 0x0 | ||
| 1480 | #define PERREN 0x1000 /* Parity Error Interrupt Enable */ | 1332 | #define PERREN 0x1000 /* Parity Error Interrupt Enable */ |
| 1481 | #define nPERREN 0x0 | ||
| 1482 | #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ | 1333 | #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ |
| 1483 | #define nMH2LEN 0x0 | ||
| 1484 | #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ | 1334 | #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ |
| 1485 | #define nML2HEN 0x0 | ||
| 1486 | #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ | 1335 | #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ |
| 1487 | #define nWUPEN 0x0 | ||
| 1488 | #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ | 1336 | #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ |
| 1489 | #define nFU2LEN 0x0 | ||
| 1490 | #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ | 1337 | #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ |
| 1491 | #define nFL2UEN 0x0 | ||
| 1492 | #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ | 1338 | #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ |
| 1493 | #define nBU2LEN 0x0 | ||
| 1494 | #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ | 1339 | #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ |
| 1495 | #define nBL2UEN 0x0 | ||
| 1496 | #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ | 1340 | #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ |
| 1497 | #define nOBERREN 0x0 | ||
| 1498 | #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ | 1341 | #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ |
| 1499 | #define nPFLEN 0x0 | ||
| 1500 | #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ | 1342 | #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ |
| 1501 | #define nSCZEN 0x0 | ||
| 1502 | #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ | 1343 | #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ |
| 1503 | #define nFERREN 0x0 | ||
| 1504 | #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ | 1344 | #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ |
| 1505 | #define nCMREN 0x0 | ||
| 1506 | #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ | 1345 | #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ |
| 1507 | #define nCMROFEN 0x0 | ||
| 1508 | #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ | 1346 | #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ |
| 1509 | #define nCMTSEN 0x0 | ||
| 1510 | #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ | 1347 | #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ |
| 1511 | #define nCMTCEN 0x0 | ||
| 1512 | #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ | 1348 | #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ |
| 1513 | #define nRWRCEN 0x0 | ||
| 1514 | #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ | 1349 | #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ |
| 1515 | #define nBCZEN 0x0 | ||
| 1516 | #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ | 1350 | #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ |
| 1517 | #define nBMERREN 0x0 | ||
| 1518 | #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ | 1351 | #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ |
| 1519 | #define nDERREN 0x0 | ||
| 1520 | 1352 | ||
| 1521 | /* Bit masks for MXVR_INT_EN_1 */ | 1353 | /* Bit masks for MXVR_INT_EN_1 */ |
| 1522 | 1354 | ||
| 1523 | #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ | 1355 | #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ |
| 1524 | #define nHDONEEN0 0x0 | ||
| 1525 | #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ | 1356 | #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ |
| 1526 | #define nDONEEN0 0x0 | ||
| 1527 | #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ | 1357 | #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ |
| 1528 | #define nAPREN 0x0 | ||
| 1529 | #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ | 1358 | #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ |
| 1530 | #define nAPROFEN 0x0 | ||
| 1531 | #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ | 1359 | #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ |
| 1532 | #define nHDONEEN1 0x0 | ||
| 1533 | #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ | 1360 | #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ |
| 1534 | #define nDONEEN1 0x0 | ||
| 1535 | #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ | 1361 | #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ |
| 1536 | #define nAPTSEN 0x0 | ||
| 1537 | #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ | 1362 | #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ |
| 1538 | #define nAPTCEN 0x0 | ||
| 1539 | #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ | 1363 | #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ |
| 1540 | #define nHDONEEN2 0x0 | ||
| 1541 | #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ | 1364 | #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ |
| 1542 | #define nDONEEN2 0x0 | ||
| 1543 | #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ | 1365 | #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ |
| 1544 | #define nAPRCEEN 0x0 | ||
| 1545 | #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ | 1366 | #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ |
| 1546 | #define nAPRPEEN 0x0 | ||
| 1547 | #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ | 1367 | #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ |
| 1548 | #define nHDONEEN3 0x0 | ||
| 1549 | #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ | 1368 | #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ |
| 1550 | #define nDONEEN3 0x0 | ||
| 1551 | #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ | 1369 | #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ |
| 1552 | #define nHDONEEN4 0x0 | ||
| 1553 | #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ | 1370 | #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ |
| 1554 | #define nDONEEN4 0x0 | ||
| 1555 | #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ | 1371 | #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ |
| 1556 | #define nHDONEEN5 0x0 | ||
| 1557 | #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ | 1372 | #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ |
| 1558 | #define nDONEEN5 0x0 | ||
| 1559 | #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ | 1373 | #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ |
| 1560 | #define nHDONEEN6 0x0 | ||
| 1561 | #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ | 1374 | #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ |
| 1562 | #define nDONEEN6 0x0 | ||
| 1563 | #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ | 1375 | #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ |
| 1564 | #define nHDONEEN7 0x0 | ||
| 1565 | #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ | 1376 | #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ |
| 1566 | #define nDONEEN7 0x0 | ||
| 1567 | 1377 | ||
| 1568 | /* Bit masks for MXVR_POSITION */ | 1378 | /* Bit masks for MXVR_POSITION */ |
| 1569 | 1379 | ||
| 1570 | #define POSITION 0x3f /* Node Position */ | 1380 | #define POSITION 0x3f /* Node Position */ |
| 1571 | #define PVALID 0x8000 /* Node Position Valid */ | 1381 | #define PVALID 0x8000 /* Node Position Valid */ |
| 1572 | #define nPVALID 0x0 | ||
| 1573 | 1382 | ||
| 1574 | /* Bit masks for MXVR_MAX_POSITION */ | 1383 | /* Bit masks for MXVR_MAX_POSITION */ |
| 1575 | 1384 | ||
| 1576 | #define MPOSITION 0x3f /* Maximum Node Position */ | 1385 | #define MPOSITION 0x3f /* Maximum Node Position */ |
| 1577 | #define MPVALID 0x8000 /* Maximum Node Position Valid */ | 1386 | #define MPVALID 0x8000 /* Maximum Node Position Valid */ |
| 1578 | #define nMPVALID 0x0 | ||
| 1579 | 1387 | ||
| 1580 | /* Bit masks for MXVR_DELAY */ | 1388 | /* Bit masks for MXVR_DELAY */ |
| 1581 | 1389 | ||
| 1582 | #define DELAY 0x3f /* Node Frame Delay */ | 1390 | #define DELAY 0x3f /* Node Frame Delay */ |
| 1583 | #define DVALID 0x8000 /* Node Frame Delay Valid */ | 1391 | #define DVALID 0x8000 /* Node Frame Delay Valid */ |
| 1584 | #define nDVALID 0x0 | ||
| 1585 | 1392 | ||
| 1586 | /* Bit masks for MXVR_MAX_DELAY */ | 1393 | /* Bit masks for MXVR_MAX_DELAY */ |
| 1587 | 1394 | ||
| 1588 | #define MDELAY 0x3f /* Maximum Node Frame Delay */ | 1395 | #define MDELAY 0x3f /* Maximum Node Frame Delay */ |
| 1589 | #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ | 1396 | #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ |
| 1590 | #define nMDVALID 0x0 | ||
| 1591 | 1397 | ||
| 1592 | /* Bit masks for MXVR_LADDR */ | 1398 | /* Bit masks for MXVR_LADDR */ |
| 1593 | 1399 | ||
| 1594 | #define LADDR 0xffff /* Logical Address */ | 1400 | #define LADDR 0xffff /* Logical Address */ |
| 1595 | #define LVALID 0x80000000 /* Logical Address Valid */ | 1401 | #define LVALID 0x80000000 /* Logical Address Valid */ |
| 1596 | #define nLVALID 0x0 | ||
| 1597 | 1402 | ||
| 1598 | /* Bit masks for MXVR_GADDR */ | 1403 | /* Bit masks for MXVR_GADDR */ |
| 1599 | 1404 | ||
| 1600 | #define GADDRL 0xff /* Group Address Lower Byte */ | 1405 | #define GADDRL 0xff /* Group Address Lower Byte */ |
| 1601 | #define GVALID 0x8000 /* Group Address Valid */ | 1406 | #define GVALID 0x8000 /* Group Address Valid */ |
| 1602 | #define nGVALID 0x0 | ||
| 1603 | 1407 | ||
| 1604 | /* Bit masks for MXVR_AADDR */ | 1408 | /* Bit masks for MXVR_AADDR */ |
| 1605 | 1409 | ||
| 1606 | #define AADDR 0xffff /* Alternate Address */ | 1410 | #define AADDR 0xffff /* Alternate Address */ |
| 1607 | #define AVALID 0x80000000 /* Alternate Address Valid */ | 1411 | #define AVALID 0x80000000 /* Alternate Address Valid */ |
| 1608 | #define nAVALID 0x0 | ||
| 1609 | 1412 | ||
| 1610 | /* Bit masks for MXVR_ALLOC_0 */ | 1413 | /* Bit masks for MXVR_ALLOC_0 */ |
| 1611 | 1414 | ||
| 1612 | #define CL0 0x7f /* Channel 0 Connection Label */ | 1415 | #define CL0 0x7f /* Channel 0 Connection Label */ |
| 1613 | #define CIU0 0x80 /* Channel 0 In Use */ | 1416 | #define CIU0 0x80 /* Channel 0 In Use */ |
| 1614 | #define nCIU0 0x0 | ||
| 1615 | #define CL1 0x7f00 /* Channel 0 Connection Label */ | 1417 | #define CL1 0x7f00 /* Channel 0 Connection Label */ |
| 1616 | #define CIU1 0x8000 /* Channel 0 In Use */ | 1418 | #define CIU1 0x8000 /* Channel 0 In Use */ |
| 1617 | #define nCIU1 0x0 | ||
| 1618 | #define CL2 0x7f0000 /* Channel 0 Connection Label */ | 1419 | #define CL2 0x7f0000 /* Channel 0 Connection Label */ |
| 1619 | #define CIU2 0x800000 /* Channel 0 In Use */ | 1420 | #define CIU2 0x800000 /* Channel 0 In Use */ |
| 1620 | #define nCIU2 0x0 | ||
| 1621 | #define CL3 0x7f000000 /* Channel 0 Connection Label */ | 1421 | #define CL3 0x7f000000 /* Channel 0 Connection Label */ |
| 1622 | #define CIU3 0x80000000 /* Channel 0 In Use */ | 1422 | #define CIU3 0x80000000 /* Channel 0 In Use */ |
| 1623 | #define nCIU3 0x0 | ||
| 1624 | 1423 | ||
| 1625 | /* Bit masks for MXVR_ALLOC_1 */ | 1424 | /* Bit masks for MXVR_ALLOC_1 */ |
| 1626 | 1425 | ||
| 1627 | #define CL4 0x7f /* Channel 4 Connection Label */ | 1426 | #define CL4 0x7f /* Channel 4 Connection Label */ |
| 1628 | #define CIU4 0x80 /* Channel 4 In Use */ | 1427 | #define CIU4 0x80 /* Channel 4 In Use */ |
| 1629 | #define nCIU4 0x0 | ||
| 1630 | #define CL5 0x7f00 /* Channel 5 Connection Label */ | 1428 | #define CL5 0x7f00 /* Channel 5 Connection Label */ |
| 1631 | #define CIU5 0x8000 /* Channel 5 In Use */ | 1429 | #define CIU5 0x8000 /* Channel 5 In Use */ |
| 1632 | #define nCIU5 0x0 | ||
| 1633 | #define CL6 0x7f0000 /* Channel 6 Connection Label */ | 1430 | #define CL6 0x7f0000 /* Channel 6 Connection Label */ |
| 1634 | #define CIU6 0x800000 /* Channel 6 In Use */ | 1431 | #define CIU6 0x800000 /* Channel 6 In Use */ |
| 1635 | #define nCIU6 0x0 | ||
| 1636 | #define CL7 0x7f000000 /* Channel 7 Connection Label */ | 1432 | #define CL7 0x7f000000 /* Channel 7 Connection Label */ |
| 1637 | #define CIU7 0x80000000 /* Channel 7 In Use */ | 1433 | #define CIU7 0x80000000 /* Channel 7 In Use */ |
| 1638 | #define nCIU7 0x0 | ||
| 1639 | 1434 | ||
| 1640 | /* Bit masks for MXVR_ALLOC_2 */ | 1435 | /* Bit masks for MXVR_ALLOC_2 */ |
| 1641 | 1436 | ||
| 1642 | #define CL8 0x7f /* Channel 8 Connection Label */ | 1437 | #define CL8 0x7f /* Channel 8 Connection Label */ |
| 1643 | #define CIU8 0x80 /* Channel 8 In Use */ | 1438 | #define CIU8 0x80 /* Channel 8 In Use */ |
| 1644 | #define nCIU8 0x0 | ||
| 1645 | #define CL9 0x7f00 /* Channel 9 Connection Label */ | 1439 | #define CL9 0x7f00 /* Channel 9 Connection Label */ |
| 1646 | #define CIU9 0x8000 /* Channel 9 In Use */ | 1440 | #define CIU9 0x8000 /* Channel 9 In Use */ |
| 1647 | #define nCIU9 0x0 | ||
| 1648 | #define CL10 0x7f0000 /* Channel 10 Connection Label */ | 1441 | #define CL10 0x7f0000 /* Channel 10 Connection Label */ |
| 1649 | #define CIU10 0x800000 /* Channel 10 In Use */ | 1442 | #define CIU10 0x800000 /* Channel 10 In Use */ |
| 1650 | #define nCIU10 0x0 | ||
| 1651 | #define CL11 0x7f000000 /* Channel 11 Connection Label */ | 1443 | #define CL11 0x7f000000 /* Channel 11 Connection Label */ |
| 1652 | #define CIU11 0x80000000 /* Channel 11 In Use */ | 1444 | #define CIU11 0x80000000 /* Channel 11 In Use */ |
| 1653 | #define nCIU11 0x0 | ||
| 1654 | 1445 | ||
| 1655 | /* Bit masks for MXVR_ALLOC_3 */ | 1446 | /* Bit masks for MXVR_ALLOC_3 */ |
| 1656 | 1447 | ||
| 1657 | #define CL12 0x7f /* Channel 12 Connection Label */ | 1448 | #define CL12 0x7f /* Channel 12 Connection Label */ |
| 1658 | #define CIU12 0x80 /* Channel 12 In Use */ | 1449 | #define CIU12 0x80 /* Channel 12 In Use */ |
| 1659 | #define nCIU12 0x0 | ||
| 1660 | #define CL13 0x7f00 /* Channel 13 Connection Label */ | 1450 | #define CL13 0x7f00 /* Channel 13 Connection Label */ |
| 1661 | #define CIU13 0x8000 /* Channel 13 In Use */ | 1451 | #define CIU13 0x8000 /* Channel 13 In Use */ |
| 1662 | #define nCIU13 0x0 | ||
| 1663 | #define CL14 0x7f0000 /* Channel 14 Connection Label */ | 1452 | #define CL14 0x7f0000 /* Channel 14 Connection Label */ |
| 1664 | #define CIU14 0x800000 /* Channel 14 In Use */ | 1453 | #define CIU14 0x800000 /* Channel 14 In Use */ |
| 1665 | #define nCIU14 0x0 | ||
| 1666 | #define CL15 0x7f000000 /* Channel 15 Connection Label */ | 1454 | #define CL15 0x7f000000 /* Channel 15 Connection Label */ |
| 1667 | #define CIU15 0x80000000 /* Channel 15 In Use */ | 1455 | #define CIU15 0x80000000 /* Channel 15 In Use */ |
| 1668 | #define nCIU15 0x0 | ||
| 1669 | 1456 | ||
| 1670 | /* Bit masks for MXVR_ALLOC_4 */ | 1457 | /* Bit masks for MXVR_ALLOC_4 */ |
| 1671 | 1458 | ||
| 1672 | #define CL16 0x7f /* Channel 16 Connection Label */ | 1459 | #define CL16 0x7f /* Channel 16 Connection Label */ |
| 1673 | #define CIU16 0x80 /* Channel 16 In Use */ | 1460 | #define CIU16 0x80 /* Channel 16 In Use */ |
| 1674 | #define nCIU16 0x0 | ||
| 1675 | #define CL17 0x7f00 /* Channel 17 Connection Label */ | 1461 | #define CL17 0x7f00 /* Channel 17 Connection Label */ |
| 1676 | #define CIU17 0x8000 /* Channel 17 In Use */ | 1462 | #define CIU17 0x8000 /* Channel 17 In Use */ |
| 1677 | #define nCIU17 0x0 | ||
| 1678 | #define CL18 0x7f0000 /* Channel 18 Connection Label */ | 1463 | #define CL18 0x7f0000 /* Channel 18 Connection Label */ |
| 1679 | #define CIU18 0x800000 /* Channel 18 In Use */ | 1464 | #define CIU18 0x800000 /* Channel 18 In Use */ |
| 1680 | #define nCIU18 0x0 | ||
| 1681 | #define CL19 0x7f000000 /* Channel 19 Connection Label */ | 1465 | #define CL19 0x7f000000 /* Channel 19 Connection Label */ |
| 1682 | #define CIU19 0x80000000 /* Channel 19 In Use */ | 1466 | #define CIU19 0x80000000 /* Channel 19 In Use */ |
| 1683 | #define nCIU19 0x0 | ||
| 1684 | 1467 | ||
| 1685 | /* Bit masks for MXVR_ALLOC_5 */ | 1468 | /* Bit masks for MXVR_ALLOC_5 */ |
| 1686 | 1469 | ||
| 1687 | #define CL20 0x7f /* Channel 20 Connection Label */ | 1470 | #define CL20 0x7f /* Channel 20 Connection Label */ |
| 1688 | #define CIU20 0x80 /* Channel 20 In Use */ | 1471 | #define CIU20 0x80 /* Channel 20 In Use */ |
| 1689 | #define nCIU20 0x0 | ||
| 1690 | #define CL21 0x7f00 /* Channel 21 Connection Label */ | 1472 | #define CL21 0x7f00 /* Channel 21 Connection Label */ |
| 1691 | #define CIU21 0x8000 /* Channel 21 In Use */ | 1473 | #define CIU21 0x8000 /* Channel 21 In Use */ |
| 1692 | #define nCIU21 0x0 | ||
| 1693 | #define CL22 0x7f0000 /* Channel 22 Connection Label */ | 1474 | #define CL22 0x7f0000 /* Channel 22 Connection Label */ |
| 1694 | #define CIU22 0x800000 /* Channel 22 In Use */ | 1475 | #define CIU22 0x800000 /* Channel 22 In Use */ |
| 1695 | #define nCIU22 0x0 | ||
| 1696 | #define CL23 0x7f000000 /* Channel 23 Connection Label */ | 1476 | #define CL23 0x7f000000 /* Channel 23 Connection Label */ |
| 1697 | #define CIU23 0x80000000 /* Channel 23 In Use */ | 1477 | #define CIU23 0x80000000 /* Channel 23 In Use */ |
| 1698 | #define nCIU23 0x0 | ||
| 1699 | 1478 | ||
| 1700 | /* Bit masks for MXVR_ALLOC_6 */ | 1479 | /* Bit masks for MXVR_ALLOC_6 */ |
| 1701 | 1480 | ||
| 1702 | #define CL24 0x7f /* Channel 24 Connection Label */ | 1481 | #define CL24 0x7f /* Channel 24 Connection Label */ |
| 1703 | #define CIU24 0x80 /* Channel 24 In Use */ | 1482 | #define CIU24 0x80 /* Channel 24 In Use */ |
| 1704 | #define nCIU24 0x0 | ||
| 1705 | #define CL25 0x7f00 /* Channel 25 Connection Label */ | 1483 | #define CL25 0x7f00 /* Channel 25 Connection Label */ |
| 1706 | #define CIU25 0x8000 /* Channel 25 In Use */ | 1484 | #define CIU25 0x8000 /* Channel 25 In Use */ |
| 1707 | #define nCIU25 0x0 | ||
| 1708 | #define CL26 0x7f0000 /* Channel 26 Connection Label */ | 1485 | #define CL26 0x7f0000 /* Channel 26 Connection Label */ |
| 1709 | #define CIU26 0x800000 /* Channel 26 In Use */ | 1486 | #define CIU26 0x800000 /* Channel 26 In Use */ |
| 1710 | #define nCIU26 0x0 | ||
| 1711 | #define CL27 0x7f000000 /* Channel 27 Connection Label */ | 1487 | #define CL27 0x7f000000 /* Channel 27 Connection Label */ |
| 1712 | #define CIU27 0x80000000 /* Channel 27 In Use */ | 1488 | #define CIU27 0x80000000 /* Channel 27 In Use */ |
| 1713 | #define nCIU27 0x0 | ||
| 1714 | 1489 | ||
| 1715 | /* Bit masks for MXVR_ALLOC_7 */ | 1490 | /* Bit masks for MXVR_ALLOC_7 */ |
| 1716 | 1491 | ||
| 1717 | #define CL28 0x7f /* Channel 28 Connection Label */ | 1492 | #define CL28 0x7f /* Channel 28 Connection Label */ |
| 1718 | #define CIU28 0x80 /* Channel 28 In Use */ | 1493 | #define CIU28 0x80 /* Channel 28 In Use */ |
| 1719 | #define nCIU28 0x0 | ||
| 1720 | #define CL29 0x7f00 /* Channel 29 Connection Label */ | 1494 | #define CL29 0x7f00 /* Channel 29 Connection Label */ |
| 1721 | #define CIU29 0x8000 /* Channel 29 In Use */ | 1495 | #define CIU29 0x8000 /* Channel 29 In Use */ |
| 1722 | #define nCIU29 0x0 | ||
| 1723 | #define CL30 0x7f0000 /* Channel 30 Connection Label */ | 1496 | #define CL30 0x7f0000 /* Channel 30 Connection Label */ |
| 1724 | #define CIU30 0x800000 /* Channel 30 In Use */ | 1497 | #define CIU30 0x800000 /* Channel 30 In Use */ |
| 1725 | #define nCIU30 0x0 | ||
| 1726 | #define CL31 0x7f000000 /* Channel 31 Connection Label */ | 1498 | #define CL31 0x7f000000 /* Channel 31 Connection Label */ |
| 1727 | #define CIU31 0x80000000 /* Channel 31 In Use */ | 1499 | #define CIU31 0x80000000 /* Channel 31 In Use */ |
| 1728 | #define nCIU31 0x0 | ||
| 1729 | 1500 | ||
| 1730 | /* Bit masks for MXVR_ALLOC_8 */ | 1501 | /* Bit masks for MXVR_ALLOC_8 */ |
| 1731 | 1502 | ||
| 1732 | #define CL32 0x7f /* Channel 32 Connection Label */ | 1503 | #define CL32 0x7f /* Channel 32 Connection Label */ |
| 1733 | #define CIU32 0x80 /* Channel 32 In Use */ | 1504 | #define CIU32 0x80 /* Channel 32 In Use */ |
| 1734 | #define nCIU32 0x0 | ||
| 1735 | #define CL33 0x7f00 /* Channel 33 Connection Label */ | 1505 | #define CL33 0x7f00 /* Channel 33 Connection Label */ |
| 1736 | #define CIU33 0x8000 /* Channel 33 In Use */ | 1506 | #define CIU33 0x8000 /* Channel 33 In Use */ |
| 1737 | #define nCIU33 0x0 | ||
| 1738 | #define CL34 0x7f0000 /* Channel 34 Connection Label */ | 1507 | #define CL34 0x7f0000 /* Channel 34 Connection Label */ |
| 1739 | #define CIU34 0x800000 /* Channel 34 In Use */ | 1508 | #define CIU34 0x800000 /* Channel 34 In Use */ |
| 1740 | #define nCIU34 0x0 | ||
| 1741 | #define CL35 0x7f000000 /* Channel 35 Connection Label */ | 1509 | #define CL35 0x7f000000 /* Channel 35 Connection Label */ |
| 1742 | #define CIU35 0x80000000 /* Channel 35 In Use */ | 1510 | #define CIU35 0x80000000 /* Channel 35 In Use */ |
| 1743 | #define nCIU35 0x0 | ||
| 1744 | 1511 | ||
| 1745 | /* Bit masks for MXVR_ALLOC_9 */ | 1512 | /* Bit masks for MXVR_ALLOC_9 */ |
| 1746 | 1513 | ||
| 1747 | #define CL36 0x7f /* Channel 36 Connection Label */ | 1514 | #define CL36 0x7f /* Channel 36 Connection Label */ |
| 1748 | #define CIU36 0x80 /* Channel 36 In Use */ | 1515 | #define CIU36 0x80 /* Channel 36 In Use */ |
| 1749 | #define nCIU36 0x0 | ||
| 1750 | #define CL37 0x7f00 /* Channel 37 Connection Label */ | 1516 | #define CL37 0x7f00 /* Channel 37 Connection Label */ |
| 1751 | #define CIU37 0x8000 /* Channel 37 In Use */ | 1517 | #define CIU37 0x8000 /* Channel 37 In Use */ |
| 1752 | #define nCIU37 0x0 | ||
| 1753 | #define CL38 0x7f0000 /* Channel 38 Connection Label */ | 1518 | #define CL38 0x7f0000 /* Channel 38 Connection Label */ |
| 1754 | #define CIU38 0x800000 /* Channel 38 In Use */ | 1519 | #define CIU38 0x800000 /* Channel 38 In Use */ |
| 1755 | #define nCIU38 0x0 | ||
| 1756 | #define CL39 0x7f000000 /* Channel 39 Connection Label */ | 1520 | #define CL39 0x7f000000 /* Channel 39 Connection Label */ |
| 1757 | #define CIU39 0x80000000 /* Channel 39 In Use */ | 1521 | #define CIU39 0x80000000 /* Channel 39 In Use */ |
| 1758 | #define nCIU39 0x0 | ||
| 1759 | 1522 | ||
| 1760 | /* Bit masks for MXVR_ALLOC_10 */ | 1523 | /* Bit masks for MXVR_ALLOC_10 */ |
| 1761 | 1524 | ||
| 1762 | #define CL40 0x7f /* Channel 40 Connection Label */ | 1525 | #define CL40 0x7f /* Channel 40 Connection Label */ |
| 1763 | #define CIU40 0x80 /* Channel 40 In Use */ | 1526 | #define CIU40 0x80 /* Channel 40 In Use */ |
| 1764 | #define nCIU40 0x0 | ||
| 1765 | #define CL41 0x7f00 /* Channel 41 Connection Label */ | 1527 | #define CL41 0x7f00 /* Channel 41 Connection Label */ |
| 1766 | #define CIU41 0x8000 /* Channel 41 In Use */ | 1528 | #define CIU41 0x8000 /* Channel 41 In Use */ |
| 1767 | #define nCIU41 0x0 | ||
| 1768 | #define CL42 0x7f0000 /* Channel 42 Connection Label */ | 1529 | #define CL42 0x7f0000 /* Channel 42 Connection Label */ |
| 1769 | #define CIU42 0x800000 /* Channel 42 In Use */ | 1530 | #define CIU42 0x800000 /* Channel 42 In Use */ |
| 1770 | #define nCIU42 0x0 | ||
| 1771 | #define CL43 0x7f000000 /* Channel 43 Connection Label */ | 1531 | #define CL43 0x7f000000 /* Channel 43 Connection Label */ |
| 1772 | #define CIU43 0x80000000 /* Channel 43 In Use */ | 1532 | #define CIU43 0x80000000 /* Channel 43 In Use */ |
| 1773 | #define nCIU43 0x0 | ||
| 1774 | 1533 | ||
| 1775 | /* Bit masks for MXVR_ALLOC_11 */ | 1534 | /* Bit masks for MXVR_ALLOC_11 */ |
| 1776 | 1535 | ||
| 1777 | #define CL44 0x7f /* Channel 44 Connection Label */ | 1536 | #define CL44 0x7f /* Channel 44 Connection Label */ |
| 1778 | #define CIU44 0x80 /* Channel 44 In Use */ | 1537 | #define CIU44 0x80 /* Channel 44 In Use */ |
| 1779 | #define nCIU44 0x0 | ||
| 1780 | #define CL45 0x7f00 /* Channel 45 Connection Label */ | 1538 | #define CL45 0x7f00 /* Channel 45 Connection Label */ |
| 1781 | #define CIU45 0x8000 /* Channel 45 In Use */ | 1539 | #define CIU45 0x8000 /* Channel 45 In Use */ |
| 1782 | #define nCIU45 0x0 | ||
| 1783 | #define CL46 0x7f0000 /* Channel 46 Connection Label */ | 1540 | #define CL46 0x7f0000 /* Channel 46 Connection Label */ |
| 1784 | #define CIU46 0x800000 /* Channel 46 In Use */ | 1541 | #define CIU46 0x800000 /* Channel 46 In Use */ |
| 1785 | #define nCIU46 0x0 | ||
| 1786 | #define CL47 0x7f000000 /* Channel 47 Connection Label */ | 1542 | #define CL47 0x7f000000 /* Channel 47 Connection Label */ |
| 1787 | #define CIU47 0x80000000 /* Channel 47 In Use */ | 1543 | #define CIU47 0x80000000 /* Channel 47 In Use */ |
| 1788 | #define nCIU47 0x0 | ||
| 1789 | 1544 | ||
| 1790 | /* Bit masks for MXVR_ALLOC_12 */ | 1545 | /* Bit masks for MXVR_ALLOC_12 */ |
| 1791 | 1546 | ||
| 1792 | #define CL48 0x7f /* Channel 48 Connection Label */ | 1547 | #define CL48 0x7f /* Channel 48 Connection Label */ |
| 1793 | #define CIU48 0x80 /* Channel 48 In Use */ | 1548 | #define CIU48 0x80 /* Channel 48 In Use */ |
| 1794 | #define nCIU48 0x0 | ||
| 1795 | #define CL49 0x7f00 /* Channel 49 Connection Label */ | 1549 | #define CL49 0x7f00 /* Channel 49 Connection Label */ |
| 1796 | #define CIU49 0x8000 /* Channel 49 In Use */ | 1550 | #define CIU49 0x8000 /* Channel 49 In Use */ |
| 1797 | #define nCIU49 0x0 | ||
| 1798 | #define CL50 0x7f0000 /* Channel 50 Connection Label */ | 1551 | #define CL50 0x7f0000 /* Channel 50 Connection Label */ |
| 1799 | #define CIU50 0x800000 /* Channel 50 In Use */ | 1552 | #define CIU50 0x800000 /* Channel 50 In Use */ |
| 1800 | #define nCIU50 0x0 | ||
| 1801 | #define CL51 0x7f000000 /* Channel 51 Connection Label */ | 1553 | #define CL51 0x7f000000 /* Channel 51 Connection Label */ |
| 1802 | #define CIU51 0x80000000 /* Channel 51 In Use */ | 1554 | #define CIU51 0x80000000 /* Channel 51 In Use */ |
| 1803 | #define nCIU51 0x0 | ||
| 1804 | 1555 | ||
| 1805 | /* Bit masks for MXVR_ALLOC_13 */ | 1556 | /* Bit masks for MXVR_ALLOC_13 */ |
| 1806 | 1557 | ||
| 1807 | #define CL52 0x7f /* Channel 52 Connection Label */ | 1558 | #define CL52 0x7f /* Channel 52 Connection Label */ |
| 1808 | #define CIU52 0x80 /* Channel 52 In Use */ | 1559 | #define CIU52 0x80 /* Channel 52 In Use */ |
| 1809 | #define nCIU52 0x0 | ||
| 1810 | #define CL53 0x7f00 /* Channel 53 Connection Label */ | 1560 | #define CL53 0x7f00 /* Channel 53 Connection Label */ |
| 1811 | #define CIU53 0x8000 /* Channel 53 In Use */ | 1561 | #define CIU53 0x8000 /* Channel 53 In Use */ |
| 1812 | #define nCIU53 0x0 | ||
| 1813 | #define CL54 0x7f0000 /* Channel 54 Connection Label */ | 1562 | #define CL54 0x7f0000 /* Channel 54 Connection Label */ |
| 1814 | #define CIU54 0x800000 /* Channel 54 In Use */ | 1563 | #define CIU54 0x800000 /* Channel 54 In Use */ |
| 1815 | #define nCIU54 0x0 | ||
| 1816 | #define CL55 0x7f000000 /* Channel 55 Connection Label */ | 1564 | #define CL55 0x7f000000 /* Channel 55 Connection Label */ |
| 1817 | #define CIU55 0x80000000 /* Channel 55 In Use */ | 1565 | #define CIU55 0x80000000 /* Channel 55 In Use */ |
| 1818 | #define nCIU55 0x0 | ||
| 1819 | 1566 | ||
| 1820 | /* Bit masks for MXVR_ALLOC_14 */ | 1567 | /* Bit masks for MXVR_ALLOC_14 */ |
| 1821 | 1568 | ||
| 1822 | #define CL56 0x7f /* Channel 56 Connection Label */ | 1569 | #define CL56 0x7f /* Channel 56 Connection Label */ |
| 1823 | #define CIU56 0x80 /* Channel 56 In Use */ | 1570 | #define CIU56 0x80 /* Channel 56 In Use */ |
| 1824 | #define nCIU56 0x0 | ||
| 1825 | #define CL57 0x7f00 /* Channel 57 Connection Label */ | 1571 | #define CL57 0x7f00 /* Channel 57 Connection Label */ |
| 1826 | #define CIU57 0x8000 /* Channel 57 In Use */ | 1572 | #define CIU57 0x8000 /* Channel 57 In Use */ |
| 1827 | #define nCIU57 0x0 | ||
| 1828 | #define CL58 0x7f0000 /* Channel 58 Connection Label */ | 1573 | #define CL58 0x7f0000 /* Channel 58 Connection Label */ |
| 1829 | #define CIU58 0x800000 /* Channel 58 In Use */ | 1574 | #define CIU58 0x800000 /* Channel 58 In Use */ |
| 1830 | #define nCIU58 0x0 | ||
| 1831 | #define CL59 0x7f000000 /* Channel 59 Connection Label */ | 1575 | #define CL59 0x7f000000 /* Channel 59 Connection Label */ |
| 1832 | #define CIU59 0x80000000 /* Channel 59 In Use */ | 1576 | #define CIU59 0x80000000 /* Channel 59 In Use */ |
| 1833 | #define nCIU59 0x0 | ||
| 1834 | 1577 | ||
| 1835 | /* MXVR_SYNC_LCHAN_0 Masks */ | 1578 | /* MXVR_SYNC_LCHAN_0 Masks */ |
| 1836 | 1579 | ||
| @@ -1926,19 +1669,13 @@ | |||
| 1926 | /* Bit masks for MXVR_DMAx_CONFIG */ | 1669 | /* Bit masks for MXVR_DMAx_CONFIG */ |
| 1927 | 1670 | ||
| 1928 | #define MDMAEN 0x1 /* DMA Channel Enable */ | 1671 | #define MDMAEN 0x1 /* DMA Channel Enable */ |
| 1929 | #define nMDMAEN 0x0 | ||
| 1930 | #define DD 0x2 /* DMA Channel Direction */ | 1672 | #define DD 0x2 /* DMA Channel Direction */ |
| 1931 | #define nDD 0x0 | ||
| 1932 | #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ | 1673 | #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ |
| 1933 | #define nBY4SWAPEN 0x0 | ||
| 1934 | #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ | 1674 | #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ |
| 1935 | #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ | 1675 | #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ |
| 1936 | #define nBITSWAPEN 0x0 | ||
| 1937 | #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ | 1676 | #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ |
| 1938 | #define nBY2SWAPEN 0x0 | ||
| 1939 | #define MFLOW 0x7000 /* DMA Channel Operation Flow */ | 1677 | #define MFLOW 0x7000 /* DMA Channel Operation Flow */ |
| 1940 | #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ | 1678 | #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ |
| 1941 | #define nFIXEDPM 0x0 | ||
| 1942 | #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ | 1679 | #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ |
| 1943 | #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ | 1680 | #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ |
| 1944 | #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ | 1681 | #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ |
| @@ -1946,94 +1683,71 @@ | |||
| 1946 | /* Bit masks for MXVR_AP_CTL */ | 1683 | /* Bit masks for MXVR_AP_CTL */ |
| 1947 | 1684 | ||
| 1948 | #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ | 1685 | #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ |
| 1949 | #define nSTARTAP 0x0 | ||
| 1950 | #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ | 1686 | #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ |
| 1951 | #define nCANCELAP 0x0 | ||
| 1952 | #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ | 1687 | #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ |
| 1953 | #define nRESETAP 0x0 | ||
| 1954 | #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ | 1688 | #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ |
| 1955 | #define nAPRBE0 0x0 | ||
| 1956 | #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ | 1689 | #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ |
| 1957 | #define nAPRBE1 0x0 | ||
| 1958 | 1690 | ||
| 1959 | /* Bit masks for MXVR_APRB_START_ADDR */ | 1691 | /* Bit masks for MXVR_APRB_START_ADDR */ |
| 1960 | 1692 | ||
| 1961 | #define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ | 1693 | #define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ |
| 1962 | 1694 | ||
| 1963 | /* Bit masks for MXVR_APRB_CURR_ADDR */ | 1695 | /* Bit masks for MXVR_APRB_CURR_ADDR */ |
| 1964 | 1696 | ||
| 1965 | #define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ | 1697 | #define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ |
| 1966 | 1698 | ||
| 1967 | /* Bit masks for MXVR_APTB_START_ADDR */ | 1699 | /* Bit masks for MXVR_APTB_START_ADDR */ |
| 1968 | 1700 | ||
| 1969 | #define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ | 1701 | #define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ |
| 1970 | 1702 | ||
| 1971 | /* Bit masks for MXVR_APTB_CURR_ADDR */ | 1703 | /* Bit masks for MXVR_APTB_CURR_ADDR */ |
| 1972 | 1704 | ||
| 1973 | #define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ | 1705 | #define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ |
| 1974 | 1706 | ||
| 1975 | /* Bit masks for MXVR_CM_CTL */ | 1707 | /* Bit masks for MXVR_CM_CTL */ |
| 1976 | 1708 | ||
| 1977 | #define STARTCM 0x1 /* Start Control Message Transmission */ | 1709 | #define STARTCM 0x1 /* Start Control Message Transmission */ |
| 1978 | #define nSTARTCM 0x0 | ||
| 1979 | #define CANCELCM 0x2 /* Cancel Control Message Transmission */ | 1710 | #define CANCELCM 0x2 /* Cancel Control Message Transmission */ |
| 1980 | #define nCANCELCM 0x0 | ||
| 1981 | #define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ | 1711 | #define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ |
| 1982 | #define nCMRBE0 0x0 | ||
| 1983 | #define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ | 1712 | #define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ |
| 1984 | #define nCMRBE1 0x0 | ||
| 1985 | #define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ | 1713 | #define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ |
| 1986 | #define nCMRBE2 0x0 | ||
| 1987 | #define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ | 1714 | #define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ |
| 1988 | #define nCMRBE3 0x0 | ||
| 1989 | #define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ | 1715 | #define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ |
| 1990 | #define nCMRBE4 0x0 | ||
| 1991 | #define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ | 1716 | #define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ |
| 1992 | #define nCMRBE5 0x0 | ||
| 1993 | #define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ | 1717 | #define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ |
| 1994 | #define nCMRBE6 0x0 | ||
| 1995 | #define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ | 1718 | #define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ |
| 1996 | #define nCMRBE7 0x0 | ||
| 1997 | #define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ | 1719 | #define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ |
| 1998 | #define nCMRBE8 0x0 | ||
| 1999 | #define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ | 1720 | #define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ |
| 2000 | #define nCMRBE9 0x0 | ||
| 2001 | #define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ | 1721 | #define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ |
| 2002 | #define nCMRBE10 0x0 | ||
| 2003 | #define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ | 1722 | #define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ |
| 2004 | #define nCMRBE11 0x0 | ||
| 2005 | #define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ | 1723 | #define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ |
| 2006 | #define nCMRBE12 0x0 | ||
| 2007 | #define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ | 1724 | #define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ |
| 2008 | #define nCMRBE13 0x0 | ||
| 2009 | #define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ | 1725 | #define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ |
| 2010 | #define nCMRBE14 0x0 | ||
| 2011 | #define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ | 1726 | #define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ |
| 2012 | #define nCMRBE15 0x0 | ||
| 2013 | 1727 | ||
| 2014 | /* Bit masks for MXVR_CMRB_START_ADDR */ | 1728 | /* Bit masks for MXVR_CMRB_START_ADDR */ |
| 2015 | 1729 | ||
| 2016 | #define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */ | 1730 | #define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ |
| 2017 | 1731 | ||
| 2018 | /* Bit masks for MXVR_CMRB_CURR_ADDR */ | 1732 | /* Bit masks for MXVR_CMRB_CURR_ADDR */ |
| 2019 | 1733 | ||
| 2020 | #define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */ | 1734 | #define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ |
| 2021 | 1735 | ||
| 2022 | /* Bit masks for MXVR_CMTB_START_ADDR */ | 1736 | /* Bit masks for MXVR_CMTB_START_ADDR */ |
| 2023 | 1737 | ||
| 2024 | #define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */ | 1738 | #define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ |
| 2025 | 1739 | ||
| 2026 | /* Bit masks for MXVR_CMTB_CURR_ADDR */ | 1740 | /* Bit masks for MXVR_CMTB_CURR_ADDR */ |
| 2027 | 1741 | ||
| 2028 | #define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */ | 1742 | #define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ |
| 2029 | 1743 | ||
| 2030 | /* Bit masks for MXVR_RRDB_START_ADDR */ | 1744 | /* Bit masks for MXVR_RRDB_START_ADDR */ |
| 2031 | 1745 | ||
| 2032 | #define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */ | 1746 | #define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ |
| 2033 | 1747 | ||
| 2034 | /* Bit masks for MXVR_RRDB_CURR_ADDR */ | 1748 | /* Bit masks for MXVR_RRDB_CURR_ADDR */ |
| 2035 | 1749 | ||
| 2036 | #define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */ | 1750 | #define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ |
| 2037 | 1751 | ||
| 2038 | /* Bit masks for MXVR_PAT_DATAx */ | 1752 | /* Bit masks for MXVR_PAT_DATAx */ |
| 2039 | 1753 | ||
| @@ -2045,136 +1759,72 @@ | |||
| 2045 | /* Bit masks for MXVR_PAT_EN_0 */ | 1759 | /* Bit masks for MXVR_PAT_EN_0 */ |
| 2046 | 1760 | ||
| 2047 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ | 1761 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ |
| 2048 | #define nMATCH_EN_0_0 0x0 | ||
| 2049 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ | 1762 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ |
| 2050 | #define nMATCH_EN_0_1 0x0 | ||
| 2051 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ | 1763 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ |
| 2052 | #define nMATCH_EN_0_2 0x0 | ||
| 2053 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ | 1764 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ |
| 2054 | #define nMATCH_EN_0_3 0x0 | ||
| 2055 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ | 1765 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ |
| 2056 | #define nMATCH_EN_0_4 0x0 | ||
| 2057 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ | 1766 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ |
| 2058 | #define nMATCH_EN_0_5 0x0 | ||
| 2059 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ | 1767 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ |
| 2060 | #define nMATCH_EN_0_6 0x0 | ||
| 2061 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ | 1768 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ |
| 2062 | #define nMATCH_EN_0_7 0x0 | ||
| 2063 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ | 1769 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ |
| 2064 | #define nMATCH_EN_1_0 0x0 | ||
| 2065 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ | 1770 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ |
| 2066 | #define nMATCH_EN_1_1 0x0 | ||
| 2067 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ | 1771 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ |
| 2068 | #define nMATCH_EN_1_2 0x0 | ||
| 2069 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ | 1772 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ |
| 2070 | #define nMATCH_EN_1_3 0x0 | ||
| 2071 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ | 1773 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ |
| 2072 | #define nMATCH_EN_1_4 0x0 | ||
| 2073 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ | 1774 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ |
| 2074 | #define nMATCH_EN_1_5 0x0 | ||
| 2075 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ | 1775 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ |
| 2076 | #define nMATCH_EN_1_6 0x0 | ||
| 2077 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ | 1776 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ |
| 2078 | #define nMATCH_EN_1_7 0x0 | ||
| 2079 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ | 1777 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ |
| 2080 | #define nMATCH_EN_2_0 0x0 | ||
| 2081 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ | 1778 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ |
| 2082 | #define nMATCH_EN_2_1 0x0 | ||
| 2083 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ | 1779 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ |
| 2084 | #define nMATCH_EN_2_2 0x0 | ||
| 2085 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ | 1780 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ |
| 2086 | #define nMATCH_EN_2_3 0x0 | ||
| 2087 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ | 1781 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ |
| 2088 | #define nMATCH_EN_2_4 0x0 | ||
| 2089 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ | 1782 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ |
| 2090 | #define nMATCH_EN_2_5 0x0 | ||
| 2091 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ | 1783 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ |
| 2092 | #define nMATCH_EN_2_6 0x0 | ||
| 2093 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ | 1784 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ |
| 2094 | #define nMATCH_EN_2_7 0x0 | ||
| 2095 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ | 1785 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ |
| 2096 | #define nMATCH_EN_3_0 0x0 | ||
| 2097 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ | 1786 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ |
| 2098 | #define nMATCH_EN_3_1 0x0 | ||
| 2099 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ | 1787 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ |
| 2100 | #define nMATCH_EN_3_2 0x0 | ||
| 2101 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ | 1788 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ |
| 2102 | #define nMATCH_EN_3_3 0x0 | ||
| 2103 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ | 1789 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ |
| 2104 | #define nMATCH_EN_3_4 0x0 | ||
| 2105 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ | 1790 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ |
| 2106 | #define nMATCH_EN_3_5 0x0 | ||
| 2107 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ | 1791 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ |
| 2108 | #define nMATCH_EN_3_6 0x0 | ||
| 2109 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ | 1792 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ |
| 2110 | #define nMATCH_EN_3_7 0x0 | ||
| 2111 | 1793 | ||
| 2112 | /* Bit masks for MXVR_PAT_EN_1 */ | 1794 | /* Bit masks for MXVR_PAT_EN_1 */ |
| 2113 | 1795 | ||
| 2114 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ | 1796 | #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ |
| 2115 | #define nMATCH_EN_0_0 0x0 | ||
| 2116 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ | 1797 | #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ |
| 2117 | #define nMATCH_EN_0_1 0x0 | ||
| 2118 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ | 1798 | #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ |
| 2119 | #define nMATCH_EN_0_2 0x0 | ||
| 2120 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ | 1799 | #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ |
| 2121 | #define nMATCH_EN_0_3 0x0 | ||
| 2122 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ | 1800 | #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ |
| 2123 | #define nMATCH_EN_0_4 0x0 | ||
| 2124 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ | 1801 | #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ |
| 2125 | #define nMATCH_EN_0_5 0x0 | ||
| 2126 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ | 1802 | #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ |
| 2127 | #define nMATCH_EN_0_6 0x0 | ||
| 2128 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ | 1803 | #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ |
| 2129 | #define nMATCH_EN_0_7 0x0 | ||
| 2130 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ | 1804 | #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ |
| 2131 | #define nMATCH_EN_1_0 0x0 | ||
| 2132 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ | 1805 | #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ |
| 2133 | #define nMATCH_EN_1_1 0x0 | ||
| 2134 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ | 1806 | #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ |
| 2135 | #define nMATCH_EN_1_2 0x0 | ||
| 2136 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ | 1807 | #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ |
| 2137 | #define nMATCH_EN_1_3 0x0 | ||
| 2138 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ | 1808 | #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ |
| 2139 | #define nMATCH_EN_1_4 0x0 | ||
| 2140 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ | 1809 | #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ |
| 2141 | #define nMATCH_EN_1_5 0x0 | ||
| 2142 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ | 1810 | #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ |
| 2143 | #define nMATCH_EN_1_6 0x0 | ||
| 2144 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ | 1811 | #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ |
| 2145 | #define nMATCH_EN_1_7 0x0 | ||
| 2146 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ | 1812 | #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ |
| 2147 | #define nMATCH_EN_2_0 0x0 | ||
| 2148 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ | 1813 | #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ |
| 2149 | #define nMATCH_EN_2_1 0x0 | ||
| 2150 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ | 1814 | #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ |
| 2151 | #define nMATCH_EN_2_2 0x0 | ||
| 2152 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ | 1815 | #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ |
| 2153 | #define nMATCH_EN_2_3 0x0 | ||
| 2154 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ | 1816 | #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ |
| 2155 | #define nMATCH_EN_2_4 0x0 | ||
| 2156 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ | 1817 | #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ |
| 2157 | #define nMATCH_EN_2_5 0x0 | ||
| 2158 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ | 1818 | #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ |
| 2159 | #define nMATCH_EN_2_6 0x0 | ||
| 2160 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ | 1819 | #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ |
| 2161 | #define nMATCH_EN_2_7 0x0 | ||
| 2162 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ | 1820 | #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ |
| 2163 | #define nMATCH_EN_3_0 0x0 | ||
| 2164 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ | 1821 | #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ |
| 2165 | #define nMATCH_EN_3_1 0x0 | ||
| 2166 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ | 1822 | #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ |
| 2167 | #define nMATCH_EN_3_2 0x0 | ||
| 2168 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ | 1823 | #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ |
| 2169 | #define nMATCH_EN_3_3 0x0 | ||
| 2170 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ | 1824 | #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ |
| 2171 | #define nMATCH_EN_3_4 0x0 | ||
| 2172 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ | 1825 | #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ |
| 2173 | #define nMATCH_EN_3_5 0x0 | ||
| 2174 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ | 1826 | #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ |
| 2175 | #define nMATCH_EN_3_6 0x0 | ||
| 2176 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ | 1827 | #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ |
| 2177 | #define nMATCH_EN_3_7 0x0 | ||
| 2178 | 1828 | ||
| 2179 | /* Bit masks for MXVR_FRAME_CNT_0 */ | 1829 | /* Bit masks for MXVR_FRAME_CNT_0 */ |
| 2180 | 1830 | ||
| @@ -2188,226 +1838,166 @@ | |||
| 2188 | 1838 | ||
| 2189 | #define TX_CH0 0x3f /* Transmit Channel 0 */ | 1839 | #define TX_CH0 0x3f /* Transmit Channel 0 */ |
| 2190 | #define MUTE_CH0 0x80 /* Mute Channel 0 */ | 1840 | #define MUTE_CH0 0x80 /* Mute Channel 0 */ |
| 2191 | #define nMUTE_CH0 0x0 | ||
| 2192 | #define TX_CH1 0x3f00 /* Transmit Channel 0 */ | 1841 | #define TX_CH1 0x3f00 /* Transmit Channel 0 */ |
| 2193 | #define MUTE_CH1 0x8000 /* Mute Channel 0 */ | 1842 | #define MUTE_CH1 0x8000 /* Mute Channel 0 */ |
| 2194 | #define nMUTE_CH1 0x0 | ||
| 2195 | #define TX_CH2 0x3f0000 /* Transmit Channel 0 */ | 1843 | #define TX_CH2 0x3f0000 /* Transmit Channel 0 */ |
| 2196 | #define MUTE_CH2 0x800000 /* Mute Channel 0 */ | 1844 | #define MUTE_CH2 0x800000 /* Mute Channel 0 */ |
| 2197 | #define nMUTE_CH2 0x0 | ||
| 2198 | #define TX_CH3 0x3f000000 /* Transmit Channel 0 */ | 1845 | #define TX_CH3 0x3f000000 /* Transmit Channel 0 */ |
| 2199 | #define MUTE_CH3 0x80000000 /* Mute Channel 0 */ | 1846 | #define MUTE_CH3 0x80000000 /* Mute Channel 0 */ |
| 2200 | #define nMUTE_CH3 0x0 | ||
| 2201 | 1847 | ||
| 2202 | /* Bit masks for MXVR_ROUTING_1 */ | 1848 | /* Bit masks for MXVR_ROUTING_1 */ |
| 2203 | 1849 | ||
| 2204 | #define TX_CH4 0x3f /* Transmit Channel 4 */ | 1850 | #define TX_CH4 0x3f /* Transmit Channel 4 */ |
| 2205 | #define MUTE_CH4 0x80 /* Mute Channel 4 */ | 1851 | #define MUTE_CH4 0x80 /* Mute Channel 4 */ |
| 2206 | #define nMUTE_CH4 0x0 | ||
| 2207 | #define TX_CH5 0x3f00 /* Transmit Channel 5 */ | 1852 | #define TX_CH5 0x3f00 /* Transmit Channel 5 */ |
| 2208 | #define MUTE_CH5 0x8000 /* Mute Channel 5 */ | 1853 | #define MUTE_CH5 0x8000 /* Mute Channel 5 */ |
| 2209 | #define nMUTE_CH5 0x0 | ||
| 2210 | #define TX_CH6 0x3f0000 /* Transmit Channel 6 */ | 1854 | #define TX_CH6 0x3f0000 /* Transmit Channel 6 */ |
| 2211 | #define MUTE_CH6 0x800000 /* Mute Channel 6 */ | 1855 | #define MUTE_CH6 0x800000 /* Mute Channel 6 */ |
| 2212 | #define nMUTE_CH6 0x0 | ||
| 2213 | #define TX_CH7 0x3f000000 /* Transmit Channel 7 */ | 1856 | #define TX_CH7 0x3f000000 /* Transmit Channel 7 */ |
| 2214 | #define MUTE_CH7 0x80000000 /* Mute Channel 7 */ | 1857 | #define MUTE_CH7 0x80000000 /* Mute Channel 7 */ |
| 2215 | #define nMUTE_CH7 0x0 | ||
| 2216 | 1858 | ||
| 2217 | /* Bit masks for MXVR_ROUTING_2 */ | 1859 | /* Bit masks for MXVR_ROUTING_2 */ |
| 2218 | 1860 | ||
| 2219 | #define TX_CH8 0x3f /* Transmit Channel 8 */ | 1861 | #define TX_CH8 0x3f /* Transmit Channel 8 */ |
| 2220 | #define MUTE_CH8 0x80 /* Mute Channel 8 */ | 1862 | #define MUTE_CH8 0x80 /* Mute Channel 8 */ |
| 2221 | #define nMUTE_CH8 0x0 | ||
| 2222 | #define TX_CH9 0x3f00 /* Transmit Channel 9 */ | 1863 | #define TX_CH9 0x3f00 /* Transmit Channel 9 */ |
| 2223 | #define MUTE_CH9 0x8000 /* Mute Channel 9 */ | 1864 | #define MUTE_CH9 0x8000 /* Mute Channel 9 */ |
| 2224 | #define nMUTE_CH9 0x0 | ||
| 2225 | #define TX_CH10 0x3f0000 /* Transmit Channel 10 */ | 1865 | #define TX_CH10 0x3f0000 /* Transmit Channel 10 */ |
| 2226 | #define MUTE_CH10 0x800000 /* Mute Channel 10 */ | 1866 | #define MUTE_CH10 0x800000 /* Mute Channel 10 */ |
| 2227 | #define nMUTE_CH10 0x0 | ||
| 2228 | #define TX_CH11 0x3f000000 /* Transmit Channel 11 */ | 1867 | #define TX_CH11 0x3f000000 /* Transmit Channel 11 */ |
| 2229 | #define MUTE_CH11 0x80000000 /* Mute Channel 11 */ | 1868 | #define MUTE_CH11 0x80000000 /* Mute Channel 11 */ |
| 2230 | #define nMUTE_CH11 0x0 | ||
| 2231 | 1869 | ||
| 2232 | /* Bit masks for MXVR_ROUTING_3 */ | 1870 | /* Bit masks for MXVR_ROUTING_3 */ |
| 2233 | 1871 | ||
| 2234 | #define TX_CH12 0x3f /* Transmit Channel 12 */ | 1872 | #define TX_CH12 0x3f /* Transmit Channel 12 */ |
| 2235 | #define MUTE_CH12 0x80 /* Mute Channel 12 */ | 1873 | #define MUTE_CH12 0x80 /* Mute Channel 12 */ |
| 2236 | #define nMUTE_CH12 0x0 | ||
| 2237 | #define TX_CH13 0x3f00 /* Transmit Channel 13 */ | 1874 | #define TX_CH13 0x3f00 /* Transmit Channel 13 */ |
| 2238 | #define MUTE_CH13 0x8000 /* Mute Channel 13 */ | 1875 | #define MUTE_CH13 0x8000 /* Mute Channel 13 */ |
| 2239 | #define nMUTE_CH13 0x0 | ||
| 2240 | #define TX_CH14 0x3f0000 /* Transmit Channel 14 */ | 1876 | #define TX_CH14 0x3f0000 /* Transmit Channel 14 */ |
| 2241 | #define MUTE_CH14 0x800000 /* Mute Channel 14 */ | 1877 | #define MUTE_CH14 0x800000 /* Mute Channel 14 */ |
| 2242 | #define nMUTE_CH14 0x0 | ||
| 2243 | #define TX_CH15 0x3f000000 /* Transmit Channel 15 */ | 1878 | #define TX_CH15 0x3f000000 /* Transmit Channel 15 */ |
| 2244 | #define MUTE_CH15 0x80000000 /* Mute Channel 15 */ | 1879 | #define MUTE_CH15 0x80000000 /* Mute Channel 15 */ |
| 2245 | #define nMUTE_CH15 0x0 | ||
| 2246 | 1880 | ||
| 2247 | /* Bit masks for MXVR_ROUTING_4 */ | 1881 | /* Bit masks for MXVR_ROUTING_4 */ |
| 2248 | 1882 | ||
| 2249 | #define TX_CH16 0x3f /* Transmit Channel 16 */ | 1883 | #define TX_CH16 0x3f /* Transmit Channel 16 */ |
| 2250 | #define MUTE_CH16 0x80 /* Mute Channel 16 */ | 1884 | #define MUTE_CH16 0x80 /* Mute Channel 16 */ |
| 2251 | #define nMUTE_CH16 0x0 | ||
| 2252 | #define TX_CH17 0x3f00 /* Transmit Channel 17 */ | 1885 | #define TX_CH17 0x3f00 /* Transmit Channel 17 */ |
| 2253 | #define MUTE_CH17 0x8000 /* Mute Channel 17 */ | 1886 | #define MUTE_CH17 0x8000 /* Mute Channel 17 */ |
| 2254 | #define nMUTE_CH17 0x0 | ||
| 2255 | #define TX_CH18 0x3f0000 /* Transmit Channel 18 */ | 1887 | #define TX_CH18 0x3f0000 /* Transmit Channel 18 */ |
| 2256 | #define MUTE_CH18 0x800000 /* Mute Channel 18 */ | 1888 | #define MUTE_CH18 0x800000 /* Mute Channel 18 */ |
| 2257 | #define nMUTE_CH18 0x0 | ||
| 2258 | #define TX_CH19 0x3f000000 /* Transmit Channel 19 */ | 1889 | #define TX_CH19 0x3f000000 /* Transmit Channel 19 */ |
| 2259 | #define MUTE_CH19 0x80000000 /* Mute Channel 19 */ | 1890 | #define MUTE_CH19 0x80000000 /* Mute Channel 19 */ |
| 2260 | #define nMUTE_CH19 0x0 | ||
| 2261 | 1891 | ||
| 2262 | /* Bit masks for MXVR_ROUTING_5 */ | 1892 | /* Bit masks for MXVR_ROUTING_5 */ |
| 2263 | 1893 | ||
| 2264 | #define TX_CH20 0x3f /* Transmit Channel 20 */ | 1894 | #define TX_CH20 0x3f /* Transmit Channel 20 */ |
| 2265 | #define MUTE_CH20 0x80 /* Mute Channel 20 */ | 1895 | #define MUTE_CH20 0x80 /* Mute Channel 20 */ |
| 2266 | #define nMUTE_CH20 0x0 | ||
| 2267 | #define TX_CH21 0x3f00 /* Transmit Channel 21 */ | 1896 | #define TX_CH21 0x3f00 /* Transmit Channel 21 */ |
| 2268 | #define MUTE_CH21 0x8000 /* Mute Channel 21 */ | 1897 | #define MUTE_CH21 0x8000 /* Mute Channel 21 */ |
| 2269 | #define nMUTE_CH21 0x0 | ||
| 2270 | #define TX_CH22 0x3f0000 /* Transmit Channel 22 */ | 1898 | #define TX_CH22 0x3f0000 /* Transmit Channel 22 */ |
| 2271 | #define MUTE_CH22 0x800000 /* Mute Channel 22 */ | 1899 | #define MUTE_CH22 0x800000 /* Mute Channel 22 */ |
| 2272 | #define nMUTE_CH22 0x0 | ||
| 2273 | #define TX_CH23 0x3f000000 /* Transmit Channel 23 */ | 1900 | #define TX_CH23 0x3f000000 /* Transmit Channel 23 */ |
| 2274 | #define MUTE_CH23 0x80000000 /* Mute Channel 23 */ | 1901 | #define MUTE_CH23 0x80000000 /* Mute Channel 23 */ |
| 2275 | #define nMUTE_CH23 0x0 | ||
| 2276 | 1902 | ||
| 2277 | /* Bit masks for MXVR_ROUTING_6 */ | 1903 | /* Bit masks for MXVR_ROUTING_6 */ |
| 2278 | 1904 | ||
| 2279 | #define TX_CH24 0x3f /* Transmit Channel 24 */ | 1905 | #define TX_CH24 0x3f /* Transmit Channel 24 */ |
| 2280 | #define MUTE_CH24 0x80 /* Mute Channel 24 */ | 1906 | #define MUTE_CH24 0x80 /* Mute Channel 24 */ |
| 2281 | #define nMUTE_CH24 0x0 | ||
| 2282 | #define TX_CH25 0x3f00 /* Transmit Channel 25 */ | 1907 | #define TX_CH25 0x3f00 /* Transmit Channel 25 */ |
| 2283 | #define MUTE_CH25 0x8000 /* Mute Channel 25 */ | 1908 | #define MUTE_CH25 0x8000 /* Mute Channel 25 */ |
| 2284 | #define nMUTE_CH25 0x0 | ||
| 2285 | #define TX_CH26 0x3f0000 /* Transmit Channel 26 */ | 1909 | #define TX_CH26 0x3f0000 /* Transmit Channel 26 */ |
| 2286 | #define MUTE_CH26 0x800000 /* Mute Channel 26 */ | 1910 | #define MUTE_CH26 0x800000 /* Mute Channel 26 */ |
| 2287 | #define nMUTE_CH26 0x0 | ||
| 2288 | #define TX_CH27 0x3f000000 /* Transmit Channel 27 */ | 1911 | #define TX_CH27 0x3f000000 /* Transmit Channel 27 */ |
| 2289 | #define MUTE_CH27 0x80000000 /* Mute Channel 27 */ | 1912 | #define MUTE_CH27 0x80000000 /* Mute Channel 27 */ |
| 2290 | #define nMUTE_CH27 0x0 | ||
| 2291 | 1913 | ||
| 2292 | /* Bit masks for MXVR_ROUTING_7 */ | 1914 | /* Bit masks for MXVR_ROUTING_7 */ |
| 2293 | 1915 | ||
| 2294 | #define TX_CH28 0x3f /* Transmit Channel 28 */ | 1916 | #define TX_CH28 0x3f /* Transmit Channel 28 */ |
| 2295 | #define MUTE_CH28 0x80 /* Mute Channel 28 */ | 1917 | #define MUTE_CH28 0x80 /* Mute Channel 28 */ |
| 2296 | #define nMUTE_CH28 0x0 | ||
| 2297 | #define TX_CH29 0x3f00 /* Transmit Channel 29 */ | 1918 | #define TX_CH29 0x3f00 /* Transmit Channel 29 */ |
| 2298 | #define MUTE_CH29 0x8000 /* Mute Channel 29 */ | 1919 | #define MUTE_CH29 0x8000 /* Mute Channel 29 */ |
| 2299 | #define nMUTE_CH29 0x0 | ||
| 2300 | #define TX_CH30 0x3f0000 /* Transmit Channel 30 */ | 1920 | #define TX_CH30 0x3f0000 /* Transmit Channel 30 */ |
| 2301 | #define MUTE_CH30 0x800000 /* Mute Channel 30 */ | 1921 | #define MUTE_CH30 0x800000 /* Mute Channel 30 */ |
| 2302 | #define nMUTE_CH30 0x0 | ||
| 2303 | #define TX_CH31 0x3f000000 /* Transmit Channel 31 */ | 1922 | #define TX_CH31 0x3f000000 /* Transmit Channel 31 */ |
| 2304 | #define MUTE_CH31 0x80000000 /* Mute Channel 31 */ | 1923 | #define MUTE_CH31 0x80000000 /* Mute Channel 31 */ |
| 2305 | #define nMUTE_CH31 0x0 | ||
| 2306 | 1924 | ||
| 2307 | /* Bit masks for MXVR_ROUTING_8 */ | 1925 | /* Bit masks for MXVR_ROUTING_8 */ |
| 2308 | 1926 | ||
| 2309 | #define TX_CH32 0x3f /* Transmit Channel 32 */ | 1927 | #define TX_CH32 0x3f /* Transmit Channel 32 */ |
| 2310 | #define MUTE_CH32 0x80 /* Mute Channel 32 */ | 1928 | #define MUTE_CH32 0x80 /* Mute Channel 32 */ |
| 2311 | #define nMUTE_CH32 0x0 | ||
| 2312 | #define TX_CH33 0x3f00 /* Transmit Channel 33 */ | 1929 | #define TX_CH33 0x3f00 /* Transmit Channel 33 */ |
| 2313 | #define MUTE_CH33 0x8000 /* Mute Channel 33 */ | 1930 | #define MUTE_CH33 0x8000 /* Mute Channel 33 */ |
| 2314 | #define nMUTE_CH33 0x0 | ||
| 2315 | #define TX_CH34 0x3f0000 /* Transmit Channel 34 */ | 1931 | #define TX_CH34 0x3f0000 /* Transmit Channel 34 */ |
| 2316 | #define MUTE_CH34 0x800000 /* Mute Channel 34 */ | 1932 | #define MUTE_CH34 0x800000 /* Mute Channel 34 */ |
| 2317 | #define nMUTE_CH34 0x0 | ||
| 2318 | #define TX_CH35 0x3f000000 /* Transmit Channel 35 */ | 1933 | #define TX_CH35 0x3f000000 /* Transmit Channel 35 */ |
| 2319 | #define MUTE_CH35 0x80000000 /* Mute Channel 35 */ | 1934 | #define MUTE_CH35 0x80000000 /* Mute Channel 35 */ |
| 2320 | #define nMUTE_CH35 0x0 | ||
| 2321 | 1935 | ||
| 2322 | /* Bit masks for MXVR_ROUTING_9 */ | 1936 | /* Bit masks for MXVR_ROUTING_9 */ |
| 2323 | 1937 | ||
| 2324 | #define TX_CH36 0x3f /* Transmit Channel 36 */ | 1938 | #define TX_CH36 0x3f /* Transmit Channel 36 */ |
| 2325 | #define MUTE_CH36 0x80 /* Mute Channel 36 */ | 1939 | #define MUTE_CH36 0x80 /* Mute Channel 36 */ |
| 2326 | #define nMUTE_CH36 0x0 | ||
| 2327 | #define TX_CH37 0x3f00 /* Transmit Channel 37 */ | 1940 | #define TX_CH37 0x3f00 /* Transmit Channel 37 */ |
| 2328 | #define MUTE_CH37 0x8000 /* Mute Channel 37 */ | 1941 | #define MUTE_CH37 0x8000 /* Mute Channel 37 */ |
| 2329 | #define nMUTE_CH37 0x0 | ||
| 2330 | #define TX_CH38 0x3f0000 /* Transmit Channel 38 */ | 1942 | #define TX_CH38 0x3f0000 /* Transmit Channel 38 */ |
| 2331 | #define MUTE_CH38 0x800000 /* Mute Channel 38 */ | 1943 | #define MUTE_CH38 0x800000 /* Mute Channel 38 */ |
| 2332 | #define nMUTE_CH38 0x0 | ||
| 2333 | #define TX_CH39 0x3f000000 /* Transmit Channel 39 */ | 1944 | #define TX_CH39 0x3f000000 /* Transmit Channel 39 */ |
| 2334 | #define MUTE_CH39 0x80000000 /* Mute Channel 39 */ | 1945 | #define MUTE_CH39 0x80000000 /* Mute Channel 39 */ |
| 2335 | #define nMUTE_CH39 0x0 | ||
| 2336 | 1946 | ||
| 2337 | /* Bit masks for MXVR_ROUTING_10 */ | 1947 | /* Bit masks for MXVR_ROUTING_10 */ |
| 2338 | 1948 | ||
| 2339 | #define TX_CH40 0x3f /* Transmit Channel 40 */ | 1949 | #define TX_CH40 0x3f /* Transmit Channel 40 */ |
| 2340 | #define MUTE_CH40 0x80 /* Mute Channel 40 */ | 1950 | #define MUTE_CH40 0x80 /* Mute Channel 40 */ |
| 2341 | #define nMUTE_CH40 0x0 | ||
| 2342 | #define TX_CH41 0x3f00 /* Transmit Channel 41 */ | 1951 | #define TX_CH41 0x3f00 /* Transmit Channel 41 */ |
| 2343 | #define MUTE_CH41 0x8000 /* Mute Channel 41 */ | 1952 | #define MUTE_CH41 0x8000 /* Mute Channel 41 */ |
| 2344 | #define nMUTE_CH41 0x0 | ||
| 2345 | #define TX_CH42 0x3f0000 /* Transmit Channel 42 */ | 1953 | #define TX_CH42 0x3f0000 /* Transmit Channel 42 */ |
| 2346 | #define MUTE_CH42 0x800000 /* Mute Channel 42 */ | 1954 | #define MUTE_CH42 0x800000 /* Mute Channel 42 */ |
| 2347 | #define nMUTE_CH42 0x0 | ||
| 2348 | #define TX_CH43 0x3f000000 /* Transmit Channel 43 */ | 1955 | #define TX_CH43 0x3f000000 /* Transmit Channel 43 */ |
| 2349 | #define MUTE_CH43 0x80000000 /* Mute Channel 43 */ | 1956 | #define MUTE_CH43 0x80000000 /* Mute Channel 43 */ |
| 2350 | #define nMUTE_CH43 0x0 | ||
| 2351 | 1957 | ||
| 2352 | /* Bit masks for MXVR_ROUTING_11 */ | 1958 | /* Bit masks for MXVR_ROUTING_11 */ |
| 2353 | 1959 | ||
| 2354 | #define TX_CH44 0x3f /* Transmit Channel 44 */ | 1960 | #define TX_CH44 0x3f /* Transmit Channel 44 */ |
| 2355 | #define MUTE_CH44 0x80 /* Mute Channel 44 */ | 1961 | #define MUTE_CH44 0x80 /* Mute Channel 44 */ |
| 2356 | #define nMUTE_CH44 0x0 | ||
| 2357 | #define TX_CH45 0x3f00 /* Transmit Channel 45 */ | 1962 | #define TX_CH45 0x3f00 /* Transmit Channel 45 */ |
| 2358 | #define MUTE_CH45 0x8000 /* Mute Channel 45 */ | 1963 | #define MUTE_CH45 0x8000 /* Mute Channel 45 */ |
| 2359 | #define nMUTE_CH45 0x0 | ||
| 2360 | #define TX_CH46 0x3f0000 /* Transmit Channel 46 */ | 1964 | #define TX_CH46 0x3f0000 /* Transmit Channel 46 */ |
| 2361 | #define MUTE_CH46 0x800000 /* Mute Channel 46 */ | 1965 | #define MUTE_CH46 0x800000 /* Mute Channel 46 */ |
| 2362 | #define nMUTE_CH46 0x0 | ||
| 2363 | #define TX_CH47 0x3f000000 /* Transmit Channel 47 */ | 1966 | #define TX_CH47 0x3f000000 /* Transmit Channel 47 */ |
| 2364 | #define MUTE_CH47 0x80000000 /* Mute Channel 47 */ | 1967 | #define MUTE_CH47 0x80000000 /* Mute Channel 47 */ |
| 2365 | #define nMUTE_CH47 0x0 | ||
| 2366 | 1968 | ||
| 2367 | /* Bit masks for MXVR_ROUTING_12 */ | 1969 | /* Bit masks for MXVR_ROUTING_12 */ |
| 2368 | 1970 | ||
| 2369 | #define TX_CH48 0x3f /* Transmit Channel 48 */ | 1971 | #define TX_CH48 0x3f /* Transmit Channel 48 */ |
| 2370 | #define MUTE_CH48 0x80 /* Mute Channel 48 */ | 1972 | #define MUTE_CH48 0x80 /* Mute Channel 48 */ |
| 2371 | #define nMUTE_CH48 0x0 | ||
| 2372 | #define TX_CH49 0x3f00 /* Transmit Channel 49 */ | 1973 | #define TX_CH49 0x3f00 /* Transmit Channel 49 */ |
| 2373 | #define MUTE_CH49 0x8000 /* Mute Channel 49 */ | 1974 | #define MUTE_CH49 0x8000 /* Mute Channel 49 */ |
| 2374 | #define nMUTE_CH49 0x0 | ||
| 2375 | #define TX_CH50 0x3f0000 /* Transmit Channel 50 */ | 1975 | #define TX_CH50 0x3f0000 /* Transmit Channel 50 */ |
| 2376 | #define MUTE_CH50 0x800000 /* Mute Channel 50 */ | 1976 | #define MUTE_CH50 0x800000 /* Mute Channel 50 */ |
| 2377 | #define nMUTE_CH50 0x0 | ||
| 2378 | #define TX_CH51 0x3f000000 /* Transmit Channel 51 */ | 1977 | #define TX_CH51 0x3f000000 /* Transmit Channel 51 */ |
| 2379 | #define MUTE_CH51 0x80000000 /* Mute Channel 51 */ | 1978 | #define MUTE_CH51 0x80000000 /* Mute Channel 51 */ |
| 2380 | #define nMUTE_CH51 0x0 | ||
| 2381 | 1979 | ||
| 2382 | /* Bit masks for MXVR_ROUTING_13 */ | 1980 | /* Bit masks for MXVR_ROUTING_13 */ |
| 2383 | 1981 | ||
| 2384 | #define TX_CH52 0x3f /* Transmit Channel 52 */ | 1982 | #define TX_CH52 0x3f /* Transmit Channel 52 */ |
| 2385 | #define MUTE_CH52 0x80 /* Mute Channel 52 */ | 1983 | #define MUTE_CH52 0x80 /* Mute Channel 52 */ |
| 2386 | #define nMUTE_CH52 0x0 | ||
| 2387 | #define TX_CH53 0x3f00 /* Transmit Channel 53 */ | 1984 | #define TX_CH53 0x3f00 /* Transmit Channel 53 */ |
| 2388 | #define MUTE_CH53 0x8000 /* Mute Channel 53 */ | 1985 | #define MUTE_CH53 0x8000 /* Mute Channel 53 */ |
| 2389 | #define nMUTE_CH53 0x0 | ||
| 2390 | #define TX_CH54 0x3f0000 /* Transmit Channel 54 */ | 1986 | #define TX_CH54 0x3f0000 /* Transmit Channel 54 */ |
| 2391 | #define MUTE_CH54 0x800000 /* Mute Channel 54 */ | 1987 | #define MUTE_CH54 0x800000 /* Mute Channel 54 */ |
| 2392 | #define nMUTE_CH54 0x0 | ||
| 2393 | #define TX_CH55 0x3f000000 /* Transmit Channel 55 */ | 1988 | #define TX_CH55 0x3f000000 /* Transmit Channel 55 */ |
| 2394 | #define MUTE_CH55 0x80000000 /* Mute Channel 55 */ | 1989 | #define MUTE_CH55 0x80000000 /* Mute Channel 55 */ |
| 2395 | #define nMUTE_CH55 0x0 | ||
| 2396 | 1990 | ||
| 2397 | /* Bit masks for MXVR_ROUTING_14 */ | 1991 | /* Bit masks for MXVR_ROUTING_14 */ |
| 2398 | 1992 | ||
| 2399 | #define TX_CH56 0x3f /* Transmit Channel 56 */ | 1993 | #define TX_CH56 0x3f /* Transmit Channel 56 */ |
| 2400 | #define MUTE_CH56 0x80 /* Mute Channel 56 */ | 1994 | #define MUTE_CH56 0x80 /* Mute Channel 56 */ |
| 2401 | #define nMUTE_CH56 0x0 | ||
| 2402 | #define TX_CH57 0x3f00 /* Transmit Channel 57 */ | 1995 | #define TX_CH57 0x3f00 /* Transmit Channel 57 */ |
| 2403 | #define MUTE_CH57 0x8000 /* Mute Channel 57 */ | 1996 | #define MUTE_CH57 0x8000 /* Mute Channel 57 */ |
| 2404 | #define nMUTE_CH57 0x0 | ||
| 2405 | #define TX_CH58 0x3f0000 /* Transmit Channel 58 */ | 1997 | #define TX_CH58 0x3f0000 /* Transmit Channel 58 */ |
| 2406 | #define MUTE_CH58 0x800000 /* Mute Channel 58 */ | 1998 | #define MUTE_CH58 0x800000 /* Mute Channel 58 */ |
| 2407 | #define nMUTE_CH58 0x0 | ||
| 2408 | #define TX_CH59 0x3f000000 /* Transmit Channel 59 */ | 1999 | #define TX_CH59 0x3f000000 /* Transmit Channel 59 */ |
| 2409 | #define MUTE_CH59 0x80000000 /* Mute Channel 59 */ | 2000 | #define MUTE_CH59 0x80000000 /* Mute Channel 59 */ |
| 2410 | #define nMUTE_CH59 0x0 | ||
| 2411 | 2001 | ||
| 2412 | /* Bit masks for MXVR_BLOCK_CNT */ | 2002 | /* Bit masks for MXVR_BLOCK_CNT */ |
| 2413 | 2003 | ||
| @@ -2416,53 +2006,37 @@ | |||
| 2416 | /* Bit masks for MXVR_CLK_CTL */ | 2006 | /* Bit masks for MXVR_CLK_CTL */ |
| 2417 | 2007 | ||
| 2418 | #define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ | 2008 | #define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ |
| 2419 | #define nMXTALCEN 0x0 | ||
| 2420 | #define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ | 2009 | #define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ |
| 2421 | #define nMXTALFEN 0x0 | ||
| 2422 | #define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ | 2010 | #define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ |
| 2423 | #define CLKX3SEL 0x80 /* Clock Generation Source Select */ | 2011 | #define CLKX3SEL 0x80 /* Clock Generation Source Select */ |
| 2424 | #define nCLKX3SEL 0x0 | ||
| 2425 | #define MMCLKEN 0x100 /* Master Clock Enable */ | 2012 | #define MMCLKEN 0x100 /* Master Clock Enable */ |
| 2426 | #define nMMCLKEN 0x0 | ||
| 2427 | #define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ | 2013 | #define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ |
| 2428 | #define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ | 2014 | #define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ |
| 2429 | #define MBCLKEN 0x10000 /* Bit Clock Enable */ | 2015 | #define MBCLKEN 0x10000 /* Bit Clock Enable */ |
| 2430 | #define nMBCLKEN 0x0 | ||
| 2431 | #define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ | 2016 | #define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ |
| 2432 | #define INVRX 0x800000 /* Invert Receive Data */ | 2017 | #define INVRX 0x800000 /* Invert Receive Data */ |
| 2433 | #define nINVRX 0x0 | ||
| 2434 | #define MFSEN 0x1000000 /* Frame Sync Enable */ | 2018 | #define MFSEN 0x1000000 /* Frame Sync Enable */ |
| 2435 | #define nMFSEN 0x0 | ||
| 2436 | #define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ | 2019 | #define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ |
| 2437 | #define MFSSEL 0x60000000 /* Frame Sync Select */ | 2020 | #define MFSSEL 0x60000000 /* Frame Sync Select */ |
| 2438 | #define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ | 2021 | #define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ |
| 2439 | #define nMFSSYNC 0x0 | ||
| 2440 | 2022 | ||
| 2441 | /* Bit masks for MXVR_CDRPLL_CTL */ | 2023 | /* Bit masks for MXVR_CDRPLL_CTL */ |
| 2442 | 2024 | ||
| 2443 | #define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ | 2025 | #define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ |
| 2444 | #define nCDRSMEN 0x0 | ||
| 2445 | #define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ | 2026 | #define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ |
| 2446 | #define nCDRRSTB 0x0 | ||
| 2447 | #define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ | 2027 | #define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ |
| 2448 | #define nCDRSVCO 0x0 | ||
| 2449 | #define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ | 2028 | #define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ |
| 2450 | #define nCDRMODE 0x0 | ||
| 2451 | #define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ | 2029 | #define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ |
| 2452 | #define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ | 2030 | #define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ |
| 2453 | #define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ | 2031 | #define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ |
| 2454 | #define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ | 2032 | #define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ |
| 2455 | #define nCDRSHPEN 0x0 | ||
| 2456 | #define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ | 2033 | #define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ |
| 2457 | 2034 | ||
| 2458 | /* Bit masks for MXVR_FMPLL_CTL */ | 2035 | /* Bit masks for MXVR_FMPLL_CTL */ |
| 2459 | 2036 | ||
| 2460 | #define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ | 2037 | #define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ |
| 2461 | #define nFMSMEN 0x0 | ||
| 2462 | #define FMRSTB 0x2 /* MXVR FMPLL Reset */ | 2038 | #define FMRSTB 0x2 /* MXVR FMPLL Reset */ |
| 2463 | #define nFMRSTB 0x0 | ||
| 2464 | #define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ | 2039 | #define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ |
| 2465 | #define nFMSVCO 0x0 | ||
| 2466 | #define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ | 2040 | #define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ |
| 2467 | #define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ | 2041 | #define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ |
| 2468 | #define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ | 2042 | #define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ |
| @@ -2470,15 +2044,10 @@ | |||
| 2470 | /* Bit masks for MXVR_PIN_CTL */ | 2044 | /* Bit masks for MXVR_PIN_CTL */ |
| 2471 | 2045 | ||
| 2472 | #define MTXONBOD 0x1 /* MTXONB Open Drain Select */ | 2046 | #define MTXONBOD 0x1 /* MTXONB Open Drain Select */ |
| 2473 | #define nMTXONBOD 0x0 | ||
| 2474 | #define MTXONBG 0x2 /* MTXONB Gates MTX Select */ | 2047 | #define MTXONBG 0x2 /* MTXONB Gates MTX Select */ |
| 2475 | #define nMTXONBG 0x0 | ||
| 2476 | #define MFSOE 0x10 /* MFS Output Enable */ | 2048 | #define MFSOE 0x10 /* MFS Output Enable */ |
| 2477 | #define nMFSOE 0x0 | ||
| 2478 | #define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ | 2049 | #define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ |
| 2479 | #define nMFSGPSEL 0x0 | ||
| 2480 | #define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ | 2050 | #define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ |
| 2481 | #define nMFSGPDAT 0x0 | ||
| 2482 | 2051 | ||
| 2483 | /* Bit masks for MXVR_SCLK_CNT */ | 2052 | /* Bit masks for MXVR_SCLK_CNT */ |
| 2484 | 2053 | ||
| @@ -2487,7 +2056,6 @@ | |||
| 2487 | /* Bit masks for KPAD_CTL */ | 2056 | /* Bit masks for KPAD_CTL */ |
| 2488 | 2057 | ||
| 2489 | #define KPAD_EN 0x1 /* Keypad Enable */ | 2058 | #define KPAD_EN 0x1 /* Keypad Enable */ |
| 2490 | #define nKPAD_EN 0x0 | ||
| 2491 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ | 2059 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ |
| 2492 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ | 2060 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ |
| 2493 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ | 2061 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ |
| @@ -2509,29 +2077,21 @@ | |||
| 2509 | /* Bit masks for KPAD_STAT */ | 2077 | /* Bit masks for KPAD_STAT */ |
| 2510 | 2078 | ||
| 2511 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ | 2079 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ |
| 2512 | #define nKPAD_IRQ 0x0 | ||
| 2513 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ | 2080 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ |
| 2514 | #define KPAD_PRESSED 0x8 /* Key press current status */ | 2081 | #define KPAD_PRESSED 0x8 /* Key press current status */ |
| 2515 | #define nKPAD_PRESSED 0x0 | ||
| 2516 | 2082 | ||
| 2517 | /* Bit masks for KPAD_SOFTEVAL */ | 2083 | /* Bit masks for KPAD_SOFTEVAL */ |
| 2518 | 2084 | ||
| 2519 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ | 2085 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ |
| 2520 | #define nKPAD_SOFTEVAL_E 0x0 | ||
| 2521 | 2086 | ||
| 2522 | /* Bit masks for SDH_COMMAND */ | 2087 | /* Bit masks for SDH_COMMAND */ |
| 2523 | 2088 | ||
| 2524 | #define CMD_IDX 0x3f /* Command Index */ | 2089 | #define CMD_IDX 0x3f /* Command Index */ |
| 2525 | #define CMD_RSP 0x40 /* Response */ | 2090 | #define CMD_RSP 0x40 /* Response */ |
| 2526 | #define nCMD_RSP 0x0 | ||
| 2527 | #define CMD_L_RSP 0x80 /* Long Response */ | 2091 | #define CMD_L_RSP 0x80 /* Long Response */ |
| 2528 | #define nCMD_L_RSP 0x0 | ||
| 2529 | #define CMD_INT_E 0x100 /* Command Interrupt */ | 2092 | #define CMD_INT_E 0x100 /* Command Interrupt */ |
| 2530 | #define nCMD_INT_E 0x0 | ||
| 2531 | #define CMD_PEND_E 0x200 /* Command Pending */ | 2093 | #define CMD_PEND_E 0x200 /* Command Pending */ |
| 2532 | #define nCMD_PEND_E 0x0 | ||
| 2533 | #define CMD_E 0x400 /* Command Enable */ | 2094 | #define CMD_E 0x400 /* Command Enable */ |
| 2534 | #define nCMD_E 0x0 | ||
| 2535 | 2095 | ||
| 2536 | /* Bit masks for SDH_PWR_CTL */ | 2096 | /* Bit masks for SDH_PWR_CTL */ |
| 2537 | 2097 | ||
| @@ -2540,21 +2100,15 @@ | |||
| 2540 | #define TBD 0x3c /* TBD */ | 2100 | #define TBD 0x3c /* TBD */ |
| 2541 | #endif | 2101 | #endif |
| 2542 | #define SD_CMD_OD 0x40 /* Open Drain Output */ | 2102 | #define SD_CMD_OD 0x40 /* Open Drain Output */ |
| 2543 | #define nSD_CMD_OD 0x0 | ||
| 2544 | #define ROD_CTL 0x80 /* Rod Control */ | 2103 | #define ROD_CTL 0x80 /* Rod Control */ |
| 2545 | #define nROD_CTL 0x0 | ||
| 2546 | 2104 | ||
| 2547 | /* Bit masks for SDH_CLK_CTL */ | 2105 | /* Bit masks for SDH_CLK_CTL */ |
| 2548 | 2106 | ||
| 2549 | #define CLKDIV 0xff /* MC_CLK Divisor */ | 2107 | #define CLKDIV 0xff /* MC_CLK Divisor */ |
| 2550 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ | 2108 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ |
| 2551 | #define nCLK_E 0x0 | ||
| 2552 | #define PWR_SV_E 0x200 /* Power Save Enable */ | 2109 | #define PWR_SV_E 0x200 /* Power Save Enable */ |
| 2553 | #define nPWR_SV_E 0x0 | ||
| 2554 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | 2110 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ |
| 2555 | #define nCLKDIV_BYPASS 0x0 | ||
| 2556 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ | 2111 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ |
| 2557 | #define nWIDE_BUS 0x0 | ||
| 2558 | 2112 | ||
| 2559 | /* Bit masks for SDH_RESP_CMD */ | 2113 | /* Bit masks for SDH_RESP_CMD */ |
| 2560 | 2114 | ||
| @@ -2563,133 +2117,74 @@ | |||
| 2563 | /* Bit masks for SDH_DATA_CTL */ | 2117 | /* Bit masks for SDH_DATA_CTL */ |
| 2564 | 2118 | ||
| 2565 | #define DTX_E 0x1 /* Data Transfer Enable */ | 2119 | #define DTX_E 0x1 /* Data Transfer Enable */ |
| 2566 | #define nDTX_E 0x0 | ||
| 2567 | #define DTX_DIR 0x2 /* Data Transfer Direction */ | 2120 | #define DTX_DIR 0x2 /* Data Transfer Direction */ |
| 2568 | #define nDTX_DIR 0x0 | ||
| 2569 | #define DTX_MODE 0x4 /* Data Transfer Mode */ | 2121 | #define DTX_MODE 0x4 /* Data Transfer Mode */ |
| 2570 | #define nDTX_MODE 0x0 | ||
| 2571 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | 2122 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ |
| 2572 | #define nDTX_DMA_E 0x0 | ||
| 2573 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | 2123 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ |
| 2574 | 2124 | ||
| 2575 | /* Bit masks for SDH_STATUS */ | 2125 | /* Bit masks for SDH_STATUS */ |
| 2576 | 2126 | ||
| 2577 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | 2127 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ |
| 2578 | #define nCMD_CRC_FAIL 0x0 | ||
| 2579 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | 2128 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ |
| 2580 | #define nDAT_CRC_FAIL 0x0 | 2129 | #define CMD_TIME_OUT 0x4 /* CMD Time Out */ |
| 2581 | #define CMD_TIMEOUT 0x4 /* CMD Time Out */ | 2130 | #define DAT_TIME_OUT 0x8 /* Data Time Out */ |
| 2582 | #define nCMD_TIMEOUT 0x0 | ||
| 2583 | #define DAT_TIMEOUT 0x8 /* Data Time Out */ | ||
| 2584 | #define nDAT_TIMEOUT 0x0 | ||
| 2585 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | 2131 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ |
| 2586 | #define nTX_UNDERRUN 0x0 | ||
| 2587 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | 2132 | #define RX_OVERRUN 0x20 /* Receive Overrun */ |
| 2588 | #define nRX_OVERRUN 0x0 | ||
| 2589 | #define CMD_RESP_END 0x40 /* CMD Response End */ | 2133 | #define CMD_RESP_END 0x40 /* CMD Response End */ |
| 2590 | #define nCMD_RESP_END 0x0 | ||
| 2591 | #define CMD_SENT 0x80 /* CMD Sent */ | 2134 | #define CMD_SENT 0x80 /* CMD Sent */ |
| 2592 | #define nCMD_SENT 0x0 | ||
| 2593 | #define DAT_END 0x100 /* Data End */ | 2135 | #define DAT_END 0x100 /* Data End */ |
| 2594 | #define nDAT_END 0x0 | ||
| 2595 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | 2136 | #define START_BIT_ERR 0x200 /* Start Bit Error */ |
| 2596 | #define nSTART_BIT_ERR 0x0 | ||
| 2597 | #define DAT_BLK_END 0x400 /* Data Block End */ | 2137 | #define DAT_BLK_END 0x400 /* Data Block End */ |
| 2598 | #define nDAT_BLK_END 0x0 | ||
| 2599 | #define CMD_ACT 0x800 /* CMD Active */ | 2138 | #define CMD_ACT 0x800 /* CMD Active */ |
| 2600 | #define nCMD_ACT 0x0 | ||
| 2601 | #define TX_ACT 0x1000 /* Transmit Active */ | 2139 | #define TX_ACT 0x1000 /* Transmit Active */ |
| 2602 | #define nTX_ACT 0x0 | ||
| 2603 | #define RX_ACT 0x2000 /* Receive Active */ | 2140 | #define RX_ACT 0x2000 /* Receive Active */ |
| 2604 | #define nRX_ACT 0x0 | ||
| 2605 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | 2141 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ |
| 2606 | #define nTX_FIFO_STAT 0x0 | ||
| 2607 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | 2142 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ |
| 2608 | #define nRX_FIFO_STAT 0x0 | ||
| 2609 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | 2143 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ |
| 2610 | #define nTX_FIFO_FULL 0x0 | ||
| 2611 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | 2144 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ |
| 2612 | #define nRX_FIFO_FULL 0x0 | ||
| 2613 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | 2145 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ |
| 2614 | #define nTX_FIFO_ZERO 0x0 | ||
| 2615 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | 2146 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ |
| 2616 | #define nRX_DAT_ZERO 0x0 | ||
| 2617 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | 2147 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ |
| 2618 | #define nTX_DAT_RDY 0x0 | ||
| 2619 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | 2148 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ |
| 2620 | #define nRX_FIFO_RDY 0x0 | ||
| 2621 | 2149 | ||
| 2622 | /* Bit masks for SDH_STATUS_CLR */ | 2150 | /* Bit masks for SDH_STATUS_CLR */ |
| 2623 | 2151 | ||
| 2624 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | 2152 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ |
| 2625 | #define nCMD_CRC_FAIL_STAT 0x0 | ||
| 2626 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | 2153 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ |
| 2627 | #define nDAT_CRC_FAIL_STAT 0x0 | ||
| 2628 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | 2154 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ |
| 2629 | #define nCMD_TIMEOUT_STAT 0x0 | ||
| 2630 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | 2155 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ |
| 2631 | #define nDAT_TIMEOUT_STAT 0x0 | ||
| 2632 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | 2156 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ |
| 2633 | #define nTX_UNDERRUN_STAT 0x0 | ||
| 2634 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | 2157 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ |
| 2635 | #define nRX_OVERRUN_STAT 0x0 | ||
| 2636 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | 2158 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ |
| 2637 | #define nCMD_RESP_END_STAT 0x0 | ||
| 2638 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | 2159 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ |
| 2639 | #define nCMD_SENT_STAT 0x0 | ||
| 2640 | #define DAT_END_STAT 0x100 /* Data End Status */ | 2160 | #define DAT_END_STAT 0x100 /* Data End Status */ |
| 2641 | #define nDAT_END_STAT 0x0 | ||
| 2642 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | 2161 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ |
| 2643 | #define nSTART_BIT_ERR_STAT 0x0 | ||
| 2644 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | 2162 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ |
| 2645 | #define nDAT_BLK_END_STAT 0x0 | ||
| 2646 | 2163 | ||
| 2647 | /* Bit masks for SDH_MASK0 */ | 2164 | /* Bit masks for SDH_MASK0 */ |
| 2648 | 2165 | ||
| 2649 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | 2166 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ |
| 2650 | #define nCMD_CRC_FAIL_MASK 0x0 | ||
| 2651 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | 2167 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ |
| 2652 | #define nDAT_CRC_FAIL_MASK 0x0 | ||
| 2653 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | 2168 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ |
| 2654 | #define nCMD_TIMEOUT_MASK 0x0 | ||
| 2655 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | 2169 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ |
| 2656 | #define nDAT_TIMEOUT_MASK 0x0 | ||
| 2657 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | 2170 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ |
| 2658 | #define nTX_UNDERRUN_MASK 0x0 | ||
| 2659 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | 2171 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ |
| 2660 | #define nRX_OVERRUN_MASK 0x0 | ||
| 2661 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | 2172 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ |
| 2662 | #define nCMD_RESP_END_MASK 0x0 | ||
| 2663 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | 2173 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ |
| 2664 | #define nCMD_SENT_MASK 0x0 | ||
| 2665 | #define DAT_END_MASK 0x100 /* Data End Mask */ | 2174 | #define DAT_END_MASK 0x100 /* Data End Mask */ |
| 2666 | #define nDAT_END_MASK 0x0 | ||
| 2667 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | 2175 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ |
| 2668 | #define nSTART_BIT_ERR_MASK 0x0 | ||
| 2669 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | 2176 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ |
| 2670 | #define nDAT_BLK_END_MASK 0x0 | ||
| 2671 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | 2177 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ |
| 2672 | #define nCMD_ACT_MASK 0x0 | ||
| 2673 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | 2178 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ |
| 2674 | #define nTX_ACT_MASK 0x0 | ||
| 2675 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | 2179 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ |
| 2676 | #define nRX_ACT_MASK 0x0 | ||
| 2677 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | 2180 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ |
| 2678 | #define nTX_FIFO_STAT_MASK 0x0 | ||
| 2679 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | 2181 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ |
| 2680 | #define nRX_FIFO_STAT_MASK 0x0 | ||
| 2681 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | 2182 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ |
| 2682 | #define nTX_FIFO_FULL_MASK 0x0 | ||
| 2683 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | 2183 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ |
| 2684 | #define nRX_FIFO_FULL_MASK 0x0 | ||
| 2685 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | 2184 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ |
| 2686 | #define nTX_FIFO_ZERO_MASK 0x0 | ||
| 2687 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | 2185 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ |
| 2688 | #define nRX_DAT_ZERO_MASK 0x0 | ||
| 2689 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | 2186 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ |
| 2690 | #define nTX_DAT_RDY_MASK 0x0 | ||
| 2691 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | 2187 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ |
| 2692 | #define nRX_FIFO_RDY_MASK 0x0 | ||
| 2693 | 2188 | ||
| 2694 | /* Bit masks for SDH_FIFO_CNT */ | 2189 | /* Bit masks for SDH_FIFO_CNT */ |
| 2695 | 2190 | ||
| @@ -2698,73 +2193,47 @@ | |||
| 2698 | /* Bit masks for SDH_E_STATUS */ | 2193 | /* Bit masks for SDH_E_STATUS */ |
| 2699 | 2194 | ||
| 2700 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | 2195 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ |
| 2701 | #define nSDIO_INT_DET 0x0 | ||
| 2702 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | 2196 | #define SD_CARD_DET 0x10 /* SD Card Detect */ |
| 2703 | #define nSD_CARD_DET 0x0 | ||
| 2704 | 2197 | ||
| 2705 | /* Bit masks for SDH_E_MASK */ | 2198 | /* Bit masks for SDH_E_MASK */ |
| 2706 | 2199 | ||
| 2707 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ | 2200 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ |
| 2708 | #define nSDIO_MSK 0x0 | ||
| 2709 | #define SCD_MSK 0x40 /* Mask Card Detect */ | 2201 | #define SCD_MSK 0x40 /* Mask Card Detect */ |
| 2710 | #define nSCD_MSK 0x0 | ||
| 2711 | 2202 | ||
| 2712 | /* Bit masks for SDH_CFG */ | 2203 | /* Bit masks for SDH_CFG */ |
| 2713 | 2204 | ||
| 2714 | #define CLKS_EN 0x1 /* Clocks Enable */ | 2205 | #define CLKS_EN 0x1 /* Clocks Enable */ |
| 2715 | #define nCLKS_EN 0x0 | ||
| 2716 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ | 2206 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ |
| 2717 | #define nSD4E 0x0 | ||
| 2718 | #define MWE 0x8 /* Moving Window Enable */ | 2207 | #define MWE 0x8 /* Moving Window Enable */ |
| 2719 | #define nMWE 0x0 | ||
| 2720 | #define SD_RST 0x10 /* SDMMC Reset */ | 2208 | #define SD_RST 0x10 /* SDMMC Reset */ |
| 2721 | #define nSD_RST 0x0 | ||
| 2722 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ | 2209 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ |
| 2723 | #define nPUP_SDDAT 0x0 | ||
| 2724 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ | 2210 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ |
| 2725 | #define nPUP_SDDAT3 0x0 | ||
| 2726 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ | 2211 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ |
| 2727 | #define nPD_SDDAT3 0x0 | ||
| 2728 | 2212 | ||
| 2729 | /* Bit masks for SDH_RD_WAIT_EN */ | 2213 | /* Bit masks for SDH_RD_WAIT_EN */ |
| 2730 | 2214 | ||
| 2731 | #define RWR 0x1 /* Read Wait Request */ | 2215 | #define RWR 0x1 /* Read Wait Request */ |
| 2732 | #define nRWR 0x0 | ||
| 2733 | 2216 | ||
| 2734 | /* Bit masks for ATAPI_CONTROL */ | 2217 | /* Bit masks for ATAPI_CONTROL */ |
| 2735 | 2218 | ||
| 2736 | #define PIO_START 0x1 /* Start PIO/Reg Op */ | 2219 | #define PIO_START 0x1 /* Start PIO/Reg Op */ |
| 2737 | #define nPIO_START 0x0 | ||
| 2738 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ | 2220 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ |
| 2739 | #define nMULTI_START 0x0 | ||
| 2740 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ | 2221 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ |
| 2741 | #define nULTRA_START 0x0 | ||
| 2742 | #define XFER_DIR 0x8 /* Transfer Direction */ | 2222 | #define XFER_DIR 0x8 /* Transfer Direction */ |
| 2743 | #define nXFER_DIR 0x0 | ||
| 2744 | #define IORDY_EN 0x10 /* IORDY Enable */ | 2223 | #define IORDY_EN 0x10 /* IORDY Enable */ |
| 2745 | #define nIORDY_EN 0x0 | ||
| 2746 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ | 2224 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ |
| 2747 | #define nFIFO_FLUSH 0x0 | ||
| 2748 | #define SOFT_RST 0x40 /* Soft Reset */ | 2225 | #define SOFT_RST 0x40 /* Soft Reset */ |
| 2749 | #define nSOFT_RST 0x0 | ||
| 2750 | #define DEV_RST 0x80 /* Device Reset */ | 2226 | #define DEV_RST 0x80 /* Device Reset */ |
| 2751 | #define nDEV_RST 0x0 | ||
| 2752 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ | 2227 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ |
| 2753 | #define nTFRCNT_RST 0x0 | ||
| 2754 | #define END_ON_TERM 0x200 /* End/Terminate Select */ | 2228 | #define END_ON_TERM 0x200 /* End/Terminate Select */ |
| 2755 | #define nEND_ON_TERM 0x0 | ||
| 2756 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ | 2229 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ |
| 2757 | #define nPIO_USE_DMA 0x0 | ||
| 2758 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ | 2230 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ |
| 2759 | 2231 | ||
| 2760 | /* Bit masks for ATAPI_STATUS */ | 2232 | /* Bit masks for ATAPI_STATUS */ |
| 2761 | 2233 | ||
| 2762 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ | 2234 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ |
| 2763 | #define nPIO_XFER_ON 0x0 | ||
| 2764 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ | 2235 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ |
| 2765 | #define nMULTI_XFER_ON 0x0 | ||
| 2766 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ | 2236 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ |
| 2767 | #define nULTRA_XFER_ON 0x0 | ||
| 2768 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ | 2237 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ |
| 2769 | 2238 | ||
| 2770 | /* Bit masks for ATAPI_DEV_ADDR */ | 2239 | /* Bit masks for ATAPI_DEV_ADDR */ |
| @@ -2774,66 +2243,39 @@ | |||
| 2774 | /* Bit masks for ATAPI_INT_MASK */ | 2243 | /* Bit masks for ATAPI_INT_MASK */ |
| 2775 | 2244 | ||
| 2776 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ | 2245 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ |
| 2777 | #define nATAPI_DEV_INT_MASK 0x0 | ||
| 2778 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ | 2246 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ |
| 2779 | #define nPIO_DONE_MASK 0x0 | ||
| 2780 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ | 2247 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ |
| 2781 | #define nMULTI_DONE_MASK 0x0 | ||
| 2782 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ | 2248 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ |
| 2783 | #define nUDMAIN_DONE_MASK 0x0 | ||
| 2784 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ | 2249 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ |
| 2785 | #define nUDMAOUT_DONE_MASK 0x0 | ||
| 2786 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ | 2250 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ |
| 2787 | #define nHOST_TERM_XFER_MASK 0x0 | ||
| 2788 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ | 2251 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ |
| 2789 | #define nMULTI_TERM_MASK 0x0 | ||
| 2790 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ | 2252 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ |
| 2791 | #define nUDMAIN_TERM_MASK 0x0 | ||
| 2792 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ | 2253 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ |
| 2793 | #define nUDMAOUT_TERM_MASK 0x0 | ||
| 2794 | 2254 | ||
| 2795 | /* Bit masks for ATAPI_INT_STATUS */ | 2255 | /* Bit masks for ATAPI_INT_STATUS */ |
| 2796 | 2256 | ||
| 2797 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ | 2257 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ |
| 2798 | #define nATAPI_DEV_INT 0x0 | ||
| 2799 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ | 2258 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ |
| 2800 | #define nPIO_DONE_INT 0x0 | ||
| 2801 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ | 2259 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ |
| 2802 | #define nMULTI_DONE_INT 0x0 | ||
| 2803 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ | 2260 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ |
| 2804 | #define nUDMAIN_DONE_INT 0x0 | ||
| 2805 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ | 2261 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ |
| 2806 | #define nUDMAOUT_DONE_INT 0x0 | ||
| 2807 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ | 2262 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ |
| 2808 | #define nHOST_TERM_XFER_INT 0x0 | ||
| 2809 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ | 2263 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ |
| 2810 | #define nMULTI_TERM_INT 0x0 | ||
| 2811 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ | 2264 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ |
| 2812 | #define nUDMAIN_TERM_INT 0x0 | ||
| 2813 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ | 2265 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ |
| 2814 | #define nUDMAOUT_TERM_INT 0x0 | ||
| 2815 | 2266 | ||
| 2816 | /* Bit masks for ATAPI_LINE_STATUS */ | 2267 | /* Bit masks for ATAPI_LINE_STATUS */ |
| 2817 | 2268 | ||
| 2818 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ | 2269 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ |
| 2819 | #define nATAPI_INTR 0x0 | ||
| 2820 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ | 2270 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ |
| 2821 | #define nATAPI_DASP 0x0 | ||
| 2822 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ | 2271 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ |
| 2823 | #define nATAPI_CS0N 0x0 | ||
| 2824 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ | 2272 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ |
| 2825 | #define nATAPI_CS1N 0x0 | ||
| 2826 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ | 2273 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ |
| 2827 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ | 2274 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ |
| 2828 | #define nATAPI_DMAREQ 0x0 | ||
| 2829 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ | 2275 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ |
| 2830 | #define nATAPI_DMAACKN 0x0 | ||
| 2831 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ | 2276 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ |
| 2832 | #define nATAPI_DIOWN 0x0 | ||
| 2833 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ | 2277 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ |
| 2834 | #define nATAPI_DIORN 0x0 | ||
| 2835 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ | 2278 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ |
| 2836 | #define nATAPI_IORDY 0x0 | ||
| 2837 | 2279 | ||
| 2838 | /* Bit masks for ATAPI_SM_STATE */ | 2280 | /* Bit masks for ATAPI_SM_STATE */ |
| 2839 | 2281 | ||
| @@ -2845,7 +2287,6 @@ | |||
| 2845 | /* Bit masks for ATAPI_TERMINATE */ | 2287 | /* Bit masks for ATAPI_TERMINATE */ |
| 2846 | 2288 | ||
| 2847 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ | 2289 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ |
| 2848 | #define nATAPI_HOST_TERM 0x0 | ||
| 2849 | 2290 | ||
| 2850 | /* Bit masks for ATAPI_REG_TIM_0 */ | 2291 | /* Bit masks for ATAPI_REG_TIM_0 */ |
| 2851 | 2292 | ||
| @@ -2900,41 +2341,26 @@ | |||
| 2900 | /* Bit masks for TIMER_ENABLE1 */ | 2341 | /* Bit masks for TIMER_ENABLE1 */ |
| 2901 | 2342 | ||
| 2902 | #define TIMEN8 0x1 /* Timer 8 Enable */ | 2343 | #define TIMEN8 0x1 /* Timer 8 Enable */ |
| 2903 | #define nTIMEN8 0x0 | ||
| 2904 | #define TIMEN9 0x2 /* Timer 9 Enable */ | 2344 | #define TIMEN9 0x2 /* Timer 9 Enable */ |
| 2905 | #define nTIMEN9 0x0 | ||
| 2906 | #define TIMEN10 0x4 /* Timer 10 Enable */ | 2345 | #define TIMEN10 0x4 /* Timer 10 Enable */ |
| 2907 | #define nTIMEN10 0x0 | ||
| 2908 | 2346 | ||
| 2909 | /* Bit masks for TIMER_DISABLE1 */ | 2347 | /* Bit masks for TIMER_DISABLE1 */ |
| 2910 | 2348 | ||
| 2911 | #define TIMDIS8 0x1 /* Timer 8 Disable */ | 2349 | #define TIMDIS8 0x1 /* Timer 8 Disable */ |
| 2912 | #define nTIMDIS8 0x0 | ||
| 2913 | #define TIMDIS9 0x2 /* Timer 9 Disable */ | 2350 | #define TIMDIS9 0x2 /* Timer 9 Disable */ |
| 2914 | #define nTIMDIS9 0x0 | ||
| 2915 | #define TIMDIS10 0x4 /* Timer 10 Disable */ | 2351 | #define TIMDIS10 0x4 /* Timer 10 Disable */ |
| 2916 | #define nTIMDIS10 0x0 | ||
| 2917 | 2352 | ||
| 2918 | /* Bit masks for TIMER_STATUS1 */ | 2353 | /* Bit masks for TIMER_STATUS1 */ |
| 2919 | 2354 | ||
| 2920 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ | 2355 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ |
| 2921 | #define nTIMIL8 0x0 | ||
| 2922 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ | 2356 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ |
| 2923 | #define nTIMIL9 0x0 | ||
| 2924 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ | 2357 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ |
| 2925 | #define nTIMIL10 0x0 | ||
| 2926 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ | 2358 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ |
| 2927 | #define nTOVF_ERR8 0x0 | ||
| 2928 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ | 2359 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ |
| 2929 | #define nTOVF_ERR9 0x0 | ||
| 2930 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ | 2360 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ |
| 2931 | #define nTOVF_ERR10 0x0 | ||
| 2932 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ | 2361 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ |
| 2933 | #define nTRUN8 0x0 | ||
| 2934 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ | 2362 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ |
| 2935 | #define nTRUN9 0x0 | ||
| 2936 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ | 2363 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ |
| 2937 | #define nTRUN10 0x0 | ||
| 2938 | 2364 | ||
| 2939 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ | 2365 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ |
| 2940 | 2366 | ||
| @@ -2945,131 +2371,77 @@ | |||
| 2945 | /* Bit masks for USB_POWER */ | 2371 | /* Bit masks for USB_POWER */ |
| 2946 | 2372 | ||
| 2947 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | 2373 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ |
| 2948 | #define nENABLE_SUSPENDM 0x0 | ||
| 2949 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | 2374 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ |
| 2950 | #define nSUSPEND_MODE 0x0 | ||
| 2951 | #define RESUME_MODE 0x4 /* DMA Mode */ | 2375 | #define RESUME_MODE 0x4 /* DMA Mode */ |
| 2952 | #define nRESUME_MODE 0x0 | ||
| 2953 | #define RESET 0x8 /* Reset indicator */ | 2376 | #define RESET 0x8 /* Reset indicator */ |
| 2954 | #define nRESET 0x0 | ||
| 2955 | #define HS_MODE 0x10 /* High Speed mode indicator */ | 2377 | #define HS_MODE 0x10 /* High Speed mode indicator */ |
| 2956 | #define nHS_MODE 0x0 | ||
| 2957 | #define HS_ENABLE 0x20 /* high Speed Enable */ | 2378 | #define HS_ENABLE 0x20 /* high Speed Enable */ |
| 2958 | #define nHS_ENABLE 0x0 | ||
| 2959 | #define SOFT_CONN 0x40 /* Soft connect */ | 2379 | #define SOFT_CONN 0x40 /* Soft connect */ |
| 2960 | #define nSOFT_CONN 0x0 | ||
| 2961 | #define ISO_UPDATE 0x80 /* Isochronous update */ | 2380 | #define ISO_UPDATE 0x80 /* Isochronous update */ |
| 2962 | #define nISO_UPDATE 0x0 | ||
| 2963 | 2381 | ||
| 2964 | /* Bit masks for USB_INTRTX */ | 2382 | /* Bit masks for USB_INTRTX */ |
| 2965 | 2383 | ||
| 2966 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | 2384 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ |
| 2967 | #define nEP0_TX 0x0 | ||
| 2968 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | 2385 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ |
| 2969 | #define nEP1_TX 0x0 | ||
| 2970 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | 2386 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ |
| 2971 | #define nEP2_TX 0x0 | ||
| 2972 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | 2387 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ |
| 2973 | #define nEP3_TX 0x0 | ||
| 2974 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | 2388 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ |
| 2975 | #define nEP4_TX 0x0 | ||
| 2976 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | 2389 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ |
| 2977 | #define nEP5_TX 0x0 | ||
| 2978 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | 2390 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ |
| 2979 | #define nEP6_TX 0x0 | ||
| 2980 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | 2391 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ |
| 2981 | #define nEP7_TX 0x0 | ||
| 2982 | 2392 | ||
| 2983 | /* Bit masks for USB_INTRRX */ | 2393 | /* Bit masks for USB_INTRRX */ |
| 2984 | 2394 | ||
| 2985 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | 2395 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ |
| 2986 | #define nEP1_RX 0x0 | ||
| 2987 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | 2396 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ |
| 2988 | #define nEP2_RX 0x0 | ||
| 2989 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | 2397 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ |
| 2990 | #define nEP3_RX 0x0 | ||
| 2991 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | 2398 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ |
| 2992 | #define nEP4_RX 0x0 | ||
| 2993 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | 2399 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ |
| 2994 | #define nEP5_RX 0x0 | ||
| 2995 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | 2400 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ |
| 2996 | #define nEP6_RX 0x0 | ||
| 2997 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | 2401 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ |
| 2998 | #define nEP7_RX 0x0 | ||
| 2999 | 2402 | ||
| 3000 | /* Bit masks for USB_INTRTXE */ | 2403 | /* Bit masks for USB_INTRTXE */ |
| 3001 | 2404 | ||
| 3002 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | 2405 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ |
| 3003 | #define nEP0_TX_E 0x0 | ||
| 3004 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | 2406 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ |
| 3005 | #define nEP1_TX_E 0x0 | ||
| 3006 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | 2407 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ |
| 3007 | #define nEP2_TX_E 0x0 | ||
| 3008 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | 2408 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ |
| 3009 | #define nEP3_TX_E 0x0 | ||
| 3010 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | 2409 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ |
| 3011 | #define nEP4_TX_E 0x0 | ||
| 3012 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | 2410 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ |
| 3013 | #define nEP5_TX_E 0x0 | ||
| 3014 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | 2411 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ |
| 3015 | #define nEP6_TX_E 0x0 | ||
| 3016 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | 2412 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ |
| 3017 | #define nEP7_TX_E 0x0 | ||
| 3018 | 2413 | ||
| 3019 | /* Bit masks for USB_INTRRXE */ | 2414 | /* Bit masks for USB_INTRRXE */ |
| 3020 | 2415 | ||
| 3021 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | 2416 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ |
| 3022 | #define nEP1_RX_E 0x0 | ||
| 3023 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | 2417 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ |
| 3024 | #define nEP2_RX_E 0x0 | ||
| 3025 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | 2418 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ |
| 3026 | #define nEP3_RX_E 0x0 | ||
| 3027 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | 2419 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ |
| 3028 | #define nEP4_RX_E 0x0 | ||
| 3029 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | 2420 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ |
| 3030 | #define nEP5_RX_E 0x0 | ||
| 3031 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | 2421 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ |
| 3032 | #define nEP6_RX_E 0x0 | ||
| 3033 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | 2422 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ |
| 3034 | #define nEP7_RX_E 0x0 | ||
| 3035 | 2423 | ||
| 3036 | /* Bit masks for USB_INTRUSB */ | 2424 | /* Bit masks for USB_INTRUSB */ |
| 3037 | 2425 | ||
| 3038 | #define SUSPEND_B 0x1 /* Suspend indicator */ | 2426 | #define SUSPEND_B 0x1 /* Suspend indicator */ |
| 3039 | #define nSUSPEND_B 0x0 | ||
| 3040 | #define RESUME_B 0x2 /* Resume indicator */ | 2427 | #define RESUME_B 0x2 /* Resume indicator */ |
| 3041 | #define nRESUME_B 0x0 | ||
| 3042 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | 2428 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ |
| 3043 | #define nRESET_OR_BABLE_B 0x0 | ||
| 3044 | #define SOF_B 0x8 /* Start of frame */ | 2429 | #define SOF_B 0x8 /* Start of frame */ |
| 3045 | #define nSOF_B 0x0 | ||
| 3046 | #define CONN_B 0x10 /* Connection indicator */ | 2430 | #define CONN_B 0x10 /* Connection indicator */ |
| 3047 | #define nCONN_B 0x0 | ||
| 3048 | #define DISCON_B 0x20 /* Disconnect indicator */ | 2431 | #define DISCON_B 0x20 /* Disconnect indicator */ |
| 3049 | #define nDISCON_B 0x0 | ||
| 3050 | #define SESSION_REQ_B 0x40 /* Session Request */ | 2432 | #define SESSION_REQ_B 0x40 /* Session Request */ |
| 3051 | #define nSESSION_REQ_B 0x0 | ||
| 3052 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | 2433 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ |
| 3053 | #define nVBUS_ERROR_B 0x0 | ||
| 3054 | 2434 | ||
| 3055 | /* Bit masks for USB_INTRUSBE */ | 2435 | /* Bit masks for USB_INTRUSBE */ |
| 3056 | 2436 | ||
| 3057 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | 2437 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ |
| 3058 | #define nSUSPEND_BE 0x0 | ||
| 3059 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | 2438 | #define RESUME_BE 0x2 /* Resume indicator int enable */ |
| 3060 | #define nRESUME_BE 0x0 | ||
| 3061 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | 2439 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ |
| 3062 | #define nRESET_OR_BABLE_BE 0x0 | ||
| 3063 | #define SOF_BE 0x8 /* Start of frame int enable */ | 2440 | #define SOF_BE 0x8 /* Start of frame int enable */ |
| 3064 | #define nSOF_BE 0x0 | ||
| 3065 | #define CONN_BE 0x10 /* Connection indicator int enable */ | 2441 | #define CONN_BE 0x10 /* Connection indicator int enable */ |
| 3066 | #define nCONN_BE 0x0 | ||
| 3067 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | 2442 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ |
| 3068 | #define nDISCON_BE 0x0 | ||
| 3069 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | 2443 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ |
| 3070 | #define nSESSION_REQ_BE 0x0 | ||
| 3071 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | 2444 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ |
| 3072 | #define nVBUS_ERROR_BE 0x0 | ||
| 3073 | 2445 | ||
| 3074 | /* Bit masks for USB_FRAME */ | 2446 | /* Bit masks for USB_FRAME */ |
| 3075 | 2447 | ||
| @@ -3082,117 +2454,67 @@ | |||
| 3082 | /* Bit masks for USB_GLOBAL_CTL */ | 2454 | /* Bit masks for USB_GLOBAL_CTL */ |
| 3083 | 2455 | ||
| 3084 | #define GLOBAL_ENA 0x1 /* enables USB module */ | 2456 | #define GLOBAL_ENA 0x1 /* enables USB module */ |
| 3085 | #define nGLOBAL_ENA 0x0 | ||
| 3086 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | 2457 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ |
| 3087 | #define nEP1_TX_ENA 0x0 | ||
| 3088 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | 2458 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ |
| 3089 | #define nEP2_TX_ENA 0x0 | ||
| 3090 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | 2459 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ |
| 3091 | #define nEP3_TX_ENA 0x0 | ||
| 3092 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | 2460 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ |
| 3093 | #define nEP4_TX_ENA 0x0 | ||
| 3094 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | 2461 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ |
| 3095 | #define nEP5_TX_ENA 0x0 | ||
| 3096 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | 2462 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ |
| 3097 | #define nEP6_TX_ENA 0x0 | ||
| 3098 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | 2463 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ |
| 3099 | #define nEP7_TX_ENA 0x0 | ||
| 3100 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | 2464 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ |
| 3101 | #define nEP1_RX_ENA 0x0 | ||
| 3102 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | 2465 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ |
| 3103 | #define nEP2_RX_ENA 0x0 | ||
| 3104 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | 2466 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ |
| 3105 | #define nEP3_RX_ENA 0x0 | ||
| 3106 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | 2467 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ |
| 3107 | #define nEP4_RX_ENA 0x0 | ||
| 3108 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | 2468 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ |
| 3109 | #define nEP5_RX_ENA 0x0 | ||
| 3110 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | 2469 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ |
| 3111 | #define nEP6_RX_ENA 0x0 | ||
| 3112 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | 2470 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ |
| 3113 | #define nEP7_RX_ENA 0x0 | ||
| 3114 | 2471 | ||
| 3115 | /* Bit masks for USB_OTG_DEV_CTL */ | 2472 | /* Bit masks for USB_OTG_DEV_CTL */ |
| 3116 | 2473 | ||
| 3117 | #define SESSION 0x1 /* session indicator */ | 2474 | #define SESSION 0x1 /* session indicator */ |
| 3118 | #define nSESSION 0x0 | ||
| 3119 | #define HOST_REQ 0x2 /* Host negotiation request */ | 2475 | #define HOST_REQ 0x2 /* Host negotiation request */ |
| 3120 | #define nHOST_REQ 0x0 | ||
| 3121 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | 2476 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ |
| 3122 | #define nHOST_MODE 0x0 | ||
| 3123 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | 2477 | #define VBUS0 0x8 /* Vbus level indicator[0] */ |
| 3124 | #define nVBUS0 0x0 | ||
| 3125 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | 2478 | #define VBUS1 0x10 /* Vbus level indicator[1] */ |
| 3126 | #define nVBUS1 0x0 | ||
| 3127 | #define LSDEV 0x20 /* Low-speed indicator */ | 2479 | #define LSDEV 0x20 /* Low-speed indicator */ |
| 3128 | #define nLSDEV 0x0 | ||
| 3129 | #define FSDEV 0x40 /* Full or High-speed indicator */ | 2480 | #define FSDEV 0x40 /* Full or High-speed indicator */ |
| 3130 | #define nFSDEV 0x0 | ||
| 3131 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | 2481 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ |
| 3132 | #define nB_DEVICE 0x0 | ||
| 3133 | 2482 | ||
| 3134 | /* Bit masks for USB_OTG_VBUS_IRQ */ | 2483 | /* Bit masks for USB_OTG_VBUS_IRQ */ |
| 3135 | 2484 | ||
| 3136 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | 2485 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ |
| 3137 | #define nDRIVE_VBUS_ON 0x0 | ||
| 3138 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | 2486 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ |
| 3139 | #define nDRIVE_VBUS_OFF 0x0 | ||
| 3140 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | 2487 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ |
| 3141 | #define nCHRG_VBUS_START 0x0 | ||
| 3142 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | 2488 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ |
| 3143 | #define nCHRG_VBUS_END 0x0 | ||
| 3144 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | 2489 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ |
| 3145 | #define nDISCHRG_VBUS_START 0x0 | ||
| 3146 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | 2490 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ |
| 3147 | #define nDISCHRG_VBUS_END 0x0 | ||
| 3148 | 2491 | ||
| 3149 | /* Bit masks for USB_OTG_VBUS_MASK */ | 2492 | /* Bit masks for USB_OTG_VBUS_MASK */ |
| 3150 | 2493 | ||
| 3151 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | 2494 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ |
| 3152 | #define nDRIVE_VBUS_ON_ENA 0x0 | ||
| 3153 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | 2495 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ |
| 3154 | #define nDRIVE_VBUS_OFF_ENA 0x0 | ||
| 3155 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | 2496 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ |
| 3156 | #define nCHRG_VBUS_START_ENA 0x0 | ||
| 3157 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | 2497 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ |
| 3158 | #define nCHRG_VBUS_END_ENA 0x0 | ||
| 3159 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | 2498 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ |
| 3160 | #define nDISCHRG_VBUS_START_ENA 0x0 | ||
| 3161 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | 2499 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ |
| 3162 | #define nDISCHRG_VBUS_END_ENA 0x0 | ||
| 3163 | 2500 | ||
| 3164 | /* Bit masks for USB_CSR0 */ | 2501 | /* Bit masks for USB_CSR0 */ |
| 3165 | 2502 | ||
| 3166 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | 2503 | #define RXPKTRDY 0x1 /* data packet receive indicator */ |
| 3167 | #define nRXPKTRDY 0x0 | ||
| 3168 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | 2504 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ |
| 3169 | #define nTXPKTRDY 0x0 | ||
| 3170 | #define STALL_SENT 0x4 /* STALL handshake sent */ | 2505 | #define STALL_SENT 0x4 /* STALL handshake sent */ |
| 3171 | #define nSTALL_SENT 0x0 | ||
| 3172 | #define DATAEND 0x8 /* Data end indicator */ | 2506 | #define DATAEND 0x8 /* Data end indicator */ |
| 3173 | #define nDATAEND 0x0 | ||
| 3174 | #define SETUPEND 0x10 /* Setup end */ | 2507 | #define SETUPEND 0x10 /* Setup end */ |
| 3175 | #define nSETUPEND 0x0 | ||
| 3176 | #define SENDSTALL 0x20 /* Send STALL handshake */ | 2508 | #define SENDSTALL 0x20 /* Send STALL handshake */ |
| 3177 | #define nSENDSTALL 0x0 | ||
| 3178 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | 2509 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ |
| 3179 | #define nSERVICED_RXPKTRDY 0x0 | ||
| 3180 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | 2510 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ |
| 3181 | #define nSERVICED_SETUPEND 0x0 | ||
| 3182 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | 2511 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ |
| 3183 | #define nFLUSHFIFO 0x0 | ||
| 3184 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | 2512 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ |
| 3185 | #define nSTALL_RECEIVED_H 0x0 | ||
| 3186 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | 2513 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ |
| 3187 | #define nSETUPPKT_H 0x0 | ||
| 3188 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | 2514 | #define ERROR_H 0x10 /* timeout error indicator host mode */ |
| 3189 | #define nERROR_H 0x0 | ||
| 3190 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | 2515 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ |
| 3191 | #define nREQPKT_H 0x0 | ||
| 3192 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | 2516 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ |
| 3193 | #define nSTATUSPKT_H 0x0 | ||
| 3194 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | 2517 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ |
| 3195 | #define nNAK_TIMEOUT_H 0x0 | ||
| 3196 | 2518 | ||
| 3197 | /* Bit masks for USB_COUNT0 */ | 2519 | /* Bit masks for USB_COUNT0 */ |
| 3198 | 2520 | ||
| @@ -3213,37 +2535,21 @@ | |||
| 3213 | /* Bit masks for USB_TXCSR */ | 2535 | /* Bit masks for USB_TXCSR */ |
| 3214 | 2536 | ||
| 3215 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | 2537 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ |
| 3216 | #define nTXPKTRDY_T 0x0 | ||
| 3217 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | 2538 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ |
| 3218 | #define nFIFO_NOT_EMPTY_T 0x0 | ||
| 3219 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | 2539 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ |
| 3220 | #define nUNDERRUN_T 0x0 | ||
| 3221 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | 2540 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ |
| 3222 | #define nFLUSHFIFO_T 0x0 | ||
| 3223 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | 2541 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ |
| 3224 | #define nSTALL_SEND_T 0x0 | ||
| 3225 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | 2542 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ |
| 3226 | #define nSTALL_SENT_T 0x0 | ||
| 3227 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | 2543 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ |
| 3228 | #define nCLEAR_DATATOGGLE_T 0x0 | ||
| 3229 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | 2544 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ |
| 3230 | #define nINCOMPTX_T 0x0 | ||
| 3231 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | 2545 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ |
| 3232 | #define nDMAREQMODE_T 0x0 | ||
| 3233 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | 2546 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ |
| 3234 | #define nFORCE_DATATOGGLE_T 0x0 | ||
| 3235 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | 2547 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ |
| 3236 | #define nDMAREQ_ENA_T 0x0 | ||
| 3237 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | 2548 | #define ISO_T 0x4000 /* enable Isochronous transfers */ |
| 3238 | #define nISO_T 0x0 | ||
| 3239 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | 2549 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ |
| 3240 | #define nAUTOSET_T 0x0 | ||
| 3241 | #define ERROR_TH 0x4 /* error condition host mode */ | 2550 | #define ERROR_TH 0x4 /* error condition host mode */ |
| 3242 | #define nERROR_TH 0x0 | ||
| 3243 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | 2551 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ |
| 3244 | #define nSTALL_RECEIVED_TH 0x0 | ||
| 3245 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | 2552 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ |
| 3246 | #define nNAK_TIMEOUT_TH 0x0 | ||
| 3247 | 2553 | ||
| 3248 | /* Bit masks for USB_TXCOUNT */ | 2554 | /* Bit masks for USB_TXCOUNT */ |
| 3249 | 2555 | ||
| @@ -3252,45 +2558,25 @@ | |||
| 3252 | /* Bit masks for USB_RXCSR */ | 2558 | /* Bit masks for USB_RXCSR */ |
| 3253 | 2559 | ||
| 3254 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | 2560 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ |
| 3255 | #define nRXPKTRDY_R 0x0 | ||
| 3256 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | 2561 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ |
| 3257 | #define nFIFO_FULL_R 0x0 | ||
| 3258 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | 2562 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ |
| 3259 | #define nOVERRUN_R 0x0 | ||
| 3260 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | 2563 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ |
| 3261 | #define nDATAERROR_R 0x0 | ||
| 3262 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | 2564 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ |
| 3263 | #define nFLUSHFIFO_R 0x0 | ||
| 3264 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | 2565 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ |
| 3265 | #define nSTALL_SEND_R 0x0 | ||
| 3266 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | 2566 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ |
| 3267 | #define nSTALL_SENT_R 0x0 | ||
| 3268 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | 2567 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ |
| 3269 | #define nCLEAR_DATATOGGLE_R 0x0 | ||
| 3270 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | 2568 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ |
| 3271 | #define nINCOMPRX_R 0x0 | ||
| 3272 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | 2569 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ |
| 3273 | #define nDMAREQMODE_R 0x0 | ||
| 3274 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | 2570 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ |
| 3275 | #define nDISNYET_R 0x0 | ||
| 3276 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | 2571 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ |
| 3277 | #define nDMAREQ_ENA_R 0x0 | ||
| 3278 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | 2572 | #define ISO_R 0x4000 /* enable Isochronous transfers */ |
| 3279 | #define nISO_R 0x0 | ||
| 3280 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | 2573 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ |
| 3281 | #define nAUTOCLEAR_R 0x0 | ||
| 3282 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | 2574 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ |
| 3283 | #define nERROR_RH 0x0 | ||
| 3284 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | 2575 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ |
| 3285 | #define nREQPKT_RH 0x0 | ||
| 3286 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | 2576 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ |
| 3287 | #define nSTALL_RECEIVED_RH 0x0 | ||
| 3288 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | 2577 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ |
| 3289 | #define nINCOMPRX_RH 0x0 | ||
| 3290 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | 2578 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ |
| 3291 | #define nDMAREQMODE_RH 0x0 | ||
| 3292 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | 2579 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ |
| 3293 | #define nAUTOREQ_RH 0x0 | ||
| 3294 | 2580 | ||
| 3295 | /* Bit masks for USB_RXCOUNT */ | 2581 | /* Bit masks for USB_RXCOUNT */ |
| 3296 | 2582 | ||
| @@ -3317,35 +2603,22 @@ | |||
| 3317 | /* Bit masks for USB_DMA_INTERRUPT */ | 2603 | /* Bit masks for USB_DMA_INTERRUPT */ |
| 3318 | 2604 | ||
| 3319 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | 2605 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ |
| 3320 | #define nDMA0_INT 0x0 | ||
| 3321 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | 2606 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ |
| 3322 | #define nDMA1_INT 0x0 | ||
| 3323 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | 2607 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ |
| 3324 | #define nDMA2_INT 0x0 | ||
| 3325 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | 2608 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ |
| 3326 | #define nDMA3_INT 0x0 | ||
| 3327 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | 2609 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ |
| 3328 | #define nDMA4_INT 0x0 | ||
| 3329 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | 2610 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ |
| 3330 | #define nDMA5_INT 0x0 | ||
| 3331 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | 2611 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ |
| 3332 | #define nDMA6_INT 0x0 | ||
| 3333 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | 2612 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ |
| 3334 | #define nDMA7_INT 0x0 | ||
| 3335 | 2613 | ||
| 3336 | /* Bit masks for USB_DMAxCONTROL */ | 2614 | /* Bit masks for USB_DMAxCONTROL */ |
| 3337 | 2615 | ||
| 3338 | #define DMA_ENA 0x1 /* DMA enable */ | 2616 | #define DMA_ENA 0x1 /* DMA enable */ |
| 3339 | #define nDMA_ENA 0x0 | ||
| 3340 | #define DIRECTION 0x2 /* direction of DMA transfer */ | 2617 | #define DIRECTION 0x2 /* direction of DMA transfer */ |
| 3341 | #define nDIRECTION 0x0 | ||
| 3342 | #define MODE 0x4 /* DMA Bus error */ | 2618 | #define MODE 0x4 /* DMA Bus error */ |
| 3343 | #define nMODE 0x0 | ||
| 3344 | #define INT_ENA 0x8 /* Interrupt enable */ | 2619 | #define INT_ENA 0x8 /* Interrupt enable */ |
| 3345 | #define nINT_ENA 0x0 | ||
| 3346 | #define EPNUM 0xf0 /* EP number */ | 2620 | #define EPNUM 0xf0 /* EP number */ |
| 3347 | #define BUSERROR 0x100 /* DMA Bus error */ | 2621 | #define BUSERROR 0x100 /* DMA Bus error */ |
| 3348 | #define nBUSERROR 0x0 | ||
| 3349 | 2622 | ||
| 3350 | /* Bit masks for USB_DMAxADDRHIGH */ | 2623 | /* Bit masks for USB_DMAxADDRHIGH */ |
| 3351 | 2624 | ||
| @@ -3366,26 +2639,16 @@ | |||
| 3366 | /* Bit masks for HMDMAx_CONTROL */ | 2639 | /* Bit masks for HMDMAx_CONTROL */ |
| 3367 | 2640 | ||
| 3368 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ | 2641 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ |
| 3369 | #define nHMDMAEN 0x0 | ||
| 3370 | #define REP 0x2 /* Handshake MDMA Request Polarity */ | 2642 | #define REP 0x2 /* Handshake MDMA Request Polarity */ |
| 3371 | #define nREP 0x0 | ||
| 3372 | #define UTE 0x8 /* Urgency Threshold Enable */ | 2643 | #define UTE 0x8 /* Urgency Threshold Enable */ |
| 3373 | #define nUTE 0x0 | ||
| 3374 | #define OIE 0x10 /* Overflow Interrupt Enable */ | 2644 | #define OIE 0x10 /* Overflow Interrupt Enable */ |
| 3375 | #define nOIE 0x0 | ||
| 3376 | #define BDIE 0x20 /* Block Done Interrupt Enable */ | 2645 | #define BDIE 0x20 /* Block Done Interrupt Enable */ |
| 3377 | #define nBDIE 0x0 | ||
| 3378 | #define MBDI 0x40 /* Mask Block Done Interrupt */ | 2646 | #define MBDI 0x40 /* Mask Block Done Interrupt */ |
| 3379 | #define nMBDI 0x0 | ||
| 3380 | #define DRQ 0x300 /* Handshake MDMA Request Type */ | 2647 | #define DRQ 0x300 /* Handshake MDMA Request Type */ |
| 3381 | #define RBC 0x1000 /* Force Reload of BCOUNT */ | 2648 | #define RBC 0x1000 /* Force Reload of BCOUNT */ |
| 3382 | #define nRBC 0x0 | ||
| 3383 | #define PS 0x2000 /* Pin Status */ | 2649 | #define PS 0x2000 /* Pin Status */ |
| 3384 | #define nPS 0x0 | ||
| 3385 | #define OI 0x4000 /* Overflow Interrupt Generated */ | 2650 | #define OI 0x4000 /* Overflow Interrupt Generated */ |
| 3386 | #define nOI 0x0 | ||
| 3387 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | 2651 | #define BDI 0x8000 /* Block Done Interrupt Generated */ |
| 3388 | #define nBDI 0x0 | ||
| 3389 | 2652 | ||
| 3390 | /* ******************************************* */ | 2653 | /* ******************************************* */ |
| 3391 | /* MULTI BIT MACRO ENUMERATIONS */ | 2654 | /* MULTI BIT MACRO ENUMERATIONS */ |