diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF548.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/defBF548.h | 341 |
1 files changed, 0 insertions, 341 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index d9e3062a9117..8d4214e0807c 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h | |||
| @@ -899,21 +899,13 @@ | |||
| 899 | /* Bit masks for PIXC_CTL */ | 899 | /* Bit masks for PIXC_CTL */ |
| 900 | 900 | ||
| 901 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ | 901 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ |
| 902 | #define nPIXC_EN 0x0 | ||
| 903 | #define OVR_A_EN 0x2 /* Overlay A Enable */ | 902 | #define OVR_A_EN 0x2 /* Overlay A Enable */ |
| 904 | #define nOVR_A_EN 0x0 | ||
| 905 | #define OVR_B_EN 0x4 /* Overlay B Enable */ | 903 | #define OVR_B_EN 0x4 /* Overlay B Enable */ |
| 906 | #define nOVR_B_EN 0x0 | ||
| 907 | #define IMG_FORM 0x8 /* Image Data Format */ | 904 | #define IMG_FORM 0x8 /* Image Data Format */ |
| 908 | #define nIMG_FORM 0x0 | ||
| 909 | #define OVR_FORM 0x10 /* Overlay Data Format */ | 905 | #define OVR_FORM 0x10 /* Overlay Data Format */ |
| 910 | #define nOVR_FORM 0x0 | ||
| 911 | #define OUT_FORM 0x20 /* Output Data Format */ | 906 | #define OUT_FORM 0x20 /* Output Data Format */ |
| 912 | #define nOUT_FORM 0x0 | ||
| 913 | #define UDS_MOD 0x40 /* Resampling Mode */ | 907 | #define UDS_MOD 0x40 /* Resampling Mode */ |
| 914 | #define nUDS_MOD 0x0 | ||
| 915 | #define TC_EN 0x80 /* Transparent Color Enable */ | 908 | #define TC_EN 0x80 /* Transparent Color Enable */ |
| 916 | #define nTC_EN 0x0 | ||
| 917 | #define IMG_STAT 0x300 /* Image FIFO Status */ | 909 | #define IMG_STAT 0x300 /* Image FIFO Status */ |
| 918 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ | 910 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ |
| 919 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ | 911 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ |
| @@ -961,13 +953,9 @@ | |||
| 961 | /* Bit masks for PIXC_INTRSTAT */ | 953 | /* Bit masks for PIXC_INTRSTAT */ |
| 962 | 954 | ||
| 963 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ | 955 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ |
| 964 | #define nOVR_INT_EN 0x0 | ||
| 965 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ | 956 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ |
| 966 | #define nFRM_INT_EN 0x0 | ||
| 967 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ | 957 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ |
| 968 | #define nOVR_INT_STAT 0x0 | ||
| 969 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ | 958 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ |
| 970 | #define nFRM_INT_STAT 0x0 | ||
| 971 | 959 | ||
| 972 | /* Bit masks for PIXC_RYCON */ | 960 | /* Bit masks for PIXC_RYCON */ |
| 973 | 961 | ||
| @@ -975,7 +963,6 @@ | |||
| 975 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ | 963 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ |
| 976 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ | 964 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ |
| 977 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ | 965 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 978 | #define nRY_MULT4 0x0 | ||
| 979 | 966 | ||
| 980 | /* Bit masks for PIXC_GUCON */ | 967 | /* Bit masks for PIXC_GUCON */ |
| 981 | 968 | ||
| @@ -983,7 +970,6 @@ | |||
| 983 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ | 970 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ |
| 984 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ | 971 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ |
| 985 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ | 972 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 986 | #define nGU_MULT4 0x0 | ||
| 987 | 973 | ||
| 988 | /* Bit masks for PIXC_BVCON */ | 974 | /* Bit masks for PIXC_BVCON */ |
| 989 | 975 | ||
| @@ -991,7 +977,6 @@ | |||
| 991 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ | 977 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ |
| 992 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ | 978 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ |
| 993 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ | 979 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 994 | #define nBV_MULT4 0x0 | ||
| 995 | 980 | ||
| 996 | /* Bit masks for PIXC_CCBIAS */ | 981 | /* Bit masks for PIXC_CCBIAS */ |
| 997 | 982 | ||
| @@ -1008,48 +993,28 @@ | |||
| 1008 | /* Bit masks for HOST_CONTROL */ | 993 | /* Bit masks for HOST_CONTROL */ |
| 1009 | 994 | ||
| 1010 | #define HOST_EN 0x1 /* Host Enable */ | 995 | #define HOST_EN 0x1 /* Host Enable */ |
| 1011 | #define nHOST_EN 0x0 | ||
| 1012 | #define HOST_END 0x2 /* Host Endianess */ | 996 | #define HOST_END 0x2 /* Host Endianess */ |
| 1013 | #define nHOST_END 0x0 | ||
| 1014 | #define DATA_SIZE 0x4 /* Data Size */ | 997 | #define DATA_SIZE 0x4 /* Data Size */ |
| 1015 | #define nDATA_SIZE 0x0 | ||
| 1016 | #define HOST_RST 0x8 /* Host Reset */ | 998 | #define HOST_RST 0x8 /* Host Reset */ |
| 1017 | #define nHOST_RST 0x0 | ||
| 1018 | #define HRDY_OVR 0x20 /* Host Ready Override */ | 999 | #define HRDY_OVR 0x20 /* Host Ready Override */ |
| 1019 | #define nHRDY_OVR 0x0 | ||
| 1020 | #define INT_MODE 0x40 /* Interrupt Mode */ | 1000 | #define INT_MODE 0x40 /* Interrupt Mode */ |
| 1021 | #define nINT_MODE 0x0 | ||
| 1022 | #define BT_EN 0x80 /* Bus Timeout Enable */ | 1001 | #define BT_EN 0x80 /* Bus Timeout Enable */ |
| 1023 | #define nBT_EN 0x0 | ||
| 1024 | #define EHW 0x100 /* Enable Host Write */ | 1002 | #define EHW 0x100 /* Enable Host Write */ |
| 1025 | #define nEHW 0x0 | ||
| 1026 | #define EHR 0x200 /* Enable Host Read */ | 1003 | #define EHR 0x200 /* Enable Host Read */ |
| 1027 | #define nEHR 0x0 | ||
| 1028 | #define BDR 0x400 /* Burst DMA Requests */ | 1004 | #define BDR 0x400 /* Burst DMA Requests */ |
| 1029 | #define nBDR 0x0 | ||
| 1030 | 1005 | ||
| 1031 | /* Bit masks for HOST_STATUS */ | 1006 | /* Bit masks for HOST_STATUS */ |
| 1032 | 1007 | ||
| 1033 | #define READY 0x1 /* DMA Ready */ | 1008 | #define READY 0x1 /* DMA Ready */ |
| 1034 | #define nREADY 0x0 | ||
| 1035 | #define FIFOFULL 0x2 /* FIFO Full */ | 1009 | #define FIFOFULL 0x2 /* FIFO Full */ |
| 1036 | #define nFIFOFULL 0x0 | ||
| 1037 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | 1010 | #define FIFOEMPTY 0x4 /* FIFO Empty */ |
| 1038 | #define nFIFOEMPTY 0x0 | ||
| 1039 | #define COMPLETE 0x8 /* DMA Complete */ | 1011 | #define COMPLETE 0x8 /* DMA Complete */ |
| 1040 | #define nCOMPLETE 0x0 | ||
| 1041 | #define HSHK 0x10 /* Host Handshake */ | 1012 | #define HSHK 0x10 /* Host Handshake */ |
| 1042 | #define nHSHK 0x0 | ||
| 1043 | #define TIMEOUT 0x20 /* Host Timeout */ | 1013 | #define TIMEOUT 0x20 /* Host Timeout */ |
| 1044 | #define nTIMEOUT 0x0 | ||
| 1045 | #define HIRQ 0x40 /* Host Interrupt Request */ | 1014 | #define HIRQ 0x40 /* Host Interrupt Request */ |
| 1046 | #define nHIRQ 0x0 | ||
| 1047 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | 1015 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ |
| 1048 | #define nALLOW_CNFG 0x0 | ||
| 1049 | #define DMA_DIR 0x100 /* DMA Direction */ | 1016 | #define DMA_DIR 0x100 /* DMA Direction */ |
| 1050 | #define nDMA_DIR 0x0 | ||
| 1051 | #define BTE 0x200 /* Bus Timeout Enabled */ | 1017 | #define BTE 0x200 /* Bus Timeout Enabled */ |
| 1052 | #define nBTE 0x0 | ||
| 1053 | 1018 | ||
| 1054 | /* Bit masks for HOST_TIMEOUT */ | 1019 | /* Bit masks for HOST_TIMEOUT */ |
| 1055 | 1020 | ||
| @@ -1058,7 +1023,6 @@ | |||
| 1058 | /* Bit masks for KPAD_CTL */ | 1023 | /* Bit masks for KPAD_CTL */ |
| 1059 | 1024 | ||
| 1060 | #define KPAD_EN 0x1 /* Keypad Enable */ | 1025 | #define KPAD_EN 0x1 /* Keypad Enable */ |
| 1061 | #define nKPAD_EN 0x0 | ||
| 1062 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ | 1026 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ |
| 1063 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ | 1027 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ |
| 1064 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ | 1028 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ |
| @@ -1080,29 +1044,21 @@ | |||
| 1080 | /* Bit masks for KPAD_STAT */ | 1044 | /* Bit masks for KPAD_STAT */ |
| 1081 | 1045 | ||
| 1082 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ | 1046 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ |
| 1083 | #define nKPAD_IRQ 0x0 | ||
| 1084 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ | 1047 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ |
| 1085 | #define KPAD_PRESSED 0x8 /* Key press current status */ | 1048 | #define KPAD_PRESSED 0x8 /* Key press current status */ |
| 1086 | #define nKPAD_PRESSED 0x0 | ||
| 1087 | 1049 | ||
| 1088 | /* Bit masks for KPAD_SOFTEVAL */ | 1050 | /* Bit masks for KPAD_SOFTEVAL */ |
| 1089 | 1051 | ||
| 1090 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ | 1052 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ |
| 1091 | #define nKPAD_SOFTEVAL_E 0x0 | ||
| 1092 | 1053 | ||
| 1093 | /* Bit masks for SDH_COMMAND */ | 1054 | /* Bit masks for SDH_COMMAND */ |
| 1094 | 1055 | ||
| 1095 | #define CMD_IDX 0x3f /* Command Index */ | 1056 | #define CMD_IDX 0x3f /* Command Index */ |
| 1096 | #define CMD_RSP 0x40 /* Response */ | 1057 | #define CMD_RSP 0x40 /* Response */ |
| 1097 | #define nCMD_RSP 0x0 | ||
| 1098 | #define CMD_L_RSP 0x80 /* Long Response */ | 1058 | #define CMD_L_RSP 0x80 /* Long Response */ |
| 1099 | #define nCMD_L_RSP 0x0 | ||
| 1100 | #define CMD_INT_E 0x100 /* Command Interrupt */ | 1059 | #define CMD_INT_E 0x100 /* Command Interrupt */ |
| 1101 | #define nCMD_INT_E 0x0 | ||
| 1102 | #define CMD_PEND_E 0x200 /* Command Pending */ | 1060 | #define CMD_PEND_E 0x200 /* Command Pending */ |
| 1103 | #define nCMD_PEND_E 0x0 | ||
| 1104 | #define CMD_E 0x400 /* Command Enable */ | 1061 | #define CMD_E 0x400 /* Command Enable */ |
| 1105 | #define nCMD_E 0x0 | ||
| 1106 | 1062 | ||
| 1107 | /* Bit masks for SDH_PWR_CTL */ | 1063 | /* Bit masks for SDH_PWR_CTL */ |
| 1108 | 1064 | ||
| @@ -1111,21 +1067,15 @@ | |||
| 1111 | #define TBD 0x3c /* TBD */ | 1067 | #define TBD 0x3c /* TBD */ |
| 1112 | #endif | 1068 | #endif |
| 1113 | #define SD_CMD_OD 0x40 /* Open Drain Output */ | 1069 | #define SD_CMD_OD 0x40 /* Open Drain Output */ |
| 1114 | #define nSD_CMD_OD 0x0 | ||
| 1115 | #define ROD_CTL 0x80 /* Rod Control */ | 1070 | #define ROD_CTL 0x80 /* Rod Control */ |
| 1116 | #define nROD_CTL 0x0 | ||
| 1117 | 1071 | ||
| 1118 | /* Bit masks for SDH_CLK_CTL */ | 1072 | /* Bit masks for SDH_CLK_CTL */ |
| 1119 | 1073 | ||
| 1120 | #define CLKDIV 0xff /* MC_CLK Divisor */ | 1074 | #define CLKDIV 0xff /* MC_CLK Divisor */ |
| 1121 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ | 1075 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ |
| 1122 | #define nCLK_E 0x0 | ||
| 1123 | #define PWR_SV_E 0x200 /* Power Save Enable */ | 1076 | #define PWR_SV_E 0x200 /* Power Save Enable */ |
| 1124 | #define nPWR_SV_E 0x0 | ||
| 1125 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | 1077 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ |
| 1126 | #define nCLKDIV_BYPASS 0x0 | ||
| 1127 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ | 1078 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ |
| 1128 | #define nWIDE_BUS 0x0 | ||
| 1129 | 1079 | ||
| 1130 | /* Bit masks for SDH_RESP_CMD */ | 1080 | /* Bit masks for SDH_RESP_CMD */ |
| 1131 | 1081 | ||
| @@ -1134,133 +1084,74 @@ | |||
| 1134 | /* Bit masks for SDH_DATA_CTL */ | 1084 | /* Bit masks for SDH_DATA_CTL */ |
| 1135 | 1085 | ||
| 1136 | #define DTX_E 0x1 /* Data Transfer Enable */ | 1086 | #define DTX_E 0x1 /* Data Transfer Enable */ |
| 1137 | #define nDTX_E 0x0 | ||
| 1138 | #define DTX_DIR 0x2 /* Data Transfer Direction */ | 1087 | #define DTX_DIR 0x2 /* Data Transfer Direction */ |
| 1139 | #define nDTX_DIR 0x0 | ||
| 1140 | #define DTX_MODE 0x4 /* Data Transfer Mode */ | 1088 | #define DTX_MODE 0x4 /* Data Transfer Mode */ |
| 1141 | #define nDTX_MODE 0x0 | ||
| 1142 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | 1089 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ |
| 1143 | #define nDTX_DMA_E 0x0 | ||
| 1144 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | 1090 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ |
| 1145 | 1091 | ||
| 1146 | /* Bit masks for SDH_STATUS */ | 1092 | /* Bit masks for SDH_STATUS */ |
| 1147 | 1093 | ||
| 1148 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | 1094 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ |
| 1149 | #define nCMD_CRC_FAIL 0x0 | ||
| 1150 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | 1095 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ |
| 1151 | #define nDAT_CRC_FAIL 0x0 | ||
| 1152 | #define CMD_TIMEOUT 0x4 /* CMD Time Out */ | 1096 | #define CMD_TIMEOUT 0x4 /* CMD Time Out */ |
| 1153 | #define nCMD_TIMEOUT 0x0 | ||
| 1154 | #define DAT_TIMEOUT 0x8 /* Data Time Out */ | 1097 | #define DAT_TIMEOUT 0x8 /* Data Time Out */ |
| 1155 | #define nDAT_TIMEOUT 0x0 | ||
| 1156 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | 1098 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ |
| 1157 | #define nTX_UNDERRUN 0x0 | ||
| 1158 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | 1099 | #define RX_OVERRUN 0x20 /* Receive Overrun */ |
| 1159 | #define nRX_OVERRUN 0x0 | ||
| 1160 | #define CMD_RESP_END 0x40 /* CMD Response End */ | 1100 | #define CMD_RESP_END 0x40 /* CMD Response End */ |
| 1161 | #define nCMD_RESP_END 0x0 | ||
| 1162 | #define CMD_SENT 0x80 /* CMD Sent */ | 1101 | #define CMD_SENT 0x80 /* CMD Sent */ |
| 1163 | #define nCMD_SENT 0x0 | ||
| 1164 | #define DAT_END 0x100 /* Data End */ | 1102 | #define DAT_END 0x100 /* Data End */ |
| 1165 | #define nDAT_END 0x0 | ||
| 1166 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | 1103 | #define START_BIT_ERR 0x200 /* Start Bit Error */ |
| 1167 | #define nSTART_BIT_ERR 0x0 | ||
| 1168 | #define DAT_BLK_END 0x400 /* Data Block End */ | 1104 | #define DAT_BLK_END 0x400 /* Data Block End */ |
| 1169 | #define nDAT_BLK_END 0x0 | ||
| 1170 | #define CMD_ACT 0x800 /* CMD Active */ | 1105 | #define CMD_ACT 0x800 /* CMD Active */ |
| 1171 | #define nCMD_ACT 0x0 | ||
| 1172 | #define TX_ACT 0x1000 /* Transmit Active */ | 1106 | #define TX_ACT 0x1000 /* Transmit Active */ |
| 1173 | #define nTX_ACT 0x0 | ||
| 1174 | #define RX_ACT 0x2000 /* Receive Active */ | 1107 | #define RX_ACT 0x2000 /* Receive Active */ |
| 1175 | #define nRX_ACT 0x0 | ||
| 1176 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | 1108 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ |
| 1177 | #define nTX_FIFO_STAT 0x0 | ||
| 1178 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | 1109 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ |
| 1179 | #define nRX_FIFO_STAT 0x0 | ||
| 1180 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | 1110 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ |
| 1181 | #define nTX_FIFO_FULL 0x0 | ||
| 1182 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | 1111 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ |
| 1183 | #define nRX_FIFO_FULL 0x0 | ||
| 1184 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | 1112 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ |
| 1185 | #define nTX_FIFO_ZERO 0x0 | ||
| 1186 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | 1113 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ |
| 1187 | #define nRX_DAT_ZERO 0x0 | ||
| 1188 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | 1114 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ |
| 1189 | #define nTX_DAT_RDY 0x0 | ||
| 1190 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | 1115 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ |
| 1191 | #define nRX_FIFO_RDY 0x0 | ||
| 1192 | 1116 | ||
| 1193 | /* Bit masks for SDH_STATUS_CLR */ | 1117 | /* Bit masks for SDH_STATUS_CLR */ |
| 1194 | 1118 | ||
| 1195 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | 1119 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ |
| 1196 | #define nCMD_CRC_FAIL_STAT 0x0 | ||
| 1197 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | 1120 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ |
| 1198 | #define nDAT_CRC_FAIL_STAT 0x0 | ||
| 1199 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | 1121 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ |
| 1200 | #define nCMD_TIMEOUT_STAT 0x0 | ||
| 1201 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | 1122 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ |
| 1202 | #define nDAT_TIMEOUT_STAT 0x0 | ||
| 1203 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | 1123 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ |
| 1204 | #define nTX_UNDERRUN_STAT 0x0 | ||
| 1205 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | 1124 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ |
| 1206 | #define nRX_OVERRUN_STAT 0x0 | ||
| 1207 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | 1125 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ |
| 1208 | #define nCMD_RESP_END_STAT 0x0 | ||
| 1209 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | 1126 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ |
| 1210 | #define nCMD_SENT_STAT 0x0 | ||
| 1211 | #define DAT_END_STAT 0x100 /* Data End Status */ | 1127 | #define DAT_END_STAT 0x100 /* Data End Status */ |
| 1212 | #define nDAT_END_STAT 0x0 | ||
| 1213 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | 1128 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ |
| 1214 | #define nSTART_BIT_ERR_STAT 0x0 | ||
| 1215 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | 1129 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ |
| 1216 | #define nDAT_BLK_END_STAT 0x0 | ||
| 1217 | 1130 | ||
| 1218 | /* Bit masks for SDH_MASK0 */ | 1131 | /* Bit masks for SDH_MASK0 */ |
| 1219 | 1132 | ||
| 1220 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | 1133 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ |
| 1221 | #define nCMD_CRC_FAIL_MASK 0x0 | ||
| 1222 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | 1134 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ |
| 1223 | #define nDAT_CRC_FAIL_MASK 0x0 | ||
| 1224 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | 1135 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ |
| 1225 | #define nCMD_TIMEOUT_MASK 0x0 | ||
| 1226 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | 1136 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ |
| 1227 | #define nDAT_TIMEOUT_MASK 0x0 | ||
| 1228 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | 1137 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ |
| 1229 | #define nTX_UNDERRUN_MASK 0x0 | ||
| 1230 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | 1138 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ |
| 1231 | #define nRX_OVERRUN_MASK 0x0 | ||
| 1232 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | 1139 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ |
| 1233 | #define nCMD_RESP_END_MASK 0x0 | ||
| 1234 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | 1140 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ |
| 1235 | #define nCMD_SENT_MASK 0x0 | ||
| 1236 | #define DAT_END_MASK 0x100 /* Data End Mask */ | 1141 | #define DAT_END_MASK 0x100 /* Data End Mask */ |
| 1237 | #define nDAT_END_MASK 0x0 | ||
| 1238 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | 1142 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ |
| 1239 | #define nSTART_BIT_ERR_MASK 0x0 | ||
| 1240 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | 1143 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ |
| 1241 | #define nDAT_BLK_END_MASK 0x0 | ||
| 1242 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | 1144 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ |
| 1243 | #define nCMD_ACT_MASK 0x0 | ||
| 1244 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | 1145 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ |
| 1245 | #define nTX_ACT_MASK 0x0 | ||
| 1246 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | 1146 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ |
| 1247 | #define nRX_ACT_MASK 0x0 | ||
| 1248 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | 1147 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ |
| 1249 | #define nTX_FIFO_STAT_MASK 0x0 | ||
| 1250 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | 1148 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ |
| 1251 | #define nRX_FIFO_STAT_MASK 0x0 | ||
| 1252 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | 1149 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ |
| 1253 | #define nTX_FIFO_FULL_MASK 0x0 | ||
| 1254 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | 1150 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ |
| 1255 | #define nRX_FIFO_FULL_MASK 0x0 | ||
| 1256 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | 1151 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ |
| 1257 | #define nTX_FIFO_ZERO_MASK 0x0 | ||
| 1258 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | 1152 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ |
| 1259 | #define nRX_DAT_ZERO_MASK 0x0 | ||
| 1260 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | 1153 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ |
| 1261 | #define nTX_DAT_RDY_MASK 0x0 | ||
| 1262 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | 1154 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ |
| 1263 | #define nRX_FIFO_RDY_MASK 0x0 | ||
| 1264 | 1155 | ||
| 1265 | /* Bit masks for SDH_FIFO_CNT */ | 1156 | /* Bit masks for SDH_FIFO_CNT */ |
| 1266 | 1157 | ||
| @@ -1269,73 +1160,47 @@ | |||
| 1269 | /* Bit masks for SDH_E_STATUS */ | 1160 | /* Bit masks for SDH_E_STATUS */ |
| 1270 | 1161 | ||
| 1271 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | 1162 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ |
| 1272 | #define nSDIO_INT_DET 0x0 | ||
| 1273 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | 1163 | #define SD_CARD_DET 0x10 /* SD Card Detect */ |
| 1274 | #define nSD_CARD_DET 0x0 | ||
| 1275 | 1164 | ||
| 1276 | /* Bit masks for SDH_E_MASK */ | 1165 | /* Bit masks for SDH_E_MASK */ |
| 1277 | 1166 | ||
| 1278 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ | 1167 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ |
| 1279 | #define nSDIO_MSK 0x0 | ||
| 1280 | #define SCD_MSK 0x40 /* Mask Card Detect */ | 1168 | #define SCD_MSK 0x40 /* Mask Card Detect */ |
| 1281 | #define nSCD_MSK 0x0 | ||
| 1282 | 1169 | ||
| 1283 | /* Bit masks for SDH_CFG */ | 1170 | /* Bit masks for SDH_CFG */ |
| 1284 | 1171 | ||
| 1285 | #define CLKS_EN 0x1 /* Clocks Enable */ | 1172 | #define CLKS_EN 0x1 /* Clocks Enable */ |
| 1286 | #define nCLKS_EN 0x0 | ||
| 1287 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ | 1173 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ |
| 1288 | #define nSD4E 0x0 | ||
| 1289 | #define MWE 0x8 /* Moving Window Enable */ | 1174 | #define MWE 0x8 /* Moving Window Enable */ |
| 1290 | #define nMWE 0x0 | ||
| 1291 | #define SD_RST 0x10 /* SDMMC Reset */ | 1175 | #define SD_RST 0x10 /* SDMMC Reset */ |
| 1292 | #define nSD_RST 0x0 | ||
| 1293 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ | 1176 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ |
| 1294 | #define nPUP_SDDAT 0x0 | ||
| 1295 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ | 1177 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ |
| 1296 | #define nPUP_SDDAT3 0x0 | ||
| 1297 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ | 1178 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ |
| 1298 | #define nPD_SDDAT3 0x0 | ||
| 1299 | 1179 | ||
| 1300 | /* Bit masks for SDH_RD_WAIT_EN */ | 1180 | /* Bit masks for SDH_RD_WAIT_EN */ |
| 1301 | 1181 | ||
| 1302 | #define RWR 0x1 /* Read Wait Request */ | 1182 | #define RWR 0x1 /* Read Wait Request */ |
| 1303 | #define nRWR 0x0 | ||
| 1304 | 1183 | ||
| 1305 | /* Bit masks for ATAPI_CONTROL */ | 1184 | /* Bit masks for ATAPI_CONTROL */ |
| 1306 | 1185 | ||
| 1307 | #define PIO_START 0x1 /* Start PIO/Reg Op */ | 1186 | #define PIO_START 0x1 /* Start PIO/Reg Op */ |
| 1308 | #define nPIO_START 0x0 | ||
| 1309 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ | 1187 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ |
| 1310 | #define nMULTI_START 0x0 | ||
| 1311 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ | 1188 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ |
| 1312 | #define nULTRA_START 0x0 | ||
| 1313 | #define XFER_DIR 0x8 /* Transfer Direction */ | 1189 | #define XFER_DIR 0x8 /* Transfer Direction */ |
| 1314 | #define nXFER_DIR 0x0 | ||
| 1315 | #define IORDY_EN 0x10 /* IORDY Enable */ | 1190 | #define IORDY_EN 0x10 /* IORDY Enable */ |
| 1316 | #define nIORDY_EN 0x0 | ||
| 1317 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ | 1191 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ |
| 1318 | #define nFIFO_FLUSH 0x0 | ||
| 1319 | #define SOFT_RST 0x40 /* Soft Reset */ | 1192 | #define SOFT_RST 0x40 /* Soft Reset */ |
| 1320 | #define nSOFT_RST 0x0 | ||
| 1321 | #define DEV_RST 0x80 /* Device Reset */ | 1193 | #define DEV_RST 0x80 /* Device Reset */ |
| 1322 | #define nDEV_RST 0x0 | ||
| 1323 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ | 1194 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ |
| 1324 | #define nTFRCNT_RST 0x0 | ||
| 1325 | #define END_ON_TERM 0x200 /* End/Terminate Select */ | 1195 | #define END_ON_TERM 0x200 /* End/Terminate Select */ |
| 1326 | #define nEND_ON_TERM 0x0 | ||
| 1327 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ | 1196 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ |
| 1328 | #define nPIO_USE_DMA 0x0 | ||
| 1329 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ | 1197 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ |
| 1330 | 1198 | ||
| 1331 | /* Bit masks for ATAPI_STATUS */ | 1199 | /* Bit masks for ATAPI_STATUS */ |
| 1332 | 1200 | ||
| 1333 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ | 1201 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ |
| 1334 | #define nPIO_XFER_ON 0x0 | ||
| 1335 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ | 1202 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ |
| 1336 | #define nMULTI_XFER_ON 0x0 | ||
| 1337 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ | 1203 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ |
| 1338 | #define nULTRA_XFER_ON 0x0 | ||
| 1339 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ | 1204 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ |
| 1340 | 1205 | ||
| 1341 | /* Bit masks for ATAPI_DEV_ADDR */ | 1206 | /* Bit masks for ATAPI_DEV_ADDR */ |
| @@ -1345,66 +1210,39 @@ | |||
| 1345 | /* Bit masks for ATAPI_INT_MASK */ | 1210 | /* Bit masks for ATAPI_INT_MASK */ |
| 1346 | 1211 | ||
| 1347 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ | 1212 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ |
| 1348 | #define nATAPI_DEV_INT_MASK 0x0 | ||
| 1349 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ | 1213 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ |
| 1350 | #define nPIO_DONE_MASK 0x0 | ||
| 1351 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ | 1214 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ |
| 1352 | #define nMULTI_DONE_MASK 0x0 | ||
| 1353 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ | 1215 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ |
| 1354 | #define nUDMAIN_DONE_MASK 0x0 | ||
| 1355 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ | 1216 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ |
| 1356 | #define nUDMAOUT_DONE_MASK 0x0 | ||
| 1357 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ | 1217 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ |
| 1358 | #define nHOST_TERM_XFER_MASK 0x0 | ||
| 1359 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ | 1218 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ |
| 1360 | #define nMULTI_TERM_MASK 0x0 | ||
| 1361 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ | 1219 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ |
| 1362 | #define nUDMAIN_TERM_MASK 0x0 | ||
| 1363 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ | 1220 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ |
| 1364 | #define nUDMAOUT_TERM_MASK 0x0 | ||
| 1365 | 1221 | ||
| 1366 | /* Bit masks for ATAPI_INT_STATUS */ | 1222 | /* Bit masks for ATAPI_INT_STATUS */ |
| 1367 | 1223 | ||
| 1368 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ | 1224 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ |
| 1369 | #define nATAPI_DEV_INT 0x0 | ||
| 1370 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ | 1225 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ |
| 1371 | #define nPIO_DONE_INT 0x0 | ||
| 1372 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ | 1226 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ |
| 1373 | #define nMULTI_DONE_INT 0x0 | ||
| 1374 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ | 1227 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ |
| 1375 | #define nUDMAIN_DONE_INT 0x0 | ||
| 1376 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ | 1228 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ |
| 1377 | #define nUDMAOUT_DONE_INT 0x0 | ||
| 1378 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ | 1229 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ |
| 1379 | #define nHOST_TERM_XFER_INT 0x0 | ||
| 1380 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ | 1230 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ |
| 1381 | #define nMULTI_TERM_INT 0x0 | ||
| 1382 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ | 1231 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ |
| 1383 | #define nUDMAIN_TERM_INT 0x0 | ||
| 1384 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ | 1232 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ |
| 1385 | #define nUDMAOUT_TERM_INT 0x0 | ||
| 1386 | 1233 | ||
| 1387 | /* Bit masks for ATAPI_LINE_STATUS */ | 1234 | /* Bit masks for ATAPI_LINE_STATUS */ |
| 1388 | 1235 | ||
| 1389 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ | 1236 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ |
| 1390 | #define nATAPI_INTR 0x0 | ||
| 1391 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ | 1237 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ |
| 1392 | #define nATAPI_DASP 0x0 | ||
| 1393 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ | 1238 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ |
| 1394 | #define nATAPI_CS0N 0x0 | ||
| 1395 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ | 1239 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ |
| 1396 | #define nATAPI_CS1N 0x0 | ||
| 1397 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ | 1240 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ |
| 1398 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ | 1241 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ |
| 1399 | #define nATAPI_DMAREQ 0x0 | ||
| 1400 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ | 1242 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ |
| 1401 | #define nATAPI_DMAACKN 0x0 | ||
| 1402 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ | 1243 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ |
| 1403 | #define nATAPI_DIOWN 0x0 | ||
| 1404 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ | 1244 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ |
| 1405 | #define nATAPI_DIORN 0x0 | ||
| 1406 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ | 1245 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ |
| 1407 | #define nATAPI_IORDY 0x0 | ||
| 1408 | 1246 | ||
| 1409 | /* Bit masks for ATAPI_SM_STATE */ | 1247 | /* Bit masks for ATAPI_SM_STATE */ |
| 1410 | 1248 | ||
| @@ -1416,7 +1254,6 @@ | |||
| 1416 | /* Bit masks for ATAPI_TERMINATE */ | 1254 | /* Bit masks for ATAPI_TERMINATE */ |
| 1417 | 1255 | ||
| 1418 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ | 1256 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ |
| 1419 | #define nATAPI_HOST_TERM 0x0 | ||
| 1420 | 1257 | ||
| 1421 | /* Bit masks for ATAPI_REG_TIM_0 */ | 1258 | /* Bit masks for ATAPI_REG_TIM_0 */ |
| 1422 | 1259 | ||
| @@ -1471,41 +1308,26 @@ | |||
| 1471 | /* Bit masks for TIMER_ENABLE1 */ | 1308 | /* Bit masks for TIMER_ENABLE1 */ |
| 1472 | 1309 | ||
| 1473 | #define TIMEN8 0x1 /* Timer 8 Enable */ | 1310 | #define TIMEN8 0x1 /* Timer 8 Enable */ |
| 1474 | #define nTIMEN8 0x0 | ||
| 1475 | #define TIMEN9 0x2 /* Timer 9 Enable */ | 1311 | #define TIMEN9 0x2 /* Timer 9 Enable */ |
| 1476 | #define nTIMEN9 0x0 | ||
| 1477 | #define TIMEN10 0x4 /* Timer 10 Enable */ | 1312 | #define TIMEN10 0x4 /* Timer 10 Enable */ |
| 1478 | #define nTIMEN10 0x0 | ||
| 1479 | 1313 | ||
| 1480 | /* Bit masks for TIMER_DISABLE1 */ | 1314 | /* Bit masks for TIMER_DISABLE1 */ |
| 1481 | 1315 | ||
| 1482 | #define TIMDIS8 0x1 /* Timer 8 Disable */ | 1316 | #define TIMDIS8 0x1 /* Timer 8 Disable */ |
| 1483 | #define nTIMDIS8 0x0 | ||
| 1484 | #define TIMDIS9 0x2 /* Timer 9 Disable */ | 1317 | #define TIMDIS9 0x2 /* Timer 9 Disable */ |
| 1485 | #define nTIMDIS9 0x0 | ||
| 1486 | #define TIMDIS10 0x4 /* Timer 10 Disable */ | 1318 | #define TIMDIS10 0x4 /* Timer 10 Disable */ |
| 1487 | #define nTIMDIS10 0x0 | ||
| 1488 | 1319 | ||
| 1489 | /* Bit masks for TIMER_STATUS1 */ | 1320 | /* Bit masks for TIMER_STATUS1 */ |
| 1490 | 1321 | ||
| 1491 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ | 1322 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ |
| 1492 | #define nTIMIL8 0x0 | ||
| 1493 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ | 1323 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ |
| 1494 | #define nTIMIL9 0x0 | ||
| 1495 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ | 1324 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ |
| 1496 | #define nTIMIL10 0x0 | ||
| 1497 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ | 1325 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ |
| 1498 | #define nTOVF_ERR8 0x0 | ||
| 1499 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ | 1326 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ |
| 1500 | #define nTOVF_ERR9 0x0 | ||
| 1501 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ | 1327 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ |
| 1502 | #define nTOVF_ERR10 0x0 | ||
| 1503 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ | 1328 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ |
| 1504 | #define nTRUN8 0x0 | ||
| 1505 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ | 1329 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ |
| 1506 | #define nTRUN9 0x0 | ||
| 1507 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ | 1330 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ |
| 1508 | #define nTRUN10 0x0 | ||
| 1509 | 1331 | ||
| 1510 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ | 1332 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ |
| 1511 | 1333 | ||
| @@ -1516,131 +1338,77 @@ | |||
| 1516 | /* Bit masks for USB_POWER */ | 1338 | /* Bit masks for USB_POWER */ |
| 1517 | 1339 | ||
| 1518 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | 1340 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ |
| 1519 | #define nENABLE_SUSPENDM 0x0 | ||
| 1520 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | 1341 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ |
| 1521 | #define nSUSPEND_MODE 0x0 | ||
| 1522 | #define RESUME_MODE 0x4 /* DMA Mode */ | 1342 | #define RESUME_MODE 0x4 /* DMA Mode */ |
| 1523 | #define nRESUME_MODE 0x0 | ||
| 1524 | #define RESET 0x8 /* Reset indicator */ | 1343 | #define RESET 0x8 /* Reset indicator */ |
| 1525 | #define nRESET 0x0 | ||
| 1526 | #define HS_MODE 0x10 /* High Speed mode indicator */ | 1344 | #define HS_MODE 0x10 /* High Speed mode indicator */ |
| 1527 | #define nHS_MODE 0x0 | ||
| 1528 | #define HS_ENABLE 0x20 /* high Speed Enable */ | 1345 | #define HS_ENABLE 0x20 /* high Speed Enable */ |
| 1529 | #define nHS_ENABLE 0x0 | ||
| 1530 | #define SOFT_CONN 0x40 /* Soft connect */ | 1346 | #define SOFT_CONN 0x40 /* Soft connect */ |
| 1531 | #define nSOFT_CONN 0x0 | ||
| 1532 | #define ISO_UPDATE 0x80 /* Isochronous update */ | 1347 | #define ISO_UPDATE 0x80 /* Isochronous update */ |
| 1533 | #define nISO_UPDATE 0x0 | ||
| 1534 | 1348 | ||
| 1535 | /* Bit masks for USB_INTRTX */ | 1349 | /* Bit masks for USB_INTRTX */ |
| 1536 | 1350 | ||
| 1537 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | 1351 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ |
| 1538 | #define nEP0_TX 0x0 | ||
| 1539 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | 1352 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ |
| 1540 | #define nEP1_TX 0x0 | ||
| 1541 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | 1353 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ |
| 1542 | #define nEP2_TX 0x0 | ||
| 1543 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | 1354 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ |
| 1544 | #define nEP3_TX 0x0 | ||
| 1545 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | 1355 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ |
| 1546 | #define nEP4_TX 0x0 | ||
| 1547 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | 1356 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ |
| 1548 | #define nEP5_TX 0x0 | ||
| 1549 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | 1357 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ |
| 1550 | #define nEP6_TX 0x0 | ||
| 1551 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | 1358 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ |
| 1552 | #define nEP7_TX 0x0 | ||
| 1553 | 1359 | ||
| 1554 | /* Bit masks for USB_INTRRX */ | 1360 | /* Bit masks for USB_INTRRX */ |
| 1555 | 1361 | ||
| 1556 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | 1362 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ |
| 1557 | #define nEP1_RX 0x0 | ||
| 1558 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | 1363 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ |
| 1559 | #define nEP2_RX 0x0 | ||
| 1560 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | 1364 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ |
| 1561 | #define nEP3_RX 0x0 | ||
| 1562 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | 1365 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ |
| 1563 | #define nEP4_RX 0x0 | ||
| 1564 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | 1366 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ |
| 1565 | #define nEP5_RX 0x0 | ||
| 1566 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | 1367 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ |
| 1567 | #define nEP6_RX 0x0 | ||
| 1568 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | 1368 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ |
| 1569 | #define nEP7_RX 0x0 | ||
| 1570 | 1369 | ||
| 1571 | /* Bit masks for USB_INTRTXE */ | 1370 | /* Bit masks for USB_INTRTXE */ |
| 1572 | 1371 | ||
| 1573 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | 1372 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ |
| 1574 | #define nEP0_TX_E 0x0 | ||
| 1575 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | 1373 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ |
| 1576 | #define nEP1_TX_E 0x0 | ||
| 1577 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | 1374 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ |
| 1578 | #define nEP2_TX_E 0x0 | ||
| 1579 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | 1375 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ |
| 1580 | #define nEP3_TX_E 0x0 | ||
| 1581 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | 1376 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ |
| 1582 | #define nEP4_TX_E 0x0 | ||
| 1583 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | 1377 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ |
| 1584 | #define nEP5_TX_E 0x0 | ||
| 1585 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | 1378 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ |
| 1586 | #define nEP6_TX_E 0x0 | ||
| 1587 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | 1379 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ |
| 1588 | #define nEP7_TX_E 0x0 | ||
| 1589 | 1380 | ||
| 1590 | /* Bit masks for USB_INTRRXE */ | 1381 | /* Bit masks for USB_INTRRXE */ |
| 1591 | 1382 | ||
| 1592 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | 1383 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ |
| 1593 | #define nEP1_RX_E 0x0 | ||
| 1594 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | 1384 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ |
| 1595 | #define nEP2_RX_E 0x0 | ||
| 1596 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | 1385 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ |
| 1597 | #define nEP3_RX_E 0x0 | ||
| 1598 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | 1386 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ |
| 1599 | #define nEP4_RX_E 0x0 | ||
| 1600 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | 1387 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ |
| 1601 | #define nEP5_RX_E 0x0 | ||
| 1602 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | 1388 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ |
| 1603 | #define nEP6_RX_E 0x0 | ||
| 1604 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | 1389 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ |
| 1605 | #define nEP7_RX_E 0x0 | ||
| 1606 | 1390 | ||
| 1607 | /* Bit masks for USB_INTRUSB */ | 1391 | /* Bit masks for USB_INTRUSB */ |
| 1608 | 1392 | ||
| 1609 | #define SUSPEND_B 0x1 /* Suspend indicator */ | 1393 | #define SUSPEND_B 0x1 /* Suspend indicator */ |
| 1610 | #define nSUSPEND_B 0x0 | ||
| 1611 | #define RESUME_B 0x2 /* Resume indicator */ | 1394 | #define RESUME_B 0x2 /* Resume indicator */ |
| 1612 | #define nRESUME_B 0x0 | ||
| 1613 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | 1395 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ |
| 1614 | #define nRESET_OR_BABLE_B 0x0 | ||
| 1615 | #define SOF_B 0x8 /* Start of frame */ | 1396 | #define SOF_B 0x8 /* Start of frame */ |
| 1616 | #define nSOF_B 0x0 | ||
| 1617 | #define CONN_B 0x10 /* Connection indicator */ | 1397 | #define CONN_B 0x10 /* Connection indicator */ |
| 1618 | #define nCONN_B 0x0 | ||
| 1619 | #define DISCON_B 0x20 /* Disconnect indicator */ | 1398 | #define DISCON_B 0x20 /* Disconnect indicator */ |
| 1620 | #define nDISCON_B 0x0 | ||
| 1621 | #define SESSION_REQ_B 0x40 /* Session Request */ | 1399 | #define SESSION_REQ_B 0x40 /* Session Request */ |
| 1622 | #define nSESSION_REQ_B 0x0 | ||
| 1623 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | 1400 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ |
| 1624 | #define nVBUS_ERROR_B 0x0 | ||
| 1625 | 1401 | ||
| 1626 | /* Bit masks for USB_INTRUSBE */ | 1402 | /* Bit masks for USB_INTRUSBE */ |
| 1627 | 1403 | ||
| 1628 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | 1404 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ |
| 1629 | #define nSUSPEND_BE 0x0 | ||
| 1630 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | 1405 | #define RESUME_BE 0x2 /* Resume indicator int enable */ |
| 1631 | #define nRESUME_BE 0x0 | ||
| 1632 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | 1406 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ |
| 1633 | #define nRESET_OR_BABLE_BE 0x0 | ||
| 1634 | #define SOF_BE 0x8 /* Start of frame int enable */ | 1407 | #define SOF_BE 0x8 /* Start of frame int enable */ |
| 1635 | #define nSOF_BE 0x0 | ||
| 1636 | #define CONN_BE 0x10 /* Connection indicator int enable */ | 1408 | #define CONN_BE 0x10 /* Connection indicator int enable */ |
| 1637 | #define nCONN_BE 0x0 | ||
| 1638 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | 1409 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ |
| 1639 | #define nDISCON_BE 0x0 | ||
| 1640 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | 1410 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ |
| 1641 | #define nSESSION_REQ_BE 0x0 | ||
| 1642 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | 1411 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ |
| 1643 | #define nVBUS_ERROR_BE 0x0 | ||
| 1644 | 1412 | ||
| 1645 | /* Bit masks for USB_FRAME */ | 1413 | /* Bit masks for USB_FRAME */ |
| 1646 | 1414 | ||
| @@ -1653,117 +1421,67 @@ | |||
| 1653 | /* Bit masks for USB_GLOBAL_CTL */ | 1421 | /* Bit masks for USB_GLOBAL_CTL */ |
| 1654 | 1422 | ||
| 1655 | #define GLOBAL_ENA 0x1 /* enables USB module */ | 1423 | #define GLOBAL_ENA 0x1 /* enables USB module */ |
| 1656 | #define nGLOBAL_ENA 0x0 | ||
| 1657 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | 1424 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ |
| 1658 | #define nEP1_TX_ENA 0x0 | ||
| 1659 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | 1425 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ |
| 1660 | #define nEP2_TX_ENA 0x0 | ||
| 1661 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | 1426 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ |
| 1662 | #define nEP3_TX_ENA 0x0 | ||
| 1663 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | 1427 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ |
| 1664 | #define nEP4_TX_ENA 0x0 | ||
| 1665 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | 1428 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ |
| 1666 | #define nEP5_TX_ENA 0x0 | ||
| 1667 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | 1429 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ |
| 1668 | #define nEP6_TX_ENA 0x0 | ||
| 1669 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | 1430 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ |
| 1670 | #define nEP7_TX_ENA 0x0 | ||
| 1671 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | 1431 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ |
| 1672 | #define nEP1_RX_ENA 0x0 | ||
| 1673 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | 1432 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ |
| 1674 | #define nEP2_RX_ENA 0x0 | ||
| 1675 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | 1433 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ |
| 1676 | #define nEP3_RX_ENA 0x0 | ||
| 1677 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | 1434 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ |
| 1678 | #define nEP4_RX_ENA 0x0 | ||
| 1679 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | 1435 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ |
| 1680 | #define nEP5_RX_ENA 0x0 | ||
| 1681 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | 1436 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ |
| 1682 | #define nEP6_RX_ENA 0x0 | ||
| 1683 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | 1437 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ |
| 1684 | #define nEP7_RX_ENA 0x0 | ||
| 1685 | 1438 | ||
| 1686 | /* Bit masks for USB_OTG_DEV_CTL */ | 1439 | /* Bit masks for USB_OTG_DEV_CTL */ |
| 1687 | 1440 | ||
| 1688 | #define SESSION 0x1 /* session indicator */ | 1441 | #define SESSION 0x1 /* session indicator */ |
| 1689 | #define nSESSION 0x0 | ||
| 1690 | #define HOST_REQ 0x2 /* Host negotiation request */ | 1442 | #define HOST_REQ 0x2 /* Host negotiation request */ |
| 1691 | #define nHOST_REQ 0x0 | ||
| 1692 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | 1443 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ |
| 1693 | #define nHOST_MODE 0x0 | ||
| 1694 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | 1444 | #define VBUS0 0x8 /* Vbus level indicator[0] */ |
| 1695 | #define nVBUS0 0x0 | ||
| 1696 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | 1445 | #define VBUS1 0x10 /* Vbus level indicator[1] */ |
| 1697 | #define nVBUS1 0x0 | ||
| 1698 | #define LSDEV 0x20 /* Low-speed indicator */ | 1446 | #define LSDEV 0x20 /* Low-speed indicator */ |
| 1699 | #define nLSDEV 0x0 | ||
| 1700 | #define FSDEV 0x40 /* Full or High-speed indicator */ | 1447 | #define FSDEV 0x40 /* Full or High-speed indicator */ |
| 1701 | #define nFSDEV 0x0 | ||
| 1702 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | 1448 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ |
| 1703 | #define nB_DEVICE 0x0 | ||
| 1704 | 1449 | ||
| 1705 | /* Bit masks for USB_OTG_VBUS_IRQ */ | 1450 | /* Bit masks for USB_OTG_VBUS_IRQ */ |
| 1706 | 1451 | ||
| 1707 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | 1452 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ |
| 1708 | #define nDRIVE_VBUS_ON 0x0 | ||
| 1709 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | 1453 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ |
| 1710 | #define nDRIVE_VBUS_OFF 0x0 | ||
| 1711 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | 1454 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ |
| 1712 | #define nCHRG_VBUS_START 0x0 | ||
| 1713 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | 1455 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ |
| 1714 | #define nCHRG_VBUS_END 0x0 | ||
| 1715 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | 1456 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ |
| 1716 | #define nDISCHRG_VBUS_START 0x0 | ||
| 1717 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | 1457 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ |
| 1718 | #define nDISCHRG_VBUS_END 0x0 | ||
| 1719 | 1458 | ||
| 1720 | /* Bit masks for USB_OTG_VBUS_MASK */ | 1459 | /* Bit masks for USB_OTG_VBUS_MASK */ |
| 1721 | 1460 | ||
| 1722 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | 1461 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ |
| 1723 | #define nDRIVE_VBUS_ON_ENA 0x0 | ||
| 1724 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | 1462 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ |
| 1725 | #define nDRIVE_VBUS_OFF_ENA 0x0 | ||
| 1726 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | 1463 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ |
| 1727 | #define nCHRG_VBUS_START_ENA 0x0 | ||
| 1728 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | 1464 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ |
| 1729 | #define nCHRG_VBUS_END_ENA 0x0 | ||
| 1730 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | 1465 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ |
| 1731 | #define nDISCHRG_VBUS_START_ENA 0x0 | ||
| 1732 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | 1466 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ |
| 1733 | #define nDISCHRG_VBUS_END_ENA 0x0 | ||
| 1734 | 1467 | ||
| 1735 | /* Bit masks for USB_CSR0 */ | 1468 | /* Bit masks for USB_CSR0 */ |
| 1736 | 1469 | ||
| 1737 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | 1470 | #define RXPKTRDY 0x1 /* data packet receive indicator */ |
| 1738 | #define nRXPKTRDY 0x0 | ||
| 1739 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | 1471 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ |
| 1740 | #define nTXPKTRDY 0x0 | ||
| 1741 | #define STALL_SENT 0x4 /* STALL handshake sent */ | 1472 | #define STALL_SENT 0x4 /* STALL handshake sent */ |
| 1742 | #define nSTALL_SENT 0x0 | ||
| 1743 | #define DATAEND 0x8 /* Data end indicator */ | 1473 | #define DATAEND 0x8 /* Data end indicator */ |
| 1744 | #define nDATAEND 0x0 | ||
| 1745 | #define SETUPEND 0x10 /* Setup end */ | 1474 | #define SETUPEND 0x10 /* Setup end */ |
| 1746 | #define nSETUPEND 0x0 | ||
| 1747 | #define SENDSTALL 0x20 /* Send STALL handshake */ | 1475 | #define SENDSTALL 0x20 /* Send STALL handshake */ |
| 1748 | #define nSENDSTALL 0x0 | ||
| 1749 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | 1476 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ |
| 1750 | #define nSERVICED_RXPKTRDY 0x0 | ||
| 1751 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | 1477 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ |
| 1752 | #define nSERVICED_SETUPEND 0x0 | ||
| 1753 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | 1478 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ |
| 1754 | #define nFLUSHFIFO 0x0 | ||
| 1755 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | 1479 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ |
| 1756 | #define nSTALL_RECEIVED_H 0x0 | ||
| 1757 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | 1480 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ |
| 1758 | #define nSETUPPKT_H 0x0 | ||
| 1759 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | 1481 | #define ERROR_H 0x10 /* timeout error indicator host mode */ |
| 1760 | #define nERROR_H 0x0 | ||
| 1761 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | 1482 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ |
| 1762 | #define nREQPKT_H 0x0 | ||
| 1763 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | 1483 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ |
| 1764 | #define nSTATUSPKT_H 0x0 | ||
| 1765 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | 1484 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ |
| 1766 | #define nNAK_TIMEOUT_H 0x0 | ||
| 1767 | 1485 | ||
| 1768 | /* Bit masks for USB_COUNT0 */ | 1486 | /* Bit masks for USB_COUNT0 */ |
| 1769 | 1487 | ||
| @@ -1784,37 +1502,21 @@ | |||
| 1784 | /* Bit masks for USB_TXCSR */ | 1502 | /* Bit masks for USB_TXCSR */ |
| 1785 | 1503 | ||
| 1786 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | 1504 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ |
| 1787 | #define nTXPKTRDY_T 0x0 | ||
| 1788 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | 1505 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ |
| 1789 | #define nFIFO_NOT_EMPTY_T 0x0 | ||
| 1790 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | 1506 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ |
| 1791 | #define nUNDERRUN_T 0x0 | ||
| 1792 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | 1507 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ |
| 1793 | #define nFLUSHFIFO_T 0x0 | ||
| 1794 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | 1508 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ |
| 1795 | #define nSTALL_SEND_T 0x0 | ||
| 1796 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | 1509 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ |
| 1797 | #define nSTALL_SENT_T 0x0 | ||
| 1798 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | 1510 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ |
| 1799 | #define nCLEAR_DATATOGGLE_T 0x0 | ||
| 1800 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | 1511 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ |
| 1801 | #define nINCOMPTX_T 0x0 | ||
| 1802 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | 1512 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ |
| 1803 | #define nDMAREQMODE_T 0x0 | ||
| 1804 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | 1513 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ |
| 1805 | #define nFORCE_DATATOGGLE_T 0x0 | ||
| 1806 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | 1514 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ |
| 1807 | #define nDMAREQ_ENA_T 0x0 | ||
| 1808 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | 1515 | #define ISO_T 0x4000 /* enable Isochronous transfers */ |
| 1809 | #define nISO_T 0x0 | ||
| 1810 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | 1516 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ |
| 1811 | #define nAUTOSET_T 0x0 | ||
| 1812 | #define ERROR_TH 0x4 /* error condition host mode */ | 1517 | #define ERROR_TH 0x4 /* error condition host mode */ |
| 1813 | #define nERROR_TH 0x0 | ||
| 1814 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | 1518 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ |
| 1815 | #define nSTALL_RECEIVED_TH 0x0 | ||
| 1816 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | 1519 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ |
| 1817 | #define nNAK_TIMEOUT_TH 0x0 | ||
| 1818 | 1520 | ||
| 1819 | /* Bit masks for USB_TXCOUNT */ | 1521 | /* Bit masks for USB_TXCOUNT */ |
| 1820 | 1522 | ||
| @@ -1823,45 +1525,25 @@ | |||
| 1823 | /* Bit masks for USB_RXCSR */ | 1525 | /* Bit masks for USB_RXCSR */ |
| 1824 | 1526 | ||
| 1825 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | 1527 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ |
| 1826 | #define nRXPKTRDY_R 0x0 | ||
| 1827 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | 1528 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ |
| 1828 | #define nFIFO_FULL_R 0x0 | ||
| 1829 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | 1529 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ |
| 1830 | #define nOVERRUN_R 0x0 | ||
| 1831 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | 1530 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ |
| 1832 | #define nDATAERROR_R 0x0 | ||
| 1833 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | 1531 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ |
| 1834 | #define nFLUSHFIFO_R 0x0 | ||
| 1835 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | 1532 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ |
| 1836 | #define nSTALL_SEND_R 0x0 | ||
| 1837 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | 1533 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ |
| 1838 | #define nSTALL_SENT_R 0x0 | ||
| 1839 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | 1534 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ |
| 1840 | #define nCLEAR_DATATOGGLE_R 0x0 | ||
| 1841 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | 1535 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ |
| 1842 | #define nINCOMPRX_R 0x0 | ||
| 1843 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | 1536 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ |
| 1844 | #define nDMAREQMODE_R 0x0 | ||
| 1845 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | 1537 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ |
| 1846 | #define nDISNYET_R 0x0 | ||
| 1847 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | 1538 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ |
| 1848 | #define nDMAREQ_ENA_R 0x0 | ||
| 1849 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | 1539 | #define ISO_R 0x4000 /* enable Isochronous transfers */ |
| 1850 | #define nISO_R 0x0 | ||
| 1851 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | 1540 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ |
| 1852 | #define nAUTOCLEAR_R 0x0 | ||
| 1853 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | 1541 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ |
| 1854 | #define nERROR_RH 0x0 | ||
| 1855 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | 1542 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ |
| 1856 | #define nREQPKT_RH 0x0 | ||
| 1857 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | 1543 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ |
| 1858 | #define nSTALL_RECEIVED_RH 0x0 | ||
| 1859 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | 1544 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ |
| 1860 | #define nINCOMPRX_RH 0x0 | ||
| 1861 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | 1545 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ |
| 1862 | #define nDMAREQMODE_RH 0x0 | ||
| 1863 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | 1546 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ |
| 1864 | #define nAUTOREQ_RH 0x0 | ||
| 1865 | 1547 | ||
| 1866 | /* Bit masks for USB_RXCOUNT */ | 1548 | /* Bit masks for USB_RXCOUNT */ |
| 1867 | 1549 | ||
| @@ -1888,35 +1570,22 @@ | |||
| 1888 | /* Bit masks for USB_DMA_INTERRUPT */ | 1570 | /* Bit masks for USB_DMA_INTERRUPT */ |
| 1889 | 1571 | ||
| 1890 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | 1572 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ |
| 1891 | #define nDMA0_INT 0x0 | ||
| 1892 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | 1573 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ |
| 1893 | #define nDMA1_INT 0x0 | ||
| 1894 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | 1574 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ |
| 1895 | #define nDMA2_INT 0x0 | ||
| 1896 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | 1575 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ |
| 1897 | #define nDMA3_INT 0x0 | ||
| 1898 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | 1576 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ |
| 1899 | #define nDMA4_INT 0x0 | ||
| 1900 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | 1577 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ |
| 1901 | #define nDMA5_INT 0x0 | ||
| 1902 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | 1578 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ |
| 1903 | #define nDMA6_INT 0x0 | ||
| 1904 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | 1579 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ |
| 1905 | #define nDMA7_INT 0x0 | ||
| 1906 | 1580 | ||
| 1907 | /* Bit masks for USB_DMAxCONTROL */ | 1581 | /* Bit masks for USB_DMAxCONTROL */ |
| 1908 | 1582 | ||
| 1909 | #define DMA_ENA 0x1 /* DMA enable */ | 1583 | #define DMA_ENA 0x1 /* DMA enable */ |
| 1910 | #define nDMA_ENA 0x0 | ||
| 1911 | #define DIRECTION 0x2 /* direction of DMA transfer */ | 1584 | #define DIRECTION 0x2 /* direction of DMA transfer */ |
| 1912 | #define nDIRECTION 0x0 | ||
| 1913 | #define MODE 0x4 /* DMA Bus error */ | 1585 | #define MODE 0x4 /* DMA Bus error */ |
| 1914 | #define nMODE 0x0 | ||
| 1915 | #define INT_ENA 0x8 /* Interrupt enable */ | 1586 | #define INT_ENA 0x8 /* Interrupt enable */ |
| 1916 | #define nINT_ENA 0x0 | ||
| 1917 | #define EPNUM 0xf0 /* EP number */ | 1587 | #define EPNUM 0xf0 /* EP number */ |
| 1918 | #define BUSERROR 0x100 /* DMA Bus error */ | 1588 | #define BUSERROR 0x100 /* DMA Bus error */ |
| 1919 | #define nBUSERROR 0x0 | ||
| 1920 | 1589 | ||
| 1921 | /* Bit masks for USB_DMAxADDRHIGH */ | 1590 | /* Bit masks for USB_DMAxADDRHIGH */ |
| 1922 | 1591 | ||
| @@ -1937,26 +1606,16 @@ | |||
| 1937 | /* Bit masks for HMDMAx_CONTROL */ | 1606 | /* Bit masks for HMDMAx_CONTROL */ |
| 1938 | 1607 | ||
| 1939 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ | 1608 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ |
| 1940 | #define nHMDMAEN 0x0 | ||
| 1941 | #define REP 0x2 /* Handshake MDMA Request Polarity */ | 1609 | #define REP 0x2 /* Handshake MDMA Request Polarity */ |
| 1942 | #define nREP 0x0 | ||
| 1943 | #define UTE 0x8 /* Urgency Threshold Enable */ | 1610 | #define UTE 0x8 /* Urgency Threshold Enable */ |
| 1944 | #define nUTE 0x0 | ||
| 1945 | #define OIE 0x10 /* Overflow Interrupt Enable */ | 1611 | #define OIE 0x10 /* Overflow Interrupt Enable */ |
| 1946 | #define nOIE 0x0 | ||
| 1947 | #define BDIE 0x20 /* Block Done Interrupt Enable */ | 1612 | #define BDIE 0x20 /* Block Done Interrupt Enable */ |
| 1948 | #define nBDIE 0x0 | ||
| 1949 | #define MBDI 0x40 /* Mask Block Done Interrupt */ | 1613 | #define MBDI 0x40 /* Mask Block Done Interrupt */ |
| 1950 | #define nMBDI 0x0 | ||
| 1951 | #define DRQ 0x300 /* Handshake MDMA Request Type */ | 1614 | #define DRQ 0x300 /* Handshake MDMA Request Type */ |
| 1952 | #define RBC 0x1000 /* Force Reload of BCOUNT */ | 1615 | #define RBC 0x1000 /* Force Reload of BCOUNT */ |
| 1953 | #define nRBC 0x0 | ||
| 1954 | #define PS 0x2000 /* Pin Status */ | 1616 | #define PS 0x2000 /* Pin Status */ |
| 1955 | #define nPS 0x0 | ||
| 1956 | #define OI 0x4000 /* Overflow Interrupt Generated */ | 1617 | #define OI 0x4000 /* Overflow Interrupt Generated */ |
| 1957 | #define nOI 0x0 | ||
| 1958 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | 1618 | #define BDI 0x8000 /* Block Done Interrupt Generated */ |
| 1959 | #define nBDI 0x0 | ||
| 1960 | 1619 | ||
| 1961 | /* ******************************************* */ | 1620 | /* ******************************************* */ |
| 1962 | /* MULTI BIT MACRO ENUMERATIONS */ | 1621 | /* MULTI BIT MACRO ENUMERATIONS */ |