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1/*
2 * File: include/asm-blackfin/mach-bf548/defBF542.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF542_H
32#define _DEF_BF542_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
43
44/* ATAPI Registers */
45
46#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
47#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
48#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
49#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
50#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
51#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
52#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
53#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
54#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
55#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
56#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
57#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
58#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
59#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
60#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
61#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
62#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
63#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
64#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
65#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
66#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
67#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
68#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
69#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
70#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
71
72/* SDH Registers */
73
74#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
75#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
76#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
77#define SDH_COMMAND 0xffc0390c /* SDH Command */
78#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
79#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
80#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
81#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
82#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
83#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
84#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
85#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
86#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
87#define SDH_STATUS 0xffc03934 /* SDH Status */
88#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
89#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
90#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
91#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
92#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
93#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
94#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
95#define SDH_CFG 0xffc039c8 /* SDH Configuration */
96#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
97#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
98#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
99#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
100#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
101#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
102#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
103#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
104#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
105
106/* USB Control Registers */
107
108#define USB_FADDR 0xffc03c00 /* Function address register */
109#define USB_POWER 0xffc03c04 /* Power management register */
110#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
111#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
112#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
113#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
114#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
115#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
116#define USB_FRAME 0xffc03c20 /* USB frame number */
117#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
118#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
119#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
120#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
121
122/* USB Packet Control Registers */
123
124#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
125#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
126#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
127#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
128#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
129#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
130#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
131#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
132#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
133#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
134#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
135#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
136#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
137
138/* USB Endpoint FIFO Registers */
139
140#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
141#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
142#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
143#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
144#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
145#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
146#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
147#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
148
149/* USB OTG Control Registers */
150
151#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
152#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
153#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
154
155/* USB Phy Control Registers */
156
157#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
158#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
159#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
160#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
161#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
162
163/* (APHY_CNTRL is for ADI usage only) */
164
165#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
166
167/* (APHY_CALIB is for ADI usage only) */
168
169#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
170#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
171
172/* (PHY_TEST is for ADI usage only) */
173
174#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
175#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
176#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
177
178/* USB Endpoint 0 Control Registers */
179
180#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
181#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
182#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
183#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
184#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
185#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
186#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
187#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
188#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
189
190/* USB Endpoint 1 Control Registers */
191
192#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
193#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
194#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
195#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
196#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
197#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
198#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
199#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
200#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
201#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
202
203/* USB Endpoint 2 Control Registers */
204
205#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
206#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
207#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
208#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
209#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
210#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
211#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
212#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
213#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
214#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
215
216/* USB Endpoint 3 Control Registers */
217
218#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
219#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
220#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
221#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
222#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
223#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
224#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
225#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
226#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
227#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
228
229/* USB Endpoint 4 Control Registers */
230
231#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
232#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
233#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
234#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
235#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
236#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
237#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
238#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
239#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
240#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
241
242/* USB Endpoint 5 Control Registers */
243
244#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
245#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
246#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
247#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
248#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
249#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
250#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
251#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
252#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
253#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
254
255/* USB Endpoint 6 Control Registers */
256
257#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
258#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
259#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
260#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
261#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
262#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
263#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
264#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
265#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
266#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
267
268/* USB Endpoint 7 Control Registers */
269
270#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
271#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
272#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
273#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
274#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
275#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
276#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
277#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
278#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
279#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
280#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
281#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
282
283/* USB Channel 0 Config Registers */
284
285#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
286#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
287#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
288#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
289#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
290
291/* USB Channel 1 Config Registers */
292
293#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
294#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
295#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
296#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
297#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
298
299/* USB Channel 2 Config Registers */
300
301#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
302#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
303#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
304#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
305#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
306
307/* USB Channel 3 Config Registers */
308
309#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
310#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
311#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
312#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
313#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
314
315/* USB Channel 4 Config Registers */
316
317#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
318#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
319#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
320#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
321#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
322
323/* USB Channel 5 Config Registers */
324
325#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
326#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
327#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
328#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
329#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
330
331/* USB Channel 6 Config Registers */
332
333#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
334#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
335#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
336#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
337#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
338
339/* USB Channel 7 Config Registers */
340
341#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
342#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
343#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
344#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
345#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
346
347/* Keypad Registers */
348
349#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
350#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
351#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
352#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
353#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
354#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
355
356
357/* ********************************************************** */
358/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
359/* and MULTI BIT READ MACROS */
360/* ********************************************************** */
361
362/* Bit masks for KPAD_CTL */
363
364#define KPAD_EN 0x1 /* Keypad Enable */
365#define nKPAD_EN 0x0
366#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
367#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
368#define KPAD_COLEN 0xe000 /* Column Enable Width */
369
370/* Bit masks for KPAD_PRESCALE */
371
372#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
373
374/* Bit masks for KPAD_MSEL */
375
376#define DBON_SCALE 0xff /* Debounce Scale Value */
377#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
378
379/* Bit masks for KPAD_ROWCOL */
380
381#define KPAD_ROW 0xff /* Rows Pressed */
382#define KPAD_COL 0xff00 /* Columns Pressed */
383
384/* Bit masks for KPAD_STAT */
385
386#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
387#define nKPAD_IRQ 0x0
388#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
389#define KPAD_PRESSED 0x8 /* Key press current status */
390#define nKPAD_PRESSED 0x0
391
392/* Bit masks for KPAD_SOFTEVAL */
393
394#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
395#define nKPAD_SOFTEVAL_E 0x0
396
397/* Bit masks for SDH_COMMAND */
398
399#define CMD_IDX 0x3f /* Command Index */
400#define CMD_RSP 0x40 /* Response */
401#define nCMD_RSP 0x0
402#define CMD_L_RSP 0x80 /* Long Response */
403#define nCMD_L_RSP 0x0
404#define CMD_INT_E 0x100 /* Command Interrupt */
405#define nCMD_INT_E 0x0
406#define CMD_PEND_E 0x200 /* Command Pending */
407#define nCMD_PEND_E 0x0
408#define CMD_E 0x400 /* Command Enable */
409#define nCMD_E 0x0
410
411/* Bit masks for SDH_PWR_CTL */
412
413#define PWR_ON 0x3 /* Power On */
414#if 0
415#define TBD 0x3c /* TBD */
416#endif
417#define SD_CMD_OD 0x40 /* Open Drain Output */
418#define nSD_CMD_OD 0x0
419#define ROD_CTL 0x80 /* Rod Control */
420#define nROD_CTL 0x0
421
422/* Bit masks for SDH_CLK_CTL */
423
424#define CLKDIV 0xff /* MC_CLK Divisor */
425#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
426#define nCLK_E 0x0
427#define PWR_SV_E 0x200 /* Power Save Enable */
428#define nPWR_SV_E 0x0
429#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
430#define nCLKDIV_BYPASS 0x0
431#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
432#define nWIDE_BUS 0x0
433
434/* Bit masks for SDH_RESP_CMD */
435
436#define RESP_CMD 0x3f /* Response Command */
437
438/* Bit masks for SDH_DATA_CTL */
439
440#define DTX_E 0x1 /* Data Transfer Enable */
441#define nDTX_E 0x0
442#define DTX_DIR 0x2 /* Data Transfer Direction */
443#define nDTX_DIR 0x0
444#define DTX_MODE 0x4 /* Data Transfer Mode */
445#define nDTX_MODE 0x0
446#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
447#define nDTX_DMA_E 0x0
448#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
449
450/* Bit masks for SDH_STATUS */
451
452#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
453#define nCMD_CRC_FAIL 0x0
454#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
455#define nDAT_CRC_FAIL 0x0
456#define CMD_TIMEOUT 0x4 /* CMD Time Out */
457#define nCMD_TIMEOUT 0x0
458#define DAT_TIMEOUT 0x8 /* Data Time Out */
459#define nDAT_TIMEOUT 0x0
460#define TX_UNDERRUN 0x10 /* Transmit Underrun */
461#define nTX_UNDERRUN 0x0
462#define RX_OVERRUN 0x20 /* Receive Overrun */
463#define nRX_OVERRUN 0x0
464#define CMD_RESP_END 0x40 /* CMD Response End */
465#define nCMD_RESP_END 0x0
466#define CMD_SENT 0x80 /* CMD Sent */
467#define nCMD_SENT 0x0
468#define DAT_END 0x100 /* Data End */
469#define nDAT_END 0x0
470#define START_BIT_ERR 0x200 /* Start Bit Error */
471#define nSTART_BIT_ERR 0x0
472#define DAT_BLK_END 0x400 /* Data Block End */
473#define nDAT_BLK_END 0x0
474#define CMD_ACT 0x800 /* CMD Active */
475#define nCMD_ACT 0x0
476#define TX_ACT 0x1000 /* Transmit Active */
477#define nTX_ACT 0x0
478#define RX_ACT 0x2000 /* Receive Active */
479#define nRX_ACT 0x0
480#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
481#define nTX_FIFO_STAT 0x0
482#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
483#define nRX_FIFO_STAT 0x0
484#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
485#define nTX_FIFO_FULL 0x0
486#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
487#define nRX_FIFO_FULL 0x0
488#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
489#define nTX_FIFO_ZERO 0x0
490#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
491#define nRX_DAT_ZERO 0x0
492#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
493#define nTX_DAT_RDY 0x0
494#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
495#define nRX_FIFO_RDY 0x0
496
497/* Bit masks for SDH_STATUS_CLR */
498
499#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
500#define nCMD_CRC_FAIL_STAT 0x0
501#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
502#define nDAT_CRC_FAIL_STAT 0x0
503#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
504#define nCMD_TIMEOUT_STAT 0x0
505#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
506#define nDAT_TIMEOUT_STAT 0x0
507#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
508#define nTX_UNDERRUN_STAT 0x0
509#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
510#define nRX_OVERRUN_STAT 0x0
511#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
512#define nCMD_RESP_END_STAT 0x0
513#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
514#define nCMD_SENT_STAT 0x0
515#define DAT_END_STAT 0x100 /* Data End Status */
516#define nDAT_END_STAT 0x0
517#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
518#define nSTART_BIT_ERR_STAT 0x0
519#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
520#define nDAT_BLK_END_STAT 0x0
521
522/* Bit masks for SDH_MASK0 */
523
524#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
525#define nCMD_CRC_FAIL_MASK 0x0
526#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
527#define nDAT_CRC_FAIL_MASK 0x0
528#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
529#define nCMD_TIMEOUT_MASK 0x0
530#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
531#define nDAT_TIMEOUT_MASK 0x0
532#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
533#define nTX_UNDERRUN_MASK 0x0
534#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
535#define nRX_OVERRUN_MASK 0x0
536#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
537#define nCMD_RESP_END_MASK 0x0
538#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
539#define nCMD_SENT_MASK 0x0
540#define DAT_END_MASK 0x100 /* Data End Mask */
541#define nDAT_END_MASK 0x0
542#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
543#define nSTART_BIT_ERR_MASK 0x0
544#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
545#define nDAT_BLK_END_MASK 0x0
546#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
547#define nCMD_ACT_MASK 0x0
548#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
549#define nTX_ACT_MASK 0x0
550#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
551#define nRX_ACT_MASK 0x0
552#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
553#define nTX_FIFO_STAT_MASK 0x0
554#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
555#define nRX_FIFO_STAT_MASK 0x0
556#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
557#define nTX_FIFO_FULL_MASK 0x0
558#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
559#define nRX_FIFO_FULL_MASK 0x0
560#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
561#define nTX_FIFO_ZERO_MASK 0x0
562#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
563#define nRX_DAT_ZERO_MASK 0x0
564#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
565#define nTX_DAT_RDY_MASK 0x0
566#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
567#define nRX_FIFO_RDY_MASK 0x0
568
569/* Bit masks for SDH_FIFO_CNT */
570
571#define FIFO_COUNT 0x7fff /* FIFO Count */
572
573/* Bit masks for SDH_E_STATUS */
574
575#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
576#define nSDIO_INT_DET 0x0
577#define SD_CARD_DET 0x10 /* SD Card Detect */
578#define nSD_CARD_DET 0x0
579
580/* Bit masks for SDH_E_MASK */
581
582#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
583#define nSDIO_MSK 0x0
584#define SCD_MSK 0x40 /* Mask Card Detect */
585#define nSCD_MSK 0x0
586
587/* Bit masks for SDH_CFG */
588
589#define CLKS_EN 0x1 /* Clocks Enable */
590#define nCLKS_EN 0x0
591#define SD4E 0x4 /* SDIO 4-Bit Enable */
592#define nSD4E 0x0
593#define MWE 0x8 /* Moving Window Enable */
594#define nMWE 0x0
595#define SD_RST 0x10 /* SDMMC Reset */
596#define nSD_RST 0x0
597#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
598#define nPUP_SDDAT 0x0
599#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
600#define nPUP_SDDAT3 0x0
601#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
602#define nPD_SDDAT3 0x0
603
604/* Bit masks for SDH_RD_WAIT_EN */
605
606#define RWR 0x1 /* Read Wait Request */
607#define nRWR 0x0
608
609/* Bit masks for ATAPI_CONTROL */
610
611#define PIO_START 0x1 /* Start PIO/Reg Op */
612#define nPIO_START 0x0
613#define MULTI_START 0x2 /* Start Multi-DMA Op */
614#define nMULTI_START 0x0
615#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
616#define nULTRA_START 0x0
617#define XFER_DIR 0x8 /* Transfer Direction */
618#define nXFER_DIR 0x0
619#define IORDY_EN 0x10 /* IORDY Enable */
620#define nIORDY_EN 0x0
621#define FIFO_FLUSH 0x20 /* Flush FIFOs */
622#define nFIFO_FLUSH 0x0
623#define SOFT_RST 0x40 /* Soft Reset */
624#define nSOFT_RST 0x0
625#define DEV_RST 0x80 /* Device Reset */
626#define nDEV_RST 0x0
627#define TFRCNT_RST 0x100 /* Trans Count Reset */
628#define nTFRCNT_RST 0x0
629#define END_ON_TERM 0x200 /* End/Terminate Select */
630#define nEND_ON_TERM 0x0
631#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
632#define nPIO_USE_DMA 0x0
633#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
634
635/* Bit masks for ATAPI_STATUS */
636
637#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
638#define nPIO_XFER_ON 0x0
639#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
640#define nMULTI_XFER_ON 0x0
641#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
642#define nULTRA_XFER_ON 0x0
643#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
644
645/* Bit masks for ATAPI_DEV_ADDR */
646
647#define DEV_ADDR 0x1f /* Device Address */
648
649/* Bit masks for ATAPI_INT_MASK */
650
651#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
652#define nATAPI_DEV_INT_MASK 0x0
653#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
654#define nPIO_DONE_MASK 0x0
655#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
656#define nMULTI_DONE_MASK 0x0
657#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
658#define nUDMAIN_DONE_MASK 0x0
659#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
660#define nUDMAOUT_DONE_MASK 0x0
661#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
662#define nHOST_TERM_XFER_MASK 0x0
663#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
664#define nMULTI_TERM_MASK 0x0
665#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
666#define nUDMAIN_TERM_MASK 0x0
667#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
668#define nUDMAOUT_TERM_MASK 0x0
669
670/* Bit masks for ATAPI_INT_STATUS */
671
672#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
673#define nATAPI_DEV_INT 0x0
674#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
675#define nPIO_DONE_INT 0x0
676#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
677#define nMULTI_DONE_INT 0x0
678#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
679#define nUDMAIN_DONE_INT 0x0
680#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
681#define nUDMAOUT_DONE_INT 0x0
682#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
683#define nHOST_TERM_XFER_INT 0x0
684#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
685#define nMULTI_TERM_INT 0x0
686#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
687#define nUDMAIN_TERM_INT 0x0
688#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
689#define nUDMAOUT_TERM_INT 0x0
690
691/* Bit masks for ATAPI_LINE_STATUS */
692
693#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
694#define nATAPI_INTR 0x0
695#define ATAPI_DASP 0x2 /* Device dasp to host line status */
696#define nATAPI_DASP 0x0
697#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
698#define nATAPI_CS0N 0x0
699#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
700#define nATAPI_CS1N 0x0
701#define ATAPI_ADDR 0x70 /* ATAPI address line status */
702#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
703#define nATAPI_DMAREQ 0x0
704#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
705#define nATAPI_DMAACKN 0x0
706#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
707#define nATAPI_DIOWN 0x0
708#define ATAPI_DIORN 0x400 /* ATAPI read line status */
709#define nATAPI_DIORN 0x0
710#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
711#define nATAPI_IORDY 0x0
712
713/* Bit masks for ATAPI_SM_STATE */
714
715#define PIO_CSTATE 0xf /* PIO mode state machine current state */
716#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
717#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
718#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
719
720/* Bit masks for ATAPI_TERMINATE */
721
722#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
723#define nATAPI_HOST_TERM 0x0
724
725/* Bit masks for ATAPI_REG_TIM_0 */
726
727#define T2_REG 0xff /* End of cycle time for register access transfers */
728#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
729
730/* Bit masks for ATAPI_PIO_TIM_0 */
731
732#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
733#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
734#define T4_REG 0xf000 /* DIOW data hold */
735
736/* Bit masks for ATAPI_PIO_TIM_1 */
737
738#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
739
740/* Bit masks for ATAPI_MULTI_TIM_0 */
741
742#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
743#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
744
745/* Bit masks for ATAPI_MULTI_TIM_1 */
746
747#define TKW 0xff /* Selects DIOW negated pulsewidth */
748#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
749
750/* Bit masks for ATAPI_MULTI_TIM_2 */
751
752#define TH 0xff /* Selects DIOW data hold */
753#define TEOC 0xff00 /* Selects end of cycle for DMA */
754
755/* Bit masks for ATAPI_ULTRA_TIM_0 */
756
757#define TACK 0xff /* Selects setup and hold times for TACK */
758#define TENV 0xff00 /* Selects envelope time */
759
760/* Bit masks for ATAPI_ULTRA_TIM_1 */
761
762#define TDVS 0xff /* Selects data valid setup time */
763#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
764
765/* Bit masks for ATAPI_ULTRA_TIM_2 */
766
767#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
768#define TMLI 0xff00 /* Selects interlock time */
769
770/* Bit masks for ATAPI_ULTRA_TIM_3 */
771
772#define TZAH 0xff /* Selects minimum delay required for output */
773#define READY_PAUSE 0xff00 /* Selects ready to pause */
774
775/* Bit masks for USB_FADDR */
776
777#define FUNCTION_ADDRESS 0x7f /* Function address */
778
779/* Bit masks for USB_POWER */
780
781#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
782#define nENABLE_SUSPENDM 0x0
783#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
784#define nSUSPEND_MODE 0x0
785#define RESUME_MODE 0x4 /* DMA Mode */
786#define nRESUME_MODE 0x0
787#define RESET 0x8 /* Reset indicator */
788#define nRESET 0x0
789#define HS_MODE 0x10 /* High Speed mode indicator */
790#define nHS_MODE 0x0
791#define HS_ENABLE 0x20 /* high Speed Enable */
792#define nHS_ENABLE 0x0
793#define SOFT_CONN 0x40 /* Soft connect */
794#define nSOFT_CONN 0x0
795#define ISO_UPDATE 0x80 /* Isochronous update */
796#define nISO_UPDATE 0x0
797
798/* Bit masks for USB_INTRTX */
799
800#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
801#define nEP0_TX 0x0
802#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
803#define nEP1_TX 0x0
804#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
805#define nEP2_TX 0x0
806#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
807#define nEP3_TX 0x0
808#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
809#define nEP4_TX 0x0
810#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
811#define nEP5_TX 0x0
812#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
813#define nEP6_TX 0x0
814#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
815#define nEP7_TX 0x0
816
817/* Bit masks for USB_INTRRX */
818
819#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
820#define nEP1_RX 0x0
821#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
822#define nEP2_RX 0x0
823#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
824#define nEP3_RX 0x0
825#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
826#define nEP4_RX 0x0
827#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
828#define nEP5_RX 0x0
829#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
830#define nEP6_RX 0x0
831#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
832#define nEP7_RX 0x0
833
834/* Bit masks for USB_INTRTXE */
835
836#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
837#define nEP0_TX_E 0x0
838#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
839#define nEP1_TX_E 0x0
840#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
841#define nEP2_TX_E 0x0
842#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
843#define nEP3_TX_E 0x0
844#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
845#define nEP4_TX_E 0x0
846#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
847#define nEP5_TX_E 0x0
848#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
849#define nEP6_TX_E 0x0
850#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
851#define nEP7_TX_E 0x0
852
853/* Bit masks for USB_INTRRXE */
854
855#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
856#define nEP1_RX_E 0x0
857#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
858#define nEP2_RX_E 0x0
859#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
860#define nEP3_RX_E 0x0
861#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
862#define nEP4_RX_E 0x0
863#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
864#define nEP5_RX_E 0x0
865#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
866#define nEP6_RX_E 0x0
867#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
868#define nEP7_RX_E 0x0
869
870/* Bit masks for USB_INTRUSB */
871
872#define SUSPEND_B 0x1 /* Suspend indicator */
873#define nSUSPEND_B 0x0
874#define RESUME_B 0x2 /* Resume indicator */
875#define nRESUME_B 0x0
876#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
877#define nRESET_OR_BABLE_B 0x0
878#define SOF_B 0x8 /* Start of frame */
879#define nSOF_B 0x0
880#define CONN_B 0x10 /* Connection indicator */
881#define nCONN_B 0x0
882#define DISCON_B 0x20 /* Disconnect indicator */
883#define nDISCON_B 0x0
884#define SESSION_REQ_B 0x40 /* Session Request */
885#define nSESSION_REQ_B 0x0
886#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
887#define nVBUS_ERROR_B 0x0
888
889/* Bit masks for USB_INTRUSBE */
890
891#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
892#define nSUSPEND_BE 0x0
893#define RESUME_BE 0x2 /* Resume indicator int enable */
894#define nRESUME_BE 0x0
895#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
896#define nRESET_OR_BABLE_BE 0x0
897#define SOF_BE 0x8 /* Start of frame int enable */
898#define nSOF_BE 0x0
899#define CONN_BE 0x10 /* Connection indicator int enable */
900#define nCONN_BE 0x0
901#define DISCON_BE 0x20 /* Disconnect indicator int enable */
902#define nDISCON_BE 0x0
903#define SESSION_REQ_BE 0x40 /* Session Request int enable */
904#define nSESSION_REQ_BE 0x0
905#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
906#define nVBUS_ERROR_BE 0x0
907
908/* Bit masks for USB_FRAME */
909
910#define FRAME_NUMBER 0x7ff /* Frame number */
911
912/* Bit masks for USB_INDEX */
913
914#define SELECTED_ENDPOINT 0xf /* selected endpoint */
915
916/* Bit masks for USB_GLOBAL_CTL */
917
918#define GLOBAL_ENA 0x1 /* enables USB module */
919#define nGLOBAL_ENA 0x0
920#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
921#define nEP1_TX_ENA 0x0
922#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
923#define nEP2_TX_ENA 0x0
924#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
925#define nEP3_TX_ENA 0x0
926#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
927#define nEP4_TX_ENA 0x0
928#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
929#define nEP5_TX_ENA 0x0
930#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
931#define nEP6_TX_ENA 0x0
932#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
933#define nEP7_TX_ENA 0x0
934#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
935#define nEP1_RX_ENA 0x0
936#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
937#define nEP2_RX_ENA 0x0
938#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
939#define nEP3_RX_ENA 0x0
940#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
941#define nEP4_RX_ENA 0x0
942#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
943#define nEP5_RX_ENA 0x0
944#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
945#define nEP6_RX_ENA 0x0
946#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
947#define nEP7_RX_ENA 0x0
948
949/* Bit masks for USB_OTG_DEV_CTL */
950
951#define SESSION 0x1 /* session indicator */
952#define nSESSION 0x0
953#define HOST_REQ 0x2 /* Host negotiation request */
954#define nHOST_REQ 0x0
955#define HOST_MODE 0x4 /* indicates USBDRC is a host */
956#define nHOST_MODE 0x0
957#define VBUS0 0x8 /* Vbus level indicator[0] */
958#define nVBUS0 0x0
959#define VBUS1 0x10 /* Vbus level indicator[1] */
960#define nVBUS1 0x0
961#define LSDEV 0x20 /* Low-speed indicator */
962#define nLSDEV 0x0
963#define FSDEV 0x40 /* Full or High-speed indicator */
964#define nFSDEV 0x0
965#define B_DEVICE 0x80 /* A' or 'B' device indicator */
966#define nB_DEVICE 0x0
967
968/* Bit masks for USB_OTG_VBUS_IRQ */
969
970#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
971#define nDRIVE_VBUS_ON 0x0
972#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
973#define nDRIVE_VBUS_OFF 0x0
974#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
975#define nCHRG_VBUS_START 0x0
976#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
977#define nCHRG_VBUS_END 0x0
978#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
979#define nDISCHRG_VBUS_START 0x0
980#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
981#define nDISCHRG_VBUS_END 0x0
982
983/* Bit masks for USB_OTG_VBUS_MASK */
984
985#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
986#define nDRIVE_VBUS_ON_ENA 0x0
987#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
988#define nDRIVE_VBUS_OFF_ENA 0x0
989#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
990#define nCHRG_VBUS_START_ENA 0x0
991#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
992#define nCHRG_VBUS_END_ENA 0x0
993#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
994#define nDISCHRG_VBUS_START_ENA 0x0
995#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
996#define nDISCHRG_VBUS_END_ENA 0x0
997
998/* Bit masks for USB_CSR0 */
999
1000#define RXPKTRDY 0x1 /* data packet receive indicator */
1001#define nRXPKTRDY 0x0
1002#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1003#define nTXPKTRDY 0x0
1004#define STALL_SENT 0x4 /* STALL handshake sent */
1005#define nSTALL_SENT 0x0
1006#define DATAEND 0x8 /* Data end indicator */
1007#define nDATAEND 0x0
1008#define SETUPEND 0x10 /* Setup end */
1009#define nSETUPEND 0x0
1010#define SENDSTALL 0x20 /* Send STALL handshake */
1011#define nSENDSTALL 0x0
1012#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1013#define nSERVICED_RXPKTRDY 0x0
1014#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1015#define nSERVICED_SETUPEND 0x0
1016#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1017#define nFLUSHFIFO 0x0
1018#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1019#define nSTALL_RECEIVED_H 0x0
1020#define SETUPPKT_H 0x8 /* send Setup token host mode */
1021#define nSETUPPKT_H 0x0
1022#define ERROR_H 0x10 /* timeout error indicator host mode */
1023#define nERROR_H 0x0
1024#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1025#define nREQPKT_H 0x0
1026#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1027#define nSTATUSPKT_H 0x0
1028#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1029#define nNAK_TIMEOUT_H 0x0
1030
1031/* Bit masks for USB_COUNT0 */
1032
1033#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1034
1035/* Bit masks for USB_NAKLIMIT0 */
1036
1037#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1038
1039/* Bit masks for USB_TX_MAX_PACKET */
1040
1041#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1042
1043/* Bit masks for USB_RX_MAX_PACKET */
1044
1045#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1046
1047/* Bit masks for USB_TXCSR */
1048
1049#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1050#define nTXPKTRDY_T 0x0
1051#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1052#define nFIFO_NOT_EMPTY_T 0x0
1053#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1054#define nUNDERRUN_T 0x0
1055#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1056#define nFLUSHFIFO_T 0x0
1057#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1058#define nSTALL_SEND_T 0x0
1059#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1060#define nSTALL_SENT_T 0x0
1061#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1062#define nCLEAR_DATATOGGLE_T 0x0
1063#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1064#define nINCOMPTX_T 0x0
1065#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1066#define nDMAREQMODE_T 0x0
1067#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1068#define nFORCE_DATATOGGLE_T 0x0
1069#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1070#define nDMAREQ_ENA_T 0x0
1071#define ISO_T 0x4000 /* enable Isochronous transfers */
1072#define nISO_T 0x0
1073#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1074#define nAUTOSET_T 0x0
1075#define ERROR_TH 0x4 /* error condition host mode */
1076#define nERROR_TH 0x0
1077#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1078#define nSTALL_RECEIVED_TH 0x0
1079#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1080#define nNAK_TIMEOUT_TH 0x0
1081
1082/* Bit masks for USB_TXCOUNT */
1083
1084#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1085
1086/* Bit masks for USB_RXCSR */
1087
1088#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1089#define nRXPKTRDY_R 0x0
1090#define FIFO_FULL_R 0x2 /* FIFO not empty */
1091#define nFIFO_FULL_R 0x0
1092#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1093#define nOVERRUN_R 0x0
1094#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1095#define nDATAERROR_R 0x0
1096#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1097#define nFLUSHFIFO_R 0x0
1098#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1099#define nSTALL_SEND_R 0x0
1100#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1101#define nSTALL_SENT_R 0x0
1102#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1103#define nCLEAR_DATATOGGLE_R 0x0
1104#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1105#define nINCOMPRX_R 0x0
1106#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1107#define nDMAREQMODE_R 0x0
1108#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1109#define nDISNYET_R 0x0
1110#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1111#define nDMAREQ_ENA_R 0x0
1112#define ISO_R 0x4000 /* enable Isochronous transfers */
1113#define nISO_R 0x0
1114#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1115#define nAUTOCLEAR_R 0x0
1116#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1117#define nERROR_RH 0x0
1118#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1119#define nREQPKT_RH 0x0
1120#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1121#define nSTALL_RECEIVED_RH 0x0
1122#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1123#define nINCOMPRX_RH 0x0
1124#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1125#define nDMAREQMODE_RH 0x0
1126#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1127#define nAUTOREQ_RH 0x0
1128
1129/* Bit masks for USB_RXCOUNT */
1130
1131#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1132
1133/* Bit masks for USB_TXTYPE */
1134
1135#define TARGET_EP_NO_T 0xf /* EP number */
1136#define PROTOCOL_T 0xc /* transfer type */
1137
1138/* Bit masks for USB_TXINTERVAL */
1139
1140#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1141
1142/* Bit masks for USB_RXTYPE */
1143
1144#define TARGET_EP_NO_R 0xf /* EP number */
1145#define PROTOCOL_R 0xc /* transfer type */
1146
1147/* Bit masks for USB_RXINTERVAL */
1148
1149#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1150
1151/* Bit masks for USB_DMA_INTERRUPT */
1152
1153#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1154#define nDMA0_INT 0x0
1155#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1156#define nDMA1_INT 0x0
1157#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1158#define nDMA2_INT 0x0
1159#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1160#define nDMA3_INT 0x0
1161#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1162#define nDMA4_INT 0x0
1163#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1164#define nDMA5_INT 0x0
1165#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1166#define nDMA6_INT 0x0
1167#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1168#define nDMA7_INT 0x0
1169
1170/* Bit masks for USB_DMAxCONTROL */
1171
1172#define DMA_ENA 0x1 /* DMA enable */
1173#define nDMA_ENA 0x0
1174#define DIRECTION 0x2 /* direction of DMA transfer */
1175#define nDIRECTION 0x0
1176#define MODE 0x4 /* DMA Bus error */
1177#define nMODE 0x0
1178#define INT_ENA 0x8 /* Interrupt enable */
1179#define nINT_ENA 0x0
1180#define EPNUM 0xf0 /* EP number */
1181#define BUSERROR 0x100 /* DMA Bus error */
1182#define nBUSERROR 0x0
1183
1184/* Bit masks for USB_DMAxADDRHIGH */
1185
1186#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1187
1188/* Bit masks for USB_DMAxADDRLOW */
1189
1190#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1191
1192/* Bit masks for USB_DMAxCOUNTHIGH */
1193
1194#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1195
1196/* Bit masks for USB_DMAxCOUNTLOW */
1197
1198#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1199
1200
1201/* ******************************************* */
1202/* MULTI BIT MACRO ENUMERATIONS */
1203/* ******************************************* */
1204
1205
1206#endif /* _DEF_BF542_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 17:08:57 -0500