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-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h418
1 files changed, 207 insertions, 211 deletions
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 19ddcd83c71f..57ac8cb9b1f6 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -43,7 +43,33 @@
43/* PLL Registers */ 43/* PLL Registers */
44 44
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
47#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
48#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
49#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 75#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -52,6 +78,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
52{ 78{
53 unsigned long flags, iwr0, iwr1, iwr2; 79 unsigned long flags, iwr0, iwr1, iwr2;
54 80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */ 85 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0); 86 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1); 87 iwr1 = bfin_read32(SIC_IWR1);
@@ -63,13 +93,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
63 93
64 bfin_write16(VR_CTL, val); 94 bfin_write16(VR_CTL, val);
65 SSYNC(); 95 SSYNC();
66
67 local_irq_save(flags);
68 asm("IDLE;"); 96 asm("IDLE;");
69 local_irq_restore(flags); 97
70 bfin_write32(SIC_IWR0, iwr0); 98 bfin_write32(SIC_IWR0, iwr0);
71 bfin_write32(SIC_IWR1, iwr1); 99 bfin_write32(SIC_IWR1, iwr1);
72 bfin_write32(SIC_IWR2, iwr2); 100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
73} 102}
74#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
75#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
@@ -211,39 +240,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
211 240
212/* Two Wire Interface Registers (TWI0) */ 241/* Two Wire Interface Registers (TWI0) */
213 242
214#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
215#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
216#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
217#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
218#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
219#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
220#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
221#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
222#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
223#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
224#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL)
225#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val)
226#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
227#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
228#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
229#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
230#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
231#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
232#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
233#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
234#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL)
235#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val)
236#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
237#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
238#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
239#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
240#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
241#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
242#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
243#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
246
247/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ 243/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
248 244
249/* SPORT1 Registers */ 245/* SPORT1 Registers */
@@ -323,7 +319,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
323#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) 319#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
324#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) 320#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
325#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) 321#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
326#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD) 322#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
327#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) 323#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
328#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) 324#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
329#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) 325#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
@@ -392,23 +388,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
392/* DMA Channel 0 Registers */ 388/* DMA Channel 0 Registers */
393 389
394#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) 390#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
395#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR) 391#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
396#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) 392#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
397#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR) 393#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
398#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 394#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
399#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) 395#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
400#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) 396#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
401#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) 397#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
402#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) 398#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
403#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY) 399#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
404#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) 400#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
405#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) 401#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
406#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) 402#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
407#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY) 403#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
408#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) 404#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
409#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR) 405#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
410#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) 406#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
411#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR) 407#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
412#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) 408#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
413#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) 409#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
414#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) 410#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
@@ -421,23 +417,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
421/* DMA Channel 1 Registers */ 417/* DMA Channel 1 Registers */
422 418
423#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) 419#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
424#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR) 420#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
425#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) 421#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
426#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR) 422#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
427#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) 423#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
428#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) 424#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
429#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) 425#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
430#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) 426#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
431#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) 427#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
432#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY) 428#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
433#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) 429#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
434#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) 430#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
435#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) 431#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
436#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY) 432#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
437#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) 433#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
438#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR) 434#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
439#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) 435#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
440#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR) 436#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
441#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) 437#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
442#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) 438#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
443#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) 439#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
@@ -450,23 +446,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
450/* DMA Channel 2 Registers */ 446/* DMA Channel 2 Registers */
451 447
452#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) 448#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
453#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR) 449#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
454#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) 450#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
455#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR) 451#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
456#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) 452#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
457#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) 453#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
458#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) 454#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
459#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) 455#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
460#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) 456#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
461#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY) 457#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
462#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) 458#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
463#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) 459#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
464#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) 460#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
465#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY) 461#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
466#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) 462#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
467#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR) 463#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
468#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) 464#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
469#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR) 465#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
470#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) 466#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
471#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) 467#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
472#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) 468#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
@@ -479,23 +475,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
479/* DMA Channel 3 Registers */ 475/* DMA Channel 3 Registers */
480 476
481#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) 477#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
482#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR) 478#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
483#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) 479#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
484#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR) 480#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
485#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) 481#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
486#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) 482#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
487#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) 483#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
488#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) 484#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
489#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) 485#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
490#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY) 486#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
491#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) 487#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
492#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) 488#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
493#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) 489#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
494#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY) 490#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
495#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) 491#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
496#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR) 492#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
497#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) 493#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
498#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR) 494#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
499#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) 495#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
500#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) 496#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
501#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) 497#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
@@ -508,23 +504,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
508/* DMA Channel 4 Registers */ 504/* DMA Channel 4 Registers */
509 505
510#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) 506#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
511#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR) 507#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
512#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) 508#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
513#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR) 509#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
514#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) 510#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
515#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) 511#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
516#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) 512#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
517#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) 513#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
518#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) 514#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
519#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY) 515#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
520#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) 516#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
521#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) 517#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
522#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) 518#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
523#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY) 519#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
524#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) 520#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
525#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR) 521#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
526#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) 522#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
527#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR) 523#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
528#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) 524#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
529#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) 525#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
530#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) 526#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
@@ -537,23 +533,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
537/* DMA Channel 5 Registers */ 533/* DMA Channel 5 Registers */
538 534
539#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) 535#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
540#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR) 536#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
541#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) 537#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
542#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR) 538#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
543#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) 539#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
544#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) 540#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
545#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) 541#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
546#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) 542#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
547#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) 543#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
548#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY) 544#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
549#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 545#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
550#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) 546#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
551#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) 547#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
552#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY) 548#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
553#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) 549#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
554#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR) 550#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
555#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) 551#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
556#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR) 552#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
557#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) 553#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
558#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) 554#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
559#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) 555#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
@@ -566,23 +562,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
566/* DMA Channel 6 Registers */ 562/* DMA Channel 6 Registers */
567 563
568#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) 564#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
569#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR) 565#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
570#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) 566#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
571#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR) 567#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
572#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) 568#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
573#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) 569#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
574#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) 570#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
575#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) 571#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
576#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) 572#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
577#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY) 573#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
578#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) 574#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
579#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) 575#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
580#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) 576#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
581#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY) 577#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
582#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) 578#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
583#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR) 579#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
584#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) 580#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
585#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR) 581#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
586#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) 582#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
587#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) 583#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
588#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) 584#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
@@ -595,23 +591,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
595/* DMA Channel 7 Registers */ 591/* DMA Channel 7 Registers */
596 592
597#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) 593#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
598#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR) 594#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
599#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) 595#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
600#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR) 596#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
601#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) 597#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
602#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) 598#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
603#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) 599#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
604#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) 600#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
605#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) 601#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
606#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY) 602#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
607#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) 603#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
608#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) 604#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
609#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) 605#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
610#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY) 606#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
611#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) 607#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
612#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR) 608#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
613#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) 609#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
614#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR) 610#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
615#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) 611#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
616#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) 612#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
617#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) 613#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
@@ -624,23 +620,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
624/* DMA Channel 8 Registers */ 620/* DMA Channel 8 Registers */
625 621
626#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) 622#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
627#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR) 623#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
628#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) 624#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
629#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR) 625#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
630#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) 626#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
631#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) 627#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
632#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) 628#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
633#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) 629#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
634#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) 630#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
635#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY) 631#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
636#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) 632#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
637#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) 633#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
638#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) 634#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
639#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY) 635#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
640#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) 636#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
641#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR) 637#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
642#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) 638#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
643#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR) 639#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
644#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) 640#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
645#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) 641#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
646#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) 642#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
@@ -653,23 +649,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
653/* DMA Channel 9 Registers */ 649/* DMA Channel 9 Registers */
654 650
655#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) 651#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
656#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR) 652#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
657#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) 653#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
658#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR) 654#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
659#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) 655#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
660#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) 656#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
661#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) 657#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
662#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) 658#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
663#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) 659#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
664#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY) 660#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
665#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) 661#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
666#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) 662#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
667#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) 663#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
668#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY) 664#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
669#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) 665#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
670#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR) 666#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
671#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) 667#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
672#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR) 668#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
673#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) 669#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
674#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) 670#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
675#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) 671#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
@@ -682,23 +678,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
682/* DMA Channel 10 Registers */ 678/* DMA Channel 10 Registers */
683 679
684#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) 680#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
685#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR) 681#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
686#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) 682#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
687#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR) 683#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
688#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) 684#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
689#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) 685#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
690#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) 686#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
691#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) 687#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
692#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) 688#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
693#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY) 689#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
694#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) 690#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
695#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) 691#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
696#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) 692#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
697#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY) 693#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
698#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) 694#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
699#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR) 695#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
700#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) 696#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
701#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR) 697#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
702#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) 698#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
703#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) 699#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
704#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) 700#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
@@ -711,23 +707,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
711/* DMA Channel 11 Registers */ 707/* DMA Channel 11 Registers */
712 708
713#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) 709#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
714#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR) 710#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
715#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) 711#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
716#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR) 712#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
717#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) 713#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
718#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) 714#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
719#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) 715#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
720#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) 716#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
721#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) 717#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
722#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY) 718#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
723#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) 719#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
724#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) 720#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
725#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) 721#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
726#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY) 722#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
727#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) 723#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
728#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR) 724#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
729#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) 725#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
730#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR) 726#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
731#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) 727#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
732#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) 728#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
733#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) 729#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
@@ -740,7 +736,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
740/* MDMA Stream 0 Registers */ 736/* MDMA Stream 0 Registers */
741 737
742#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) 738#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
743#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) 739#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
744#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) 740#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
745#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) 741#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
746#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) 742#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
@@ -803,11 +799,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
803#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) 799#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
804#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) 800#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
805#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) 801#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
806#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY) 802#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
807#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) 803#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
808#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) 804#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
809#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) 805#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
810#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) 806#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
811#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) 807#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
812#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) 808#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
813#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) 809#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
@@ -829,11 +825,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
829#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) 825#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
830#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) 826#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
831#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) 827#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
832#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY) 828#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
833#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) 829#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
834#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) 830#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
835#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) 831#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
836#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) 832#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
837#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) 833#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
838#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) 834#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
839#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) 835#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
@@ -1246,23 +1242,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1246/* DMA Channel 12 Registers */ 1242/* DMA Channel 12 Registers */
1247 1243
1248#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) 1244#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
1249#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR) 1245#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
1250#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) 1246#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
1251#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR) 1247#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
1252#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) 1248#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
1253#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) 1249#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
1254#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) 1250#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
1255#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) 1251#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
1256#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) 1252#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
1257#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY) 1253#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
1258#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) 1254#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
1259#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) 1255#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
1260#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) 1256#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
1261#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY) 1257#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
1262#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) 1258#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
1263#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR) 1259#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
1264#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) 1260#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
1265#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR) 1261#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
1266#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) 1262#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
1267#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) 1263#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
1268#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) 1264#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
@@ -1275,23 +1271,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1275/* DMA Channel 13 Registers */ 1271/* DMA Channel 13 Registers */
1276 1272
1277#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) 1273#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
1278#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR) 1274#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
1279#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) 1275#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
1280#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR) 1276#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
1281#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) 1277#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
1282#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) 1278#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
1283#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) 1279#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
1284#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) 1280#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
1285#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) 1281#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
1286#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY) 1282#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
1287#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) 1283#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
1288#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) 1284#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
1289#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) 1285#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
1290#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY) 1286#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
1291#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) 1287#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
1292#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR) 1288#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
1293#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) 1289#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
1294#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR) 1290#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
1295#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) 1291#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
1296#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) 1292#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
1297#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) 1293#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
@@ -1304,23 +1300,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1304/* DMA Channel 14 Registers */ 1300/* DMA Channel 14 Registers */
1305 1301
1306#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) 1302#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
1307#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR) 1303#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
1308#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) 1304#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
1309#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR) 1305#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
1310#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) 1306#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
1311#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) 1307#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
1312#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) 1308#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
1313#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) 1309#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
1314#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) 1310#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
1315#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY) 1311#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
1316#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) 1312#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
1317#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) 1313#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
1318#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) 1314#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
1319#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY) 1315#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
1320#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) 1316#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
1321#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR) 1317#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
1322#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) 1318#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
1323#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR) 1319#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
1324#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) 1320#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
1325#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) 1321#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
1326#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) 1322#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
@@ -1333,23 +1329,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1333/* DMA Channel 15 Registers */ 1329/* DMA Channel 15 Registers */
1334 1330
1335#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) 1331#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
1336#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR) 1332#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
1337#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) 1333#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
1338#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR) 1334#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
1339#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) 1335#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
1340#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) 1336#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
1341#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) 1337#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
1342#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) 1338#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
1343#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) 1339#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
1344#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY) 1340#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
1345#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) 1341#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
1346#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) 1342#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
1347#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) 1343#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
1348#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY) 1344#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
1349#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) 1345#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
1350#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR) 1346#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
1351#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) 1347#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
1352#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR) 1348#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
1353#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) 1349#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
1354#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) 1350#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1355#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) 1351#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
@@ -1362,23 +1358,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1362/* DMA Channel 16 Registers */ 1358/* DMA Channel 16 Registers */
1363 1359
1364#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) 1360#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
1365#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR) 1361#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
1366#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) 1362#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
1367#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR) 1363#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
1368#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) 1364#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
1369#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) 1365#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
1370#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) 1366#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
1371#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) 1367#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
1372#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) 1368#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
1373#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY) 1369#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
1374#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) 1370#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
1375#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) 1371#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
1376#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) 1372#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
1377#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY) 1373#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
1378#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) 1374#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
1379#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR) 1375#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
1380#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) 1376#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
1381#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR) 1377#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
1382#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) 1378#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
1383#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) 1379#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
1384#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) 1380#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
@@ -1391,23 +1387,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1391/* DMA Channel 17 Registers */ 1387/* DMA Channel 17 Registers */
1392 1388
1393#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) 1389#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
1394#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR) 1390#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
1395#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) 1391#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
1396#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR) 1392#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
1397#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) 1393#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
1398#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) 1394#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
1399#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) 1395#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
1400#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) 1396#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
1401#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) 1397#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
1402#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY) 1398#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
1403#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) 1399#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
1404#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) 1400#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
1405#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) 1401#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
1406#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY) 1402#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
1407#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) 1403#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
1408#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR) 1404#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
1409#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) 1405#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
1410#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR) 1406#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
1411#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) 1407#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
1412#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) 1408#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
1413#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) 1409#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
@@ -1420,23 +1416,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1420/* DMA Channel 18 Registers */ 1416/* DMA Channel 18 Registers */
1421 1417
1422#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) 1418#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
1423#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR) 1419#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
1424#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) 1420#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
1425#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR) 1421#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
1426#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) 1422#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
1427#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) 1423#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
1428#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) 1424#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
1429#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) 1425#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
1430#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) 1426#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
1431#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY) 1427#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
1432#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) 1428#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
1433#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) 1429#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
1434#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) 1430#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
1435#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY) 1431#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
1436#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) 1432#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1437#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR) 1433#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1438#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) 1434#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1439#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR) 1435#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1440#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) 1436#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
1441#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) 1437#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
1442#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) 1438#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
@@ -1449,23 +1445,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1449/* DMA Channel 19 Registers */ 1445/* DMA Channel 19 Registers */
1450 1446
1451#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) 1447#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1452#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR) 1448#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1453#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) 1449#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1454#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR) 1450#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1455#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) 1451#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
1456#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) 1452#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
1457#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) 1453#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
1458#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) 1454#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
1459#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) 1455#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
1460#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY) 1456#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
1461#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) 1457#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
1462#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) 1458#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
1463#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) 1459#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
1464#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY) 1460#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
1465#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) 1461#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1466#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR) 1462#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1467#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) 1463#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1468#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR) 1464#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1469#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) 1465#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
1470#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) 1466#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1471#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) 1467#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
@@ -1478,23 +1474,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1478/* DMA Channel 20 Registers */ 1474/* DMA Channel 20 Registers */
1479 1475
1480#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) 1476#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1481#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR) 1477#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1482#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) 1478#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1483#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR) 1479#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1484#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) 1480#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
1485#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) 1481#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
1486#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) 1482#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
1487#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) 1483#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
1488#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) 1484#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
1489#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY) 1485#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
1490#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) 1486#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
1491#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) 1487#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
1492#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) 1488#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
1493#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY) 1489#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
1494#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) 1490#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1495#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR) 1491#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1496#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) 1492#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1497#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR) 1493#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1498#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) 1494#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
1499#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) 1495#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
1500#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) 1496#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
@@ -1507,23 +1503,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1507/* DMA Channel 21 Registers */ 1503/* DMA Channel 21 Registers */
1508 1504
1509#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) 1505#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
1510#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR) 1506#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
1511#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) 1507#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
1512#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR) 1508#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
1513#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) 1509#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
1514#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) 1510#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
1515#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) 1511#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
1516#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) 1512#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
1517#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) 1513#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
1518#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY) 1514#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
1519#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) 1515#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
1520#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) 1516#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
1521#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) 1517#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
1522#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY) 1518#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
1523#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) 1519#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
1524#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR) 1520#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
1525#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) 1521#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
1526#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR) 1522#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
1527#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) 1523#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
1528#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) 1524#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
1529#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) 1525#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
@@ -1536,23 +1532,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1536/* DMA Channel 22 Registers */ 1532/* DMA Channel 22 Registers */
1537 1533
1538#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) 1534#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
1539#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR) 1535#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
1540#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) 1536#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
1541#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR) 1537#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
1542#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) 1538#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
1543#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) 1539#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
1544#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) 1540#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
1545#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) 1541#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
1546#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) 1542#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
1547#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY) 1543#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
1548#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) 1544#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
1549#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) 1545#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
1550#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) 1546#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
1551#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY) 1547#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
1552#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) 1548#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
1553#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR) 1549#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
1554#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) 1550#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
1555#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR) 1551#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
1556#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) 1552#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
1557#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) 1553#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
1558#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) 1554#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
@@ -1565,23 +1561,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1565/* DMA Channel 23 Registers */ 1561/* DMA Channel 23 Registers */
1566 1562
1567#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) 1563#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
1568#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR) 1564#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
1569#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) 1565#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
1570#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR) 1566#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
1571#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) 1567#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
1572#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) 1568#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
1573#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) 1569#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
1574#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) 1570#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
1575#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) 1571#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
1576#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY) 1572#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
1577#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) 1573#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
1578#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) 1574#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
1579#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) 1575#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
1580#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY) 1576#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
1581#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) 1577#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
1582#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR) 1578#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
1583#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) 1579#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
1584#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR) 1580#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
1585#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) 1581#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
1586#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) 1582#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1587#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) 1583#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
@@ -1594,23 +1590,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1594/* MDMA Stream 2 Registers */ 1590/* MDMA Stream 2 Registers */
1595 1591
1596#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) 1592#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
1597#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR) 1593#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
1598#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) 1594#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
1599#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR) 1595#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
1600#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) 1596#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
1601#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) 1597#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1602#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) 1598#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
1603#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) 1599#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1604#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) 1600#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
1605#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY) 1601#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1606#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) 1602#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
1607#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) 1603#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1608#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) 1604#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
1609#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY) 1605#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1610#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) 1606#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
1611#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR) 1607#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
1612#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) 1608#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
1613#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR) 1609#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
1614#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) 1610#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1615#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) 1611#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1616#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) 1612#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
@@ -1620,23 +1616,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1620#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) 1616#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1621#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) 1617#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1622#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) 1618#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
1623#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR) 1619#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
1624#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) 1620#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
1625#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR) 1621#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
1626#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) 1622#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
1627#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) 1623#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1628#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) 1624#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
1629#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) 1625#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1630#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) 1626#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
1631#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY) 1627#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1632#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) 1628#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
1633#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) 1629#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1634#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) 1630#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
1635#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY) 1631#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1636#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) 1632#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
1637#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR) 1633#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
1638#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) 1634#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
1639#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR) 1635#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
1640#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) 1636#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1641#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) 1637#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1642#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) 1638#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
@@ -1649,23 +1645,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1649/* MDMA Stream 3 Registers */ 1645/* MDMA Stream 3 Registers */
1650 1646
1651#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) 1647#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
1652#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR) 1648#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
1653#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) 1649#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
1654#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR) 1650#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
1655#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) 1651#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
1656#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) 1652#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1657#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) 1653#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
1658#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) 1654#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1659#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) 1655#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
1660#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY) 1656#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1661#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) 1657#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
1662#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) 1658#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1663#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) 1659#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
1664#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY) 1660#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1665#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) 1661#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
1666#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR) 1662#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
1667#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) 1663#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
1668#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR) 1664#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
1669#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) 1665#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1670#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) 1666#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1671#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) 1667#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
@@ -1675,23 +1671,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1675#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) 1671#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1676#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) 1672#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1677#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) 1673#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
1678#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR) 1674#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
1679#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) 1675#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
1680#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR) 1676#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
1681#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) 1677#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
1682#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) 1678#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1683#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) 1679#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
1684#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) 1680#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1685#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) 1681#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
1686#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY) 1682#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1687#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) 1683#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
1688#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) 1684#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1689#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) 1685#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
1690#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY) 1686#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1691#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) 1687#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
1692#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR) 1688#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
1693#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) 1689#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
1694#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR) 1690#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
1695#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) 1691#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1696#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) 1692#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1697#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) 1693#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 10:28:07 -0500