diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/cdefBF547.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/cdefBF547.h | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h index d0a200b08abd..ba716277c00d 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF547.h +++ b/include/asm-blackfin/mach-bf548/cdefBF547.h | |||
| @@ -185,39 +185,6 @@ | |||
| 185 | 185 | ||
| 186 | /* Two Wire Interface Registers (TWI1) */ | 186 | /* Two Wire Interface Registers (TWI1) */ |
| 187 | 187 | ||
| 188 | #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) | ||
| 189 | #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) | ||
| 190 | #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) | ||
| 191 | #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) | ||
| 192 | #define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) | ||
| 193 | #define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) | ||
| 194 | #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) | ||
| 195 | #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) | ||
| 196 | #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) | ||
| 197 | #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) | ||
| 198 | #define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) | ||
| 199 | #define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) | ||
| 200 | #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) | ||
| 201 | #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) | ||
| 202 | #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) | ||
| 203 | #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) | ||
| 204 | #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) | ||
| 205 | #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) | ||
| 206 | #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) | ||
| 207 | #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) | ||
| 208 | #define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) | ||
| 209 | #define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) | ||
| 210 | #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) | ||
| 211 | #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) | ||
| 212 | #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) | ||
| 213 | #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) | ||
| 214 | #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) | ||
| 215 | #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) | ||
| 216 | #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) | ||
| 217 | #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) | ||
| 218 | #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) | ||
| 219 | #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) | ||
| 220 | |||
| 221 | /* SPI2 Registers */ | 188 | /* SPI2 Registers */ |
| 222 | 189 | ||
| 223 | #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) | 190 | #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) |