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-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index b8509c16ecd4..d6ee74ac0460 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -166,6 +166,21 @@
166#define BFIN_UART_SCR UART1_SCR 166#define BFIN_UART_SCR UART1_SCR
167#define BFIN_UART_GCTL UART1_GCTL 167#define BFIN_UART_GCTL UART1_GCTL
168 168
169#define BFIN_UART_NR_PORTS 4
170
171#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
172#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
173#define OFFSET_GCTL 0x08 /* Global Control Register */
174#define OFFSET_LCR 0x0C /* Line Control Register */
175#define OFFSET_MCR 0x10 /* Modem Control Register */
176#define OFFSET_LSR 0x14 /* Line Status Register */
177#define OFFSET_MSR 0x18 /* Modem Status Register */
178#define OFFSET_SCR 0x1C /* SCR Scratch Register */
179#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
180#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
181#define OFFSET_THR 0x28 /* Transmit Holding register */
182#define OFFSET_RBR 0x2C /* Receive Buffer register */
183
169/* PLL_DIV Masks */ 184/* PLL_DIV Masks */
170#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 185#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
171#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ 186#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */