diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf537/mem_map.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf537/mem_map.h | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h index 2a808c1202bf..18759e38eaae 100644 --- a/include/asm-blackfin/mach-bf537/mem_map.h +++ b/include/asm-blackfin/mach-bf537/mem_map.h | |||
| @@ -52,10 +52,10 @@ | |||
| 52 | 52 | ||
| 53 | /* Memory Map for ADSP-BF537 processors */ | 53 | /* Memory Map for ADSP-BF537 processors */ |
| 54 | 54 | ||
| 55 | #ifdef CONFIG_BLKFIN_CACHE | 55 | #ifdef CONFIG_BFIN_ICACHE |
| 56 | #define BLKFIN_ICACHESIZE (16*1024) | 56 | #define BFIN_ICACHESIZE (16*1024) |
| 57 | #else | 57 | #else |
| 58 | #define BLKFIN_ICACHESIZE (0*1024) | 58 | #define BFIN_ICACHESIZE (0*1024) |
| 59 | #endif | 59 | #endif |
| 60 | 60 | ||
| 61 | 61 | ||
| @@ -66,29 +66,29 @@ | |||
| 66 | 66 | ||
| 67 | #define L1_CODE_LENGTH 0xC000 | 67 | #define L1_CODE_LENGTH 0xC000 |
| 68 | 68 | ||
| 69 | #ifdef CONFIG_BLKFIN_DCACHE | 69 | #ifdef CONFIG_BFIN_DCACHE |
| 70 | 70 | ||
| 71 | #ifdef CONFIG_BLKFIN_DCACHE_BANKA | 71 | #ifdef CONFIG_BFIN_DCACHE_BANKA |
| 72 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | 72 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) |
| 73 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 73 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 74 | #define L1_DATA_B_LENGTH 0x8000 | 74 | #define L1_DATA_B_LENGTH 0x8000 |
| 75 | #define BLKFIN_DCACHESIZE (16*1024) | 75 | #define BFIN_DCACHESIZE (16*1024) |
| 76 | #define BLKFIN_DSUPBANKS 1 | 76 | #define BFIN_DSUPBANKS 1 |
| 77 | #else | 77 | #else |
| 78 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | 78 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) |
| 79 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 79 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 80 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | 80 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) |
| 81 | #define BLKFIN_DCACHESIZE (32*1024) | 81 | #define BFIN_DCACHESIZE (32*1024) |
| 82 | #define BLKFIN_DSUPBANKS 2 | 82 | #define BFIN_DSUPBANKS 2 |
| 83 | #endif | 83 | #endif |
| 84 | 84 | ||
| 85 | #else | 85 | #else |
| 86 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | 86 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) |
| 87 | #define L1_DATA_A_LENGTH 0x8000 | 87 | #define L1_DATA_A_LENGTH 0x8000 |
| 88 | #define L1_DATA_B_LENGTH 0x8000 | 88 | #define L1_DATA_B_LENGTH 0x8000 |
| 89 | #define BLKFIN_DCACHESIZE (0*1024) | 89 | #define BFIN_DCACHESIZE (0*1024) |
| 90 | #define BLKFIN_DSUPBANKS 0 | 90 | #define BFIN_DSUPBANKS 0 |
| 91 | #endif /*CONFIG_BLKFIN_DCACHE*/ | 91 | #endif /*CONFIG_BFIN_DCACHE*/ |
| 92 | 92 | ||
| 93 | #endif /*CONFIG_BF537*/ | 93 | #endif /*CONFIG_BF537*/ |
| 94 | 94 | ||
| @@ -102,30 +102,30 @@ | |||
| 102 | #define L1_CODE_LENGTH 0xC000 | 102 | #define L1_CODE_LENGTH 0xC000 |
| 103 | 103 | ||
| 104 | 104 | ||
| 105 | #ifdef CONFIG_BLKFIN_DCACHE | 105 | #ifdef CONFIG_BFIN_DCACHE |
| 106 | 106 | ||
| 107 | #ifdef CONFIG_BLKFIN_DCACHE_BANKA | 107 | #ifdef CONFIG_BFIN_DCACHE_BANKA |
| 108 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | 108 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) |
| 109 | #define L1_DATA_A_LENGTH (0x4000 - 0x4000) | 109 | #define L1_DATA_A_LENGTH (0x4000 - 0x4000) |
| 110 | #define L1_DATA_B_LENGTH 0x4000 | 110 | #define L1_DATA_B_LENGTH 0x4000 |
| 111 | #define BLKFIN_DCACHESIZE (16*1024) | 111 | #define BFIN_DCACHESIZE (16*1024) |
| 112 | #define BLKFIN_DSUPBANKS 1 | 112 | #define BFIN_DSUPBANKS 1 |
| 113 | 113 | ||
| 114 | #else | 114 | #else |
| 115 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | 115 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) |
| 116 | #define L1_DATA_A_LENGTH (0x4000 - 0x4000) | 116 | #define L1_DATA_A_LENGTH (0x4000 - 0x4000) |
| 117 | #define L1_DATA_B_LENGTH (0x4000 - 0x4000) | 117 | #define L1_DATA_B_LENGTH (0x4000 - 0x4000) |
| 118 | #define BLKFIN_DCACHESIZE (32*1024) | 118 | #define BFIN_DCACHESIZE (32*1024) |
| 119 | #define BLKFIN_DSUPBANKS 2 | 119 | #define BFIN_DSUPBANKS 2 |
| 120 | #endif | 120 | #endif |
| 121 | 121 | ||
| 122 | #else | 122 | #else |
| 123 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | 123 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) |
| 124 | #define L1_DATA_A_LENGTH 0x4000 | 124 | #define L1_DATA_A_LENGTH 0x4000 |
| 125 | #define L1_DATA_B_LENGTH 0x4000 | 125 | #define L1_DATA_B_LENGTH 0x4000 |
| 126 | #define BLKFIN_DCACHESIZE (0*1024) | 126 | #define BFIN_DCACHESIZE (0*1024) |
| 127 | #define BLKFIN_DSUPBANKS 0 | 127 | #define BFIN_DSUPBANKS 0 |
| 128 | #endif /*CONFIG_BLKFIN_DCACHE*/ | 128 | #endif /*CONFIG_BFIN_DCACHE*/ |
| 129 | 129 | ||
| 130 | #endif | 130 | #endif |
| 131 | 131 | ||
| @@ -138,30 +138,30 @@ | |||
| 138 | 138 | ||
| 139 | #define L1_CODE_LENGTH 0xC000 | 139 | #define L1_CODE_LENGTH 0xC000 |
| 140 | 140 | ||
| 141 | #ifdef CONFIG_BLKFIN_DCACHE | 141 | #ifdef CONFIG_BFIN_DCACHE |
| 142 | 142 | ||
| 143 | #ifdef CONFIG_BLKFIN_DCACHE_BANKA | 143 | #ifdef CONFIG_BFIN_DCACHE_BANKA |
| 144 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | 144 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) |
| 145 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 145 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 146 | #define L1_DATA_B_LENGTH 0x8000 | 146 | #define L1_DATA_B_LENGTH 0x8000 |
| 147 | #define BLKFIN_DCACHESIZE (16*1024) | 147 | #define BFIN_DCACHESIZE (16*1024) |
| 148 | #define BLKFIN_DSUPBANKS 1 | 148 | #define BFIN_DSUPBANKS 1 |
| 149 | 149 | ||
| 150 | #else | 150 | #else |
| 151 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | 151 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) |
| 152 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 152 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 153 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | 153 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) |
| 154 | #define BLKFIN_DCACHESIZE (32*1024) | 154 | #define BFIN_DCACHESIZE (32*1024) |
| 155 | #define BLKFIN_DSUPBANKS 2 | 155 | #define BFIN_DSUPBANKS 2 |
| 156 | #endif | 156 | #endif |
| 157 | 157 | ||
| 158 | #else | 158 | #else |
| 159 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | 159 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) |
| 160 | #define L1_DATA_A_LENGTH 0x8000 | 160 | #define L1_DATA_A_LENGTH 0x8000 |
| 161 | #define L1_DATA_B_LENGTH 0x8000 | 161 | #define L1_DATA_B_LENGTH 0x8000 |
| 162 | #define BLKFIN_DCACHESIZE (0*1024) | 162 | #define BFIN_DCACHESIZE (0*1024) |
| 163 | #define BLKFIN_DSUPBANKS 0 | 163 | #define BFIN_DSUPBANKS 0 |
| 164 | #endif /*CONFIG_BLKFIN_DCACHE*/ | 164 | #endif /*CONFIG_BFIN_DCACHE*/ |
| 165 | 165 | ||
| 166 | #endif | 166 | #endif |
| 167 | 167 | ||