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-rw-r--r--include/asm-blackfin/mach-bf537/irq.h219
1 files changed, 219 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
new file mode 100644
index 000000000000..8af2a832ef6b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -0,0 +1,219 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/irq.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF537_IRQ_H_
33#define _BF537_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39 Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define SYS_IRQS 41
55#define NR_PERI_INTS 32
56
57/* The ABSTRACT IRQ definitions */
58/** the first seven of the following are fixed, the rest you change if you need to **/
59#define IRQ_EMU 0 /*Emulation */
60#define IRQ_RST 1 /*reset */
61#define IRQ_NMI 2 /*Non Maskable */
62#define IRQ_EVX 3 /*Exception */
63#define IRQ_UNUSED 4 /*- unused interrupt*/
64#define IRQ_HWERR 5 /*Hardware Error */
65#define IRQ_CORETMR 6 /*Core timer */
66
67#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
68#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
69#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
70#define IRQ_RTC 10 /*RTC Interrupt */
71#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
72#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
73#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
74#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
75#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
76#define IRQ_TWI 16 /*TWI Interrupt */
77#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
78#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
79#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
80#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
81#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
82#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
83#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
84#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
85#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
86#define IRQ_TMR0 26 /*Timer 0 */
87#define IRQ_TMR1 27 /*Timer 1 */
88#define IRQ_TMR2 28 /*Timer 2 */
89#define IRQ_TMR3 29 /*Timer 3 */
90#define IRQ_TMR4 30 /*Timer 4 */
91#define IRQ_TMR5 31 /*Timer 5 */
92#define IRQ_TMR6 32 /*Timer 6 */
93#define IRQ_TMR7 33 /*Timer 7 */
94#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
95#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
96#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
97#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
98#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
99#define IRQ_WATCH 38 /*Watch Dog Timer */
100#define IRQ_SW_INT1 40 /*Software Int 1 */
101#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
102
103#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
104#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
105#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */
106#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
107#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
108#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
109#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
110#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
111
112#define IRQ_PF0 50
113#define IRQ_PF1 51
114#define IRQ_PF2 52
115#define IRQ_PF3 53
116#define IRQ_PF4 54
117#define IRQ_PF5 55
118#define IRQ_PF6 56
119#define IRQ_PF7 57
120#define IRQ_PF8 58
121#define IRQ_PF9 59
122#define IRQ_PF10 60
123#define IRQ_PF11 61
124#define IRQ_PF12 62
125#define IRQ_PF13 63
126#define IRQ_PF14 64
127#define IRQ_PF15 65
128
129#define IRQ_PG0 66
130#define IRQ_PG1 67
131#define IRQ_PG2 68
132#define IRQ_PG3 69
133#define IRQ_PG4 70
134#define IRQ_PG5 71
135#define IRQ_PG6 72
136#define IRQ_PG7 73
137#define IRQ_PG8 74
138#define IRQ_PG9 75
139#define IRQ_PG10 76
140#define IRQ_PG11 77
141#define IRQ_PG12 78
142#define IRQ_PG13 79
143#define IRQ_PG14 80
144#define IRQ_PG15 81
145
146#define IRQ_PH0 82
147#define IRQ_PH1 83
148#define IRQ_PH2 84
149#define IRQ_PH3 85
150#define IRQ_PH4 86
151#define IRQ_PH5 87
152#define IRQ_PH6 88
153#define IRQ_PH7 89
154#define IRQ_PH8 90
155#define IRQ_PH9 91
156#define IRQ_PH10 92
157#define IRQ_PH11 93
158#define IRQ_PH12 94
159#define IRQ_PH13 95
160#define IRQ_PH14 96
161#define IRQ_PH15 97
162
163#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
164#define NR_IRQS (IRQ_PH15+1)
165#else
166#define NR_IRQS (IRQ_UART1_ERROR+1)
167#endif
168
169#define IVG7 7
170#define IVG8 8
171#define IVG9 9
172#define IVG10 10
173#define IVG11 11
174#define IVG12 12
175#define IVG13 13
176#define IVG14 14
177#define IVG15 15
178
179/* IAR0 BIT FIELDS*/
180#define IRQ_PLL_WAKEUP_POS 0
181#define IRQ_DMA_ERROR_POS 4
182#define IRQ_ERROR_POS 8
183#define IRQ_RTC_POS 12
184#define IRQ_PPI_POS 16
185#define IRQ_SPORT0_RX_POS 20
186#define IRQ_SPORT0_TX_POS 24
187#define IRQ_SPORT1_RX_POS 28
188
189/* IAR1 BIT FIELDS*/
190#define IRQ_SPORT1_TX_POS 0
191#define IRQ_TWI_POS 4
192#define IRQ_SPI_POS 8
193#define IRQ_UART0_RX_POS 12
194#define IRQ_UART0_TX_POS 16
195#define IRQ_UART1_RX_POS 20
196#define IRQ_UART1_TX_POS 24
197#define IRQ_CAN_RX_POS 28
198
199/* IAR2 BIT FIELDS*/
200#define IRQ_CAN_TX_POS 0
201#define IRQ_MAC_RX_POS 4
202#define IRQ_MAC_TX_POS 8
203#define IRQ_TMR0_POS 12
204#define IRQ_TMR1_POS 16
205#define IRQ_TMR2_POS 20
206#define IRQ_TMR3_POS 24
207#define IRQ_TMR4_POS 28
208
209/* IAR3 BIT FIELDS*/
210#define IRQ_TMR5_POS 0
211#define IRQ_TMR6_POS 4
212#define IRQ_TMR7_POS 8
213#define IRQ_PROG_INTA_POS 12
214#define IRQ_PORTG_INTB_POS 16
215#define IRQ_MEM_DMA0_POS 20
216#define IRQ_MEM_DMA1_POS 24
217#define IRQ_WATCH_POS 28
218
219#endif /* _BF537_IRQ_H_ */