diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf537/defBF537.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf537/defBF537.h | 404 |
1 files changed, 404 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h new file mode 100644 index 000000000000..26f9c02eb73c --- /dev/null +++ b/include/asm-blackfin/mach-bf537/defBF537.h | |||
| @@ -0,0 +1,404 @@ | |||
| 1 | /* | ||
| 2 | * file: include/asm-blackfin/mach-bf537/defbf537.h | ||
| 3 | * based on: | ||
| 4 | * author: | ||
| 5 | * | ||
| 6 | * created: | ||
| 7 | * description: | ||
| 8 | * system mmr register map | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _DEF_BF537_H | ||
| 33 | #define _DEF_BF537_H | ||
| 34 | |||
| 35 | /*include all Core registers and bit definitions*/ | ||
| 36 | #include "defBF537.h" | ||
| 37 | |||
| 38 | /*include core specific register pointer definitions*/ | ||
| 39 | #include <asm/mach-common/cdef_LPBlackfin.h> | ||
| 40 | |||
| 41 | /************************************************************************************ | ||
| 42 | ** Define EMAC Section Unique to BF536/BF537 | ||
| 43 | *************************************************************************************/ | ||
| 44 | |||
| 45 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
| 46 | #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ | ||
| 47 | #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ | ||
| 48 | #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ | ||
| 49 | #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ | ||
| 50 | #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ | ||
| 51 | #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ | ||
| 52 | #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ | ||
| 53 | #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ | ||
| 54 | #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ | ||
| 55 | #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ | ||
| 56 | #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ | ||
| 57 | #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ | ||
| 58 | #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ | ||
| 59 | #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ | ||
| 60 | #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ | ||
| 61 | #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ | ||
| 62 | #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ | ||
| 63 | #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ | ||
| 64 | #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ | ||
| 65 | |||
| 66 | #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ | ||
| 67 | #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ | ||
| 68 | #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ | ||
| 69 | #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ | ||
| 70 | #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ | ||
| 71 | #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ | ||
| 72 | #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ | ||
| 73 | #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ | ||
| 74 | |||
| 75 | #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ | ||
| 76 | #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ | ||
| 77 | #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ | ||
| 78 | #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ | ||
| 79 | #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ | ||
| 80 | |||
| 81 | #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ | ||
| 82 | #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ | ||
| 83 | #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ | ||
| 84 | #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ | ||
| 85 | #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ | ||
| 86 | #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ | ||
| 87 | #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ | ||
| 88 | #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ | ||
| 89 | #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ | ||
| 90 | #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ | ||
| 91 | #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ | ||
| 92 | #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ | ||
| 93 | #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ | ||
| 94 | #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ | ||
| 95 | #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ | ||
| 96 | #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ | ||
| 97 | #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ | ||
| 98 | #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
| 99 | #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ | ||
| 100 | #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ | ||
| 101 | #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 102 | #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 103 | #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 104 | #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
| 105 | |||
| 106 | #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ | ||
| 107 | #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ | ||
| 108 | #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ | ||
| 109 | #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ | ||
| 110 | #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ | ||
| 111 | #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ | ||
| 112 | #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ | ||
| 113 | #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ | ||
| 114 | #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ | ||
| 115 | #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ | ||
| 116 | #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ | ||
| 117 | #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ | ||
| 118 | #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ | ||
| 119 | #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ | ||
| 120 | #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ | ||
| 121 | #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ | ||
| 122 | #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ | ||
| 123 | #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ | ||
| 124 | #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 125 | #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 126 | #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 127 | #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
| 128 | #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ | ||
| 129 | |||
| 130 | /* Listing for IEEE-Supported Count Registers */ | ||
| 131 | #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ | ||
| 132 | #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ | ||
| 133 | #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ | ||
| 134 | #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ | ||
| 135 | #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ | ||
| 136 | #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ | ||
| 137 | #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ | ||
| 138 | #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ | ||
| 139 | #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ | ||
| 140 | #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ | ||
| 141 | #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ | ||
| 142 | #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ | ||
| 143 | #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ | ||
| 144 | #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ | ||
| 145 | #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ | ||
| 146 | #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ | ||
| 147 | #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ | ||
| 148 | #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
| 149 | #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ | ||
| 150 | #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */ | ||
| 151 | #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 152 | #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 153 | #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 154 | #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
| 155 | |||
| 156 | #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ | ||
| 157 | #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ | ||
| 158 | #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ | ||
| 159 | #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ | ||
| 160 | #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ | ||
| 161 | #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ | ||
| 162 | #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ | ||
| 163 | #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ | ||
| 164 | #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ | ||
| 165 | #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ | ||
| 166 | #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ | ||
| 167 | #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ | ||
| 168 | #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ | ||
| 169 | #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ | ||
| 170 | #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ | ||
| 171 | #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ | ||
| 172 | #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ | ||
| 173 | #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ | ||
| 174 | #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 175 | #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 176 | #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 177 | #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
| 178 | #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ | ||
| 179 | |||
| 180 | /*********************************************************************************** | ||
| 181 | ** System MMR Register Bits And Macros | ||
| 182 | ** | ||
| 183 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
| 184 | ** Use these macros carefully, as any that do left shifts for field | ||
| 185 | ** depositing will result in the lower order bits being destroyed. Any | ||
| 186 | ** macro that shifts left to properly position the bit-field should be | ||
| 187 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
| 188 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
| 189 | ** the macro is used. | ||
| 190 | *************************************************************************************/ | ||
| 191 | /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ | ||
| 192 | /* EMAC_OPMODE Masks */ | ||
| 193 | #define RE 0x00000001 /* Receiver Enable */ | ||
| 194 | #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ | ||
| 195 | #define HU 0x00000010 /* Hash Filter Unicast Address */ | ||
| 196 | #define HM 0x00000020 /* Hash Filter Multicast Address */ | ||
| 197 | #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ | ||
| 198 | #define PR 0x00000080 /* Promiscuous Mode Enable */ | ||
| 199 | #define IFE 0x00000100 /* Inverse Filtering Enable */ | ||
| 200 | #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ | ||
| 201 | #define PBF 0x00000400 /* Pass Bad Frames Enable */ | ||
| 202 | #define PSF 0x00000800 /* Pass Short Frames Enable */ | ||
| 203 | #define RAF 0x00001000 /* Receive-All Mode */ | ||
| 204 | #define TE 0x00010000 /* Transmitter Enable */ | ||
| 205 | #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ | ||
| 206 | #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ | ||
| 207 | #define DC 0x00080000 /* Deferral Check */ | ||
| 208 | #define BOLMT 0x00300000 /* Back-Off Limit */ | ||
| 209 | #define BOLMT_10 0x00000000 /* 10-bit range */ | ||
| 210 | #define BOLMT_8 0x00100000 /* 8-bit range */ | ||
| 211 | #define BOLMT_4 0x00200000 /* 4-bit range */ | ||
| 212 | #define BOLMT_1 0x00300000 /* 1-bit range */ | ||
| 213 | #define DRTY 0x00400000 /* Disable TX Retry On Collision */ | ||
| 214 | #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ | ||
| 215 | #define RMII 0x01000000 /* RMII/MII* Mode */ | ||
| 216 | #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ | ||
| 217 | #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ | ||
| 218 | #define LB 0x08000000 /* Internal Loopback Enable */ | ||
| 219 | #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ | ||
| 220 | |||
| 221 | /* EMAC_STAADD Masks */ | ||
| 222 | #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ | ||
| 223 | #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ | ||
| 224 | #define STADISPRE 0x00000004 /* Disable Preamble Generation */ | ||
| 225 | #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ | ||
| 226 | #define REGAD 0x000007C0 /* STA Register Address */ | ||
| 227 | #define PHYAD 0x0000F800 /* PHY Device Address */ | ||
| 228 | |||
| 229 | #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ | ||
| 230 | #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ | ||
| 231 | |||
| 232 | /* EMAC_STADAT Mask */ | ||
| 233 | #define STADATA 0x0000FFFF /* Station Management Data */ | ||
| 234 | |||
| 235 | /* EMAC_FLC Masks */ | ||
| 236 | #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ | ||
| 237 | #define FLCE 0x00000002 /* Flow Control Enable */ | ||
| 238 | #define PCF 0x00000004 /* Pass Control Frames */ | ||
| 239 | #define BKPRSEN 0x00000008 /* Enable Backpressure */ | ||
| 240 | #define FLCPAUSE 0xFFFF0000 /* Pause Time */ | ||
| 241 | |||
| 242 | #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ | ||
| 243 | |||
| 244 | /* EMAC_WKUP_CTL Masks */ | ||
| 245 | #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ | ||
| 246 | #define MPKE 0x00000002 /* Magic Packet Enable */ | ||
| 247 | #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ | ||
| 248 | #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ | ||
| 249 | #define MPKS 0x00000020 /* Magic Packet Received Status */ | ||
| 250 | #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ | ||
| 251 | |||
| 252 | /* EMAC_WKUP_FFCMD Masks */ | ||
| 253 | #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ | ||
| 254 | #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ | ||
| 255 | #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ | ||
| 256 | #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ | ||
| 257 | #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ | ||
| 258 | #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ | ||
| 259 | #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ | ||
| 260 | #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ | ||
| 261 | |||
| 262 | /* EMAC_WKUP_FFOFF Masks */ | ||
| 263 | #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ | ||
| 264 | #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ | ||
| 265 | #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ | ||
| 266 | #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ | ||
| 267 | |||
| 268 | #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | ||
| 269 | #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | ||
| 270 | #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | ||
| 271 | #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | ||
| 272 | /* Set ALL Offsets */ | ||
| 273 | #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) | ||
| 274 | |||
| 275 | /* EMAC_WKUP_FFCRC0 Masks */ | ||
| 276 | #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ | ||
| 277 | #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ | ||
| 278 | |||
| 279 | #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | ||
| 280 | #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | ||
| 281 | |||
| 282 | /* EMAC_WKUP_FFCRC1 Masks */ | ||
| 283 | #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ | ||
| 284 | #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ | ||
| 285 | |||
| 286 | #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | ||
| 287 | #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | ||
| 288 | |||
| 289 | /* EMAC_SYSCTL Masks */ | ||
| 290 | #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ | ||
| 291 | #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ | ||
| 292 | #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ | ||
| 293 | #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ | ||
| 294 | |||
| 295 | #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ | ||
| 296 | |||
| 297 | /* EMAC_SYSTAT Masks */ | ||
| 298 | #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ | ||
| 299 | #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ | ||
| 300 | #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ | ||
| 301 | #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ | ||
| 302 | #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ | ||
| 303 | #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ | ||
| 304 | #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ | ||
| 305 | #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ | ||
| 306 | |||
| 307 | /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ | ||
| 308 | #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ | ||
| 309 | #define RX_COMP 0x00001000 /* RX Frame Complete */ | ||
| 310 | #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ | ||
| 311 | #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ | ||
| 312 | #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ | ||
| 313 | #define RX_CRC 0x00010000 /* RX Frame CRC Error */ | ||
| 314 | #define RX_LEN 0x00020000 /* RX Frame Length Error */ | ||
| 315 | #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ | ||
| 316 | #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ | ||
| 317 | #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ | ||
| 318 | #define RX_PHY 0x00200000 /* RX Frame PHY Error */ | ||
| 319 | #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ | ||
| 320 | #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ | ||
| 321 | #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ | ||
| 322 | #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ | ||
| 323 | #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ | ||
| 324 | #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ | ||
| 325 | #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ | ||
| 326 | #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ | ||
| 327 | #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ | ||
| 328 | #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ | ||
| 329 | |||
| 330 | /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ | ||
| 331 | #define TX_COMP 0x00000001 /* TX Frame Complete */ | ||
| 332 | #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ | ||
| 333 | #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ | ||
| 334 | #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ | ||
| 335 | #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ | ||
| 336 | #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ | ||
| 337 | #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ | ||
| 338 | #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ | ||
| 339 | #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ | ||
| 340 | #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ | ||
| 341 | #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ | ||
| 342 | #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ | ||
| 343 | #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ | ||
| 344 | #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ | ||
| 345 | #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ | ||
| 346 | |||
| 347 | /* EMAC_MMC_CTL Masks */ | ||
| 348 | #define RSTC 0x00000001 /* Reset All Counters */ | ||
| 349 | #define CROLL 0x00000002 /* Counter Roll-Over Enable */ | ||
| 350 | #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ | ||
| 351 | #define MMCE 0x00000008 /* Enable MMC Counter Operation */ | ||
| 352 | |||
| 353 | /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ | ||
| 354 | #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ | ||
| 355 | #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ | ||
| 356 | #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ | ||
| 357 | #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ | ||
| 358 | #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ | ||
| 359 | #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ | ||
| 360 | #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ | ||
| 361 | #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ | ||
| 362 | #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ | ||
| 363 | #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ | ||
| 364 | #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ | ||
| 365 | #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ | ||
| 366 | #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ | ||
| 367 | #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ | ||
| 368 | #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ | ||
| 369 | #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ | ||
| 370 | #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ | ||
| 371 | #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ | ||
| 372 | #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ | ||
| 373 | #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ | ||
| 374 | #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ | ||
| 375 | #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ | ||
| 376 | #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ | ||
| 377 | #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ | ||
| 378 | |||
| 379 | /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ | ||
| 380 | #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ | ||
| 381 | #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ | ||
| 382 | #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ | ||
| 383 | #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ | ||
| 384 | #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ | ||
| 385 | #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ | ||
| 386 | #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ | ||
| 387 | #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ | ||
| 388 | #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ | ||
| 389 | #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ | ||
| 390 | #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ | ||
| 391 | #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ | ||
| 392 | #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ | ||
| 393 | #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ | ||
| 394 | #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ | ||
| 395 | #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ | ||
| 396 | #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ | ||
| 397 | #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ | ||
| 398 | #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ | ||
| 399 | #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ | ||
| 400 | #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ | ||
| 401 | #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ | ||
| 402 | #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ | ||
| 403 | |||
| 404 | #endif /* _DEF_BF537_H */ | ||