aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf537/defBF534.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-bf537/defBF534.h')
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index 1859f2fee5a7..d0d80d3152ba 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -86,6 +86,7 @@
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */ 86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87 87
88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
89#define SPI0_REGBASE 0xFFC00500
89#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 90#define SPI_CTL 0xFFC00500 /* SPI Control Register */
90#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 91#define SPI_FLG 0xFFC00504 /* SPI Flag register */
91#define SPI_STAT 0xFFC00508 /* SPI Status register */ 92#define SPI_STAT 0xFFC00508 /* SPI Status register */
@@ -456,6 +457,7 @@
456#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 457#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
457 458
458/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
459#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 461#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
460#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 462#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
461#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 463#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
@@ -1165,7 +1167,7 @@
1165#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ 1167#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1166#define PSSE 0x0010 /* Slave-Select Input Enable */ 1168#define PSSE 0x0010 /* Slave-Select Input Enable */
1167#define EMISO 0x0020 /* Enable MISO As Output */ 1169#define EMISO 0x0020 /* Enable MISO As Output */
1168#define SPI_SIZE 0x0100 /* Size of Words (16/8* Bits) */ 1170#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1169#define LSBF 0x0200 /* LSB First */ 1171#define LSBF 0x0200 /* LSB First */
1170#define CPHA 0x0400 /* Clock Phase */ 1172#define CPHA 0x0400 /* Clock Phase */
1171#define CPOL 0x0800 /* Clock Polarity */ 1173#define CPOL 0x0800 /* Clock Polarity */