diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf537/bf537.h')
-rw-r--r-- | include/asm-blackfin/mach-bf537/bf537.h | 67 |
1 files changed, 6 insertions, 61 deletions
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h index 603823f51ca0..cfe2a221112e 100644 --- a/include/asm-blackfin/mach-bf537/bf537.h +++ b/include/asm-blackfin/mach-bf537/bf537.h | |||
@@ -62,12 +62,12 @@ | |||
62 | /***************************/ | 62 | /***************************/ |
63 | 63 | ||
64 | 64 | ||
65 | #define BLKFIN_DSUBBANKS 4 | 65 | #define BFIN_DSUBBANKS 4 |
66 | #define BLKFIN_DWAYS 2 | 66 | #define BFIN_DWAYS 2 |
67 | #define BLKFIN_DLINES 64 | 67 | #define BFIN_DLINES 64 |
68 | #define BLKFIN_ISUBBANKS 4 | 68 | #define BFIN_ISUBBANKS 4 |
69 | #define BLKFIN_IWAYS 4 | 69 | #define BFIN_IWAYS 4 |
70 | #define BLKFIN_ILINES 32 | 70 | #define BFIN_ILINES 32 |
71 | 71 | ||
72 | #define WAY0_L 0x1 | 72 | #define WAY0_L 0x1 |
73 | #define WAY1_L 0x2 | 73 | #define WAY1_L 0x2 |
@@ -138,59 +138,4 @@ | |||
138 | #define CPUID 0x0 | 138 | #define CPUID 0x0 |
139 | #endif | 139 | #endif |
140 | 140 | ||
141 | #if (CONFIG_MEM_SIZE % 4) | ||
142 | #error "SDRAM mem size must be multible of 4MB" | ||
143 | #endif | ||
144 | |||
145 | #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) | ||
146 | #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) | ||
147 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) | ||
148 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) | ||
149 | |||
150 | /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ | ||
151 | |||
152 | #define ANOMALY_05000158_WORKAROUND 0x200 | ||
153 | #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ | ||
154 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ | ||
155 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | ||
156 | #else /*Write Through */ | ||
157 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ | ||
158 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) | ||
159 | #endif | ||
160 | |||
161 | |||
162 | #define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) | ||
163 | #define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) | ||
164 | #define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) | ||
165 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) | ||
166 | |||
167 | #define SIZE_1K 0x00000400 /* 1K */ | ||
168 | #define SIZE_4K 0x00001000 /* 4K */ | ||
169 | #define SIZE_1M 0x00100000 /* 1M */ | ||
170 | #define SIZE_4M 0x00400000 /* 4M */ | ||
171 | |||
172 | #define MAX_CPLBS (16 * 2) | ||
173 | |||
174 | /* | ||
175 | * Number of required data CPLB switchtable entries | ||
176 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
177 | * approx 16 for smaller 1MB page size CPLBs for allignment purposes | ||
178 | * 1 for L1 Data Memory | ||
179 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
180 | * 1 for ASYNC Memory | ||
181 | */ | ||
182 | |||
183 | |||
184 | #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) | ||
185 | |||
186 | /* | ||
187 | * Number of required instruction CPLB switchtable entries | ||
188 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
189 | * approx 12 for smaller 1MB page size CPLBs for allignment purposes | ||
190 | * 1 for L1 Instruction Memory | ||
191 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
192 | */ | ||
193 | |||
194 | #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) | ||
195 | |||
196 | #endif /* __MACH_BF537_H__ */ | 141 | #endif /* __MACH_BF537_H__ */ |