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-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h163
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diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
deleted file mode 100644
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--- a/include/asm-blackfin/mach-bf537/anomaly.h
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1/*
2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1 silicon - sorry */
17#if __SILICON_REVISION__ < 2
18# error will not work on BF537 silicon version 0.0 or 0.1
19#endif
20
21#if defined(__ADSPBF534__)
22# define ANOMALY_BF534 1
23#else
24# define ANOMALY_BF534 0
25#endif
26#if defined(__ADSPBF536__)
27# define ANOMALY_BF536 1
28#else
29# define ANOMALY_BF536 0
30#endif
31#if defined(__ADSPBF537__)
32# define ANOMALY_BF537 1
33#else
34# define ANOMALY_BF537 0
35#endif
36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
38#define ANOMALY_05000074 (1)
39/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
40#define ANOMALY_05000119 (1)
41/* Rx.H cannot be used to access 16-bit System MMR registers */
42#define ANOMALY_05000122 (1)
43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
45/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
46#define ANOMALY_05000167 (1)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */
50#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
51/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
52#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
53/* Spurious Hardware Error from an access in the shadow of a conditional branch */
54#define ANOMALY_05000245 (1)
55/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
56#define ANOMALY_05000247 (1)
57/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
58#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
59/* EMAC Tx DMA error after an early frame abort */
60#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
61/* Maximum external clock speed for Timers */
62#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
63/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
64#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
65/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
66#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
67/* EMAC MDIO input latched on wrong MDC edge */
68#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
69/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
70#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
71/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
72#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
73/* ICPLB_STATUS MMR register may be corrupted */
74#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
75/* DCPLB_FAULT_ADDR MMR register may be corrupted */
76#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
77/* Stores to data cache may be lost */
78#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
79/* Hardware loop corrupted when taking an ICPLB exception */
80#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
81/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
82#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
83/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
84#define ANOMALY_05000265 (1)
85/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
86#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
87/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
88#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
89/* Certain data cache write through modes fail for VDDint <=0.9V */
90#define ANOMALY_05000272 (1)
91/* Writes to Synchronous SDRAM memory may be lost */
92#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
93/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
94#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
95/* Disabling Peripherals with DMA running may cause DMA system instability */
96#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
97/* SPI Master boot mode does not work well with Atmel Data flash devices */
98#define ANOMALY_05000280 (1)
99/* False Hardware Error Exception when ISR context is not restored */
100#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
101/* Memory DMA corruption with 32-bit data and traffic control */
102#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
103/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
104#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
105/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
106#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
107/* SPORTs may receive bad data if FIFOs fill up */
108#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
109/* Memory to memory DMA source/destination descriptors must be in same memory space */
110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
117/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
118#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
119/* False hardware errors caused by fetches at the boundary of reserved memory */
120#define ANOMALY_05000310 (1)
121/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
122#define ANOMALY_05000312 (1)
123/* PPI is level sensitive on first transfer */
124#define ANOMALY_05000313 (1)
125/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
126#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
127/* EMAC RMII mode: collisions occur in Full Duplex mode */
128#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* New Feature: UART Remains Enabled after UART Boot */
136#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
137/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
138#define ANOMALY_05000355 (1)
139/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
140#define ANOMALY_05000357 (1)
141/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
142#define ANOMALY_05000359 (1)
143/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
144#define ANOMALY_05000366 (1)
145/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
146#define ANOMALY_05000371 (1)
147/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
148#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
149/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
150#define ANOMALY_05000403 (1)
151
152/* Anomalies that don't exist on this proc */
153#define ANOMALY_05000125 (0)
154#define ANOMALY_05000158 (0)
155#define ANOMALY_05000183 (0)
156#define ANOMALY_05000198 (0)
157#define ANOMALY_05000230 (0)
158#define ANOMALY_05000266 (0)
159#define ANOMALY_05000311 (0)
160#define ANOMALY_05000323 (0)
161#define ANOMALY_05000363 (0)
162
163#endif
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