aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf537/anomaly.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-bf537/anomaly.h')
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h216
1 files changed, 122 insertions, 94 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 5c5e33dec5f1..dc736c61980f 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,109 +7,137 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List
11 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List 11 * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
12 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List 12 * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
13 */ 13 */
14 14
15#ifndef _MACH_ANOMALY_H_ 15#ifndef _MACH_ANOMALY_H_
16#define _MACH_ANOMALY_H_ 16#define _MACH_ANOMALY_H_
17 17
18/* We do not support 0.1 silicon - sorry */ 18/* We do not support 0.1 silicon - sorry */
19#if (defined(CONFIG_BF_REV_0_1)) 19#if __SILICON_REVISION__ < 2
20#error Kernel will not work on BF537/6/4 Version 0.1 20# error Kernel will not work on BF537 silicon version 0.0 or 0.1
21#endif 21#endif
22 22
23#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) 23#if defined(__ADSPBF534__)
24#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 24# define ANOMALY_BF534 1
25 * slot1 and store of a P register in slot 2 is not 25#else
26 * supported */ 26# define ANOMALY_BF534 0
27#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
28 * Channel DMA stops */
29#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
30 * registers. */
31#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
32 * upper bits*/
33#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
34 * syncs */
35#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
36#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
37 * Changed */
38#endif 27#endif
39#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 28#if defined(__ADSPBF536__)
40 * SPORT external receive and transmit clocks. */ 29# define ANOMALY_BF536 1
41#define ANOMALY_05000272 /* Certain data cache write through modes fail for 30#else
42 * VDDint <=0.9V */ 31# define ANOMALY_BF536 0
43#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
44#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
45 * an edge is detected may clear interrupt */
46#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
47 * not restored */
48#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
49 * control */
50#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
51 * killed in a particular stage*/
52#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
53 * boundary of reserved memory */
54#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
55 * registers are interrupted */
56#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
57#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
58 * received properly */
59#endif 32#endif
60 33#if defined(__ADSPBF537__)
61#if defined(CONFIG_BF_REV_0_2) 34# define ANOMALY_BF537 1
62#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or 35#else
63 * IDLE around a Change of Control causes 36# define ANOMALY_BF537 0
64 * unpredictable results */
65#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
66 * (TDM) */
67#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
68#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
69#endif
70#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
71#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
72 * interrupt not functional */
73#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
74#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
75#endif 37#endif
76#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
77 * loops may cause the instruction fetch unit to
78 * malfunction */
79#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
80 * the ICPLB Data registers differ */
81#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
82#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
83#define ANOMALY_05000262 /* Stores to data cache may be lost */
84#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
85#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
86 * instruction will cause an infinite stall in the
87 * second to last instruction in a hardware loop */
88#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
89 * and non-zero DEB_TRAFFIC_PERIOD value */
90#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
91 * internal voltage regulator (VDDint) to decrease */
92#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
93 * an edge is detected may clear interrupt */
94#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
95 * DMA system instability */
96#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
97 * Atmel Dataflash devices */
98#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
99 * is not restored */
100#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
101 * control */
102#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
103 * Killed in a Particular Stage */
104#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
105 * (Not Available On Older Silicon) */
106#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
107#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
108 * On Next System MMR Access */
109#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
110 * mode */
111#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
112 * status No Carrier */
113#endif /* CONFIG_BF_REV_0_2 */
114 38
115#endif /* _MACH_ANOMALY_H_ */ 39/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
40#define ANOMALY_05000074 (1)
41/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
42#define ANOMALY_05000119 (1)
43/* Rx.H cannot be used to access 16-bit System MMR registers */
44#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
47/* PPI Data Lengths Between 8 and 16 do not zero out upper bits*/
48#define ANOMALY_05000166 (1) /* XXX: deleted from BF537 sheet ? */
49/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
50#define ANOMALY_05000180 (1)
51/* Instruction Cache Is Not Functional */
52#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
53/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
54#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
55/* Spurious Hardware Error from an access in the shadow of a conditional branch */
56#define ANOMALY_05000245 (1)
57/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
58#define ANOMALY_05000247 (1)
59/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
60#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
61/* EMAC Tx DMA error after an early frame abort */
62#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
63/* Maximum external clock speed for Timers */
64#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
65/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
66#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
67/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
68#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
69/* EMAC MDIO input latched on wrong MDC edge */
70#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
71/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
72#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
73/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
74#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
75/* ICPLB_STATUS MMR register may be corrupted */
76#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
77/* DCPLB_FAULT_ADDR MMR register may be corrupted */
78#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
79/* Stores to data cache may be lost */
80#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
81/* Hardware loop corrupted when taking an ICPLB exception */
82#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
83/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
84#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
85/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
86#define ANOMALY_05000265 (1)
87/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
88#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
89/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
90#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
91/* Certain data cache write through modes fail for VDDint <=0.9V */
92#define ANOMALY_05000272 (1)
93/* Writes to Synchronous SDRAM memory may be lost */
94#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
95/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
96#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
97/* Disabling Peripherals with DMA running may cause DMA system instability */
98#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
99/* SPI Master boot mode does not work well with Atmel Data flash devices */
100#define ANOMALY_05000280 (1)
101/* False Hardware Error Exception when ISR context is not restored */
102#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
103/* Memory DMA corruption with 32-bit data and traffic control */
104#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
105/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
106#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
107/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
108#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
109/* SPORTs may receive bad data if FIFOs fill up */
110#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
111/* Memory to memory DMA source/destination descriptors must be in same memory space */
112#define ANOMALY_05000301 (1)
113/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
114#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
115/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
116#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
117/* SCKELOW Bit Does Not Maintain State Through Hibernate */
118#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
119/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
120#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
121/* False hardware errors caused by fetches at the boundary of reserved memory */
122#define ANOMALY_05000310 (1)
123/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
124#define ANOMALY_05000312 (1)
125/* PPI is level sensitive on first transfer */
126#define ANOMALY_05000313 (1)
127/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
128#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode: collisions occur in Full Duplex mode */
130#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
132#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
133/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
134#define ANOMALY_05000322 (1)
135
136/* Anomalies that don't exist on this proc */
137#define ANOMALY_05000125 (0)
138#define ANOMALY_05000183 (0)
139#define ANOMALY_05000198 (0)
140#define ANOMALY_05000266 (0)
141#define ANOMALY_05000311 (0)
142
143#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 02:19:21 -0500