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-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h249
1 files changed, 127 insertions, 122 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 4453e614c3b1..2b66ecf489f7 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -1,139 +1,144 @@
1
2/* 1/*
3 * File: include/asm-blackfin/mach-bf537/anomaly.h 2 * File: include/asm-blackfin/mach-bf537/anomaly.h
4 * Based on: 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 * 4 *
22 * This program is distributed in the hope that it will be useful, 5 * Copyright (C) 2004-2007 Analog Devices Inc.
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 6 * Licensed under the GPL-2 or later.
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING.
29 * If not, write to the Free Software Foundation,
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 */ 7 */
32 8
33/* This file shoule be up to date with: 9/* This file shoule be up to date with:
34 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List
35 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List 11 * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
36 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List 12 * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
37 */ 13 */
38 14
39#ifndef _MACH_ANOMALY_H_ 15#ifndef _MACH_ANOMALY_H_
40#define _MACH_ANOMALY_H_ 16#define _MACH_ANOMALY_H_
41 17
42/* We do not support 0.1 silicon - sorry */ 18/* We do not support 0.1 silicon - sorry */
43#if (defined(CONFIG_BF_REV_0_1)) 19#if __SILICON_REVISION__ < 2
44#error Kernel will not work on BF537/6/4 Version 0.1 20# error Kernel will not work on BF537 silicon version 0.0 or 0.1
45#endif 21#endif
46 22
47#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) 23#if defined(__ADSPBF534__)
48#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 24# define ANOMALY_BF534 1
49 slot1 and store of a P register in slot 2 is not 25#else
50 supported */ 26# define ANOMALY_BF534 0
51#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
52 Channel DMA stops */
53#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
54 registers. */
55#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
56 upper bits*/
57#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
58 syncs */
59#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
60#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
61 Changed */
62#endif
63#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
64 SPORT external receive and transmit clocks. */
65#define ANOMALY_05000272 /* Certain data cache write through modes fail for
66 VDDint <=0.9V */
67#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
68#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
69 an edge is detected may clear interrupt */
70#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
71 not restored */
72#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
73 control */
74#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
75 killed in a particular stage*/
76#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
77 * boundary of reserved memory */
78#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
79 registers are interrupted */
80#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
81#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
82 * received properly */
83#endif 27#endif
84 28#if defined(__ADSPBF536__)
85#if defined(CONFIG_BF_REV_0_2) 29# define ANOMALY_BF536 1
86#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or 30#else
87 IDLE around a Change of Control causes 31# define ANOMALY_BF536 0
88 unpredictable results */
89#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
90 (TDM) */
91#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
92#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
93#endif 32#endif
94#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ 33#if defined(__ADSPBF537__)
95#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event 34# define ANOMALY_BF537 1
96 interrupt not functional */ 35#else
97#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) 36# define ANOMALY_BF537 0
98#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
99#endif 37#endif
100#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
101 loops may cause the instruction fetch unit to
102 malfunction */
103#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
104 the ICPLB Data registers differ */
105#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
106#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
107#define ANOMALY_05000262 /* Stores to data cache may be lost */
108#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
109#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
110 instruction will cause an infinite stall in the
111 second to last instruction in a hardware loop */
112#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
113 and non-zero DEB_TRAFFIC_PERIOD value */
114#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
115 internal voltage regulator (VDDint) to decrease */
116#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
117 an edge is detected may clear interrupt */
118#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
119 DMA system instability */
120#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
121 Atmel Dataflash devices */
122#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
123 * is not restored */
124#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
125 * control */
126#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
127 * Killed in a Particular Stage */
128#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
129 * (Not Available On Older Silicon) */
130#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
131#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
132 * On Next System MMR Access */
133#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
134 * mode */
135#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
136 * status No Carrier */
137#endif /* CONFIG_BF_REV_0_2 */
138 38
139#endif /* _MACH_ANOMALY_H_ */ 39/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
40#define ANOMALY_05000074 (1)
41/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
42#define ANOMALY_05000119 (1)
43/* Rx.H cannot be used to access 16-bit System MMR registers */
44#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */
50#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
51/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
52#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
53/* Spurious Hardware Error from an access in the shadow of a conditional branch */
54#define ANOMALY_05000245 (1)
55/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
56#define ANOMALY_05000247 (1)
57/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
58#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
59/* EMAC Tx DMA error after an early frame abort */
60#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
61/* Maximum external clock speed for Timers */
62#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
63/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
64#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
65/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
66#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
67/* EMAC MDIO input latched on wrong MDC edge */
68#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
69/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
70#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
71/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
72#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
73/* ICPLB_STATUS MMR register may be corrupted */
74#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
75/* DCPLB_FAULT_ADDR MMR register may be corrupted */
76#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
77/* Stores to data cache may be lost */
78#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
79/* Hardware loop corrupted when taking an ICPLB exception */
80#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
81/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
82#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
83/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
84#define ANOMALY_05000265 (1)
85/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
86#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
87/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
88#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
89/* Certain data cache write through modes fail for VDDint <=0.9V */
90#define ANOMALY_05000272 (1)
91/* Writes to Synchronous SDRAM memory may be lost */
92#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
93/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
94#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
95/* Disabling Peripherals with DMA running may cause DMA system instability */
96#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
97/* SPI Master boot mode does not work well with Atmel Data flash devices */
98#define ANOMALY_05000280 (1)
99/* False Hardware Error Exception when ISR context is not restored */
100#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
101/* Memory DMA corruption with 32-bit data and traffic control */
102#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
103/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
104#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
105/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
106#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
107/* SPORTs may receive bad data if FIFOs fill up */
108#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
109/* Memory to memory DMA source/destination descriptors must be in same memory space */
110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
117/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
118#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
119/* False hardware errors caused by fetches at the boundary of reserved memory */
120#define ANOMALY_05000310 (1)
121/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
122#define ANOMALY_05000312 (1)
123/* PPI is level sensitive on first transfer */
124#define ANOMALY_05000313 (1)
125/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
126#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
127/* EMAC RMII mode: collisions occur in Full Duplex mode */
128#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1)
133
134/* Anomalies that don't exist on this proc */
135#define ANOMALY_05000125 (0)
136#define ANOMALY_05000158 (0)
137#define ANOMALY_05000183 (0)
138#define ANOMALY_05000198 (0)
139#define ANOMALY_05000230 (0)
140#define ANOMALY_05000266 (0)
141#define ANOMALY_05000311 (0)
142#define ANOMALY_05000323 (0)
143
144#endif
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