diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf537/anomaly.h')
-rw-r--r-- | include/asm-blackfin/mach-bf537/anomaly.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index a6b08facb242..8460ab9c324f 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * File: include/asm-blackfin/mach-bf537/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf537/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
4 | * | 4 | * |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. | 5 | * Copyright (C) 2004-2008 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||
@@ -132,8 +132,8 @@ | |||
132 | #define ANOMALY_05000322 (1) | 132 | #define ANOMALY_05000322 (1) |
133 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ | 133 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
134 | #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) | 134 | #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) |
135 | /* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */ | 135 | /* New Feature: UART Remains Enabled after UART Boot */ |
136 | #define ANOMALY_05000350 (__SILICON_REVISION__ < 3) | 136 | #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) |
137 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | 137 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
138 | #define ANOMALY_05000355 (1) | 138 | #define ANOMALY_05000355 (1) |
139 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | 139 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
@@ -145,12 +145,10 @@ | |||
145 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | 145 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
146 | #define ANOMALY_05000371 (1) | 146 | #define ANOMALY_05000371 (1) |
147 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | 147 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ |
148 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 3) | 148 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) |
149 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 149 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
150 | #define ANOMALY_05000403 (1) | 150 | #define ANOMALY_05000403 (1) |
151 | 151 | ||
152 | |||
153 | |||
154 | /* Anomalies that don't exist on this proc */ | 152 | /* Anomalies that don't exist on this proc */ |
155 | #define ANOMALY_05000125 (0) | 153 | #define ANOMALY_05000125 (0) |
156 | #define ANOMALY_05000158 (0) | 154 | #define ANOMALY_05000158 (0) |