diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf537/anomaly.h')
-rw-r--r-- | include/asm-blackfin/mach-bf537/anomaly.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 2b66ecf489f7..746a794b3119 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h | |||
@@ -7,9 +7,7 @@ | |||
7 | */ | 7 | */ |
8 | 8 | ||
9 | /* This file shoule be up to date with: | 9 | /* This file shoule be up to date with: |
10 | * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List | 10 | * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List |
11 | * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List | ||
12 | * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List | ||
13 | */ | 11 | */ |
14 | 12 | ||
15 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
@@ -17,7 +15,7 @@ | |||
17 | 15 | ||
18 | /* We do not support 0.1 silicon - sorry */ | 16 | /* We do not support 0.1 silicon - sorry */ |
19 | #if __SILICON_REVISION__ < 2 | 17 | #if __SILICON_REVISION__ < 2 |
20 | # error Kernel will not work on BF537 silicon version 0.0 or 0.1 | 18 | # error will not work on BF537 silicon version 0.0 or 0.1 |
21 | #endif | 19 | #endif |
22 | 20 | ||
23 | #if defined(__ADSPBF534__) | 21 | #if defined(__ADSPBF534__) |
@@ -44,6 +42,8 @@ | |||
44 | #define ANOMALY_05000122 (1) | 42 | #define ANOMALY_05000122 (1) |
45 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ | 43 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ |
46 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) | 44 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) |
45 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ | ||
46 | #define ANOMALY_05000167 (1) | ||
47 | /* PPI_DELAY not functional in PPI modes with 0 frame syncs */ | 47 | /* PPI_DELAY not functional in PPI modes with 0 frame syncs */ |
48 | #define ANOMALY_05000180 (1) | 48 | #define ANOMALY_05000180 (1) |
49 | /* Instruction Cache Is Not Functional */ | 49 | /* Instruction Cache Is Not Functional */ |
@@ -130,6 +130,12 @@ | |||
130 | #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) | 130 | #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) |
131 | /* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ | 131 | /* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ |
132 | #define ANOMALY_05000322 (1) | 132 | #define ANOMALY_05000322 (1) |
133 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ | ||
134 | #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) | ||
135 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | ||
136 | #define ANOMALY_05000357 (1) | ||
137 | /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ | ||
138 | #define ANOMALY_05000359 (1) | ||
133 | 139 | ||
134 | /* Anomalies that don't exist on this proc */ | 140 | /* Anomalies that don't exist on this proc */ |
135 | #define ANOMALY_05000125 (0) | 141 | #define ANOMALY_05000125 (0) |