3 files changed, 13 insertions, 8 deletions

diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index fbe88dee3e2d..d016603b6615 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
 
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 17e1548cec08..0ab4dd7494cf 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -468,6 +468,8 @@
 #define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
 #define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
 #define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
+#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
+#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
 
 #define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
 #define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 832e6f6122da..5aa38e5da6b7 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -66,12 +66,13 @@ Core        Emulation               **
             DMA8/9 Interrupt        IVG13       28
             DMA10/11 Interrupt      IVG13       29
             Watchdog Timer          IVG13       30
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
+
+            Softirq                 IVG14       31
+            System Call    --
                  (lowest priority)  IVG15       32 *
  */
-#define SYS_IRQS                32
-#define NR_PERI_INTS    24
+#define SYS_IRQS        31
+#define NR_PERI_INTS    24
 
 /* The ABSTRACT IRQ definitions */
 /** the first seven of the following are fixed, the rest you change if you need to **/
@@ -96,7 +97,7 @@ Core        Emulation               **
 #define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
 #define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
 #define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
+#define         IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
 #define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
 #define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
 #define IRQ_TMR0                23      /*Timer 0 */
@@ -108,9 +109,6 @@ Core        Emulation               **
 #define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
 #define IRQ_WATCH               30      /*Watch Dog Timer */
 
-#define IRQ_SW_INT1             31      /*Software Int 1 */
-#define IRQ_SW_INT2             32      /*Software Int 2 (reserved for SYSCALL) */
-
 #define IRQ_PF0                 33
 #define IRQ_PF1                 34
 #define IRQ_PF2                 35