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-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h166
1 files changed, 0 insertions, 166 deletions
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
deleted file mode 100644
index bd30b6f3be00..000000000000
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_map.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MEM_MAP_533_H_
32#define _MEM_MAP_533_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x400
51
52/* Level 1 Memory */
53
54#ifdef CONFIG_BFIN_ICACHE
55#define BFIN_ICACHESIZE (16*1024)
56#else
57#define BFIN_ICACHESIZE (0*1024)
58#endif
59
60/* Memory Map for ADSP-BF533 processors */
61
62#ifdef CONFIG_BF533
63#define L1_CODE_START 0xFFA00000
64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000
66
67#ifdef CONFIG_BFIN_ICACHE
68#define L1_CODE_LENGTH (0x14000 - 0x4000)
69#else
70#define L1_CODE_LENGTH 0x14000
71#endif
72
73#ifdef CONFIG_BFIN_DCACHE
74
75#ifdef CONFIG_BFIN_DCACHE_BANKA
76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH 0x8000
79#define BFIN_DCACHESIZE (16*1024)
80#define BFIN_DSUPBANKS 1
81#else
82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
83#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
84#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
85#define BFIN_DCACHESIZE (32*1024)
86#define BFIN_DSUPBANKS 2
87#endif
88
89#else
90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
91#define L1_DATA_A_LENGTH 0x8000
92#define L1_DATA_B_LENGTH 0x8000
93#define BFIN_DCACHESIZE (0*1024)
94#define BFIN_DSUPBANKS 0
95#endif /*CONFIG_BFIN_DCACHE*/
96#endif
97
98/* Memory Map for ADSP-BF532 processors */
99
100#ifdef CONFIG_BF532
101#define L1_CODE_START 0xFFA08000
102#define L1_DATA_A_START 0xFF804000
103#define L1_DATA_B_START 0xFF904000
104
105#ifdef CONFIG_BFIN_ICACHE
106#define L1_CODE_LENGTH (0xC000 - 0x4000)
107#else
108#define L1_CODE_LENGTH 0xC000
109#endif
110
111#ifdef CONFIG_BFIN_DCACHE
112
113#ifdef CONFIG_BFIN_DCACHE_BANKA
114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
115#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
116#define L1_DATA_B_LENGTH 0x4000
117#define BFIN_DCACHESIZE (16*1024)
118#define BFIN_DSUPBANKS 1
119
120#else
121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
122#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
123#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
124#define BFIN_DCACHESIZE (32*1024)
125#define BFIN_DSUPBANKS 2
126#endif
127
128#else
129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
130#define L1_DATA_A_LENGTH 0x4000
131#define L1_DATA_B_LENGTH 0x4000
132#define BFIN_DCACHESIZE (0*1024)
133#define BFIN_DSUPBANKS 0
134#endif /*CONFIG_BFIN_DCACHE*/
135#endif
136
137/* Memory Map for ADSP-BF531 processors */
138
139#ifdef CONFIG_BF531
140#define L1_CODE_START 0xFFA08000
141#define L1_DATA_A_START 0xFF804000
142#define L1_DATA_B_START 0xFF904000
143#define L1_CODE_LENGTH 0x4000
144#define L1_DATA_B_LENGTH 0x0000
145
146
147#ifdef CONFIG_BFIN_DCACHE
148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
149#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
150#define BFIN_DCACHESIZE (16*1024)
151#define BFIN_DSUPBANKS 1
152#else
153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
154#define L1_DATA_A_LENGTH 0x4000
155#define BFIN_DCACHESIZE (0*1024)
156#define BFIN_DSUPBANKS 0
157#endif
158
159#endif
160
161/* Scratch Pad Memory */
162
163#define L1_SCRATCH_START 0xFFB00000
164#define L1_SCRATCH_LENGTH 0x1000
165
166#endif /* _MEM_MAP_533_H_ */
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