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-rw-r--r--include/asm-blackfin/mach-bf533/cdefBF532.h767
1 files changed, 0 insertions, 767 deletions
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
deleted file mode 100644
index 154655452d4c..000000000000
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ /dev/null
@@ -1,767 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/cdefBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF532_H
32#define _CDEF_BF532_H
33
34#include <asm/blackfin.h>
35
36/*include all Core registers and bit definitions*/
37#include "defBF532.h"
38
39/*include core specific register pointer definitions*/
40#include <asm/mach-common/cdef_LPBlackfin.h>
41
42#include <asm/system.h>
43
44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr = bfin_read32(SIC_IWR);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR, IWR_ENABLE(0));
59
60 bfin_write16(PLL_CTL, val);
61 SSYNC();
62 asm("IDLE;");
63
64 bfin_write32(SIC_IWR, iwr);
65 local_irq_restore(flags);
66}
67#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
68#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
69#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
70#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
71#define bfin_read_CHIPID() bfin_read32(CHIPID)
72#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
73#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
74#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
75/* Writing to VR_CTL initiates a PLL relock sequence. */
76static __inline__ void bfin_write_VR_CTL(unsigned int val)
77{
78 unsigned long flags, iwr;
79
80 if (val == bfin_read_VR_CTL())
81 return;
82
83 local_irq_save(flags);
84 /* Enable the PLL Wakeup bit in SIC IWR */
85 iwr = bfin_read32(SIC_IWR);
86 /* Only allow PPL Wakeup) */
87 bfin_write32(SIC_IWR, IWR_ENABLE(0));
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR, iwr);
94 local_irq_restore(flags);
95}
96
97/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
98#define bfin_read_SWRST() bfin_read16(SWRST)
99#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
100#define bfin_read_SYSCR() bfin_read16(SYSCR)
101#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
102#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
103#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
104#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
105#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
106#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
107#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
108#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
109#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
110#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
111#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
112#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
113#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
114#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
115#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
116
117/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
118#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
119#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
120#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
121#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
122#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
123#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
124
125/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
126#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
127#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
128#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
129#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
130#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
131#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
132#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
133#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
134#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
135#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
136#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
137#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
138#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
139#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
140
141/* DMA Traffic controls */
142#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
143#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
144#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
145#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
146
147/* Alternate deprecated register names (below) provided for backwards code compatibility */
148#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
149#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
150#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
151#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
152
153/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
154#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
155#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
156#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
157#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
158#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
159#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
160#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
161#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
162#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
163#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
164#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
165#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
166#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
167#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
168#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
169#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
170#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
171#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
172#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
173#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
174#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
175#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
176#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
177#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
178#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
179#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
180
181
182#if ANOMALY_05000311
183#define BFIN_WRITE_FIO_FLAG(name) \
184static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
185{\
186 unsigned long flags;\
187 local_irq_save(flags);\
188 bfin_write16(FIO_FLAG_ ## name,val);\
189 bfin_read_CHIPID();\
190 local_irq_restore(flags);\
191}
192BFIN_WRITE_FIO_FLAG(D)
193BFIN_WRITE_FIO_FLAG(C)
194BFIN_WRITE_FIO_FLAG(S)
195BFIN_WRITE_FIO_FLAG(T)
196
197#define BFIN_READ_FIO_FLAG(name) \
198static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
199{\
200 unsigned long flags;\
201 unsigned short ret;\
202 local_irq_save(flags);\
203 ret = bfin_read16(FIO_FLAG_ ## name);\
204 bfin_read_CHIPID();\
205 local_irq_restore(flags);\
206 return ret;\
207}
208BFIN_READ_FIO_FLAG(D)
209BFIN_READ_FIO_FLAG(C)
210BFIN_READ_FIO_FLAG(S)
211BFIN_READ_FIO_FLAG(T)
212
213#else
214#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val)
215#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val)
216#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val)
217#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val)
218#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
219#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
220#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
221#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
222#endif
223
224
225/* DMA Controller */
226#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
227#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
228#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
229#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
230#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
231#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
232#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
233#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
234#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
235#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
236#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
237#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
238#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
239#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
240#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
241#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
242#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
243#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
244#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
245#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
246#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
247#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
248#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
249#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
250#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
251#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
252
253#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
254#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
255#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
256#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
257#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
258#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
259#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
260#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
261#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
262#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
263#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
264#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
265#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
266#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
267#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
268#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
269#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
270#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
271#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
272#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
273#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
274#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
275#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
276#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
277#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
278#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
279
280#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
281#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
282#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
283#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
284#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
285#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
286#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
287#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
288#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
289#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
290#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
291#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
292#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
293#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
294#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
295#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
296#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
297#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
298#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
299#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
300#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
301#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
302#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
303#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
304#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
305#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
306
307#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
308#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
309#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
310#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
311#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
312#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
313#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
314#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
315#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
316#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
317#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
318#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
319#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
320#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
321#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
322#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
323#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
324#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
325#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
326#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
327#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
328#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
329#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
330#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
331#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
332#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
333
334#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
335#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
336#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
337#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
338#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
339#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
340#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
341#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
342#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
343#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
344#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
345#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
346#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
347#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
348#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
349#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
350#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
351#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
352#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
353#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
354#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
355#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
356#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
357#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
358#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
359#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
360
361#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
362#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
363#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
364#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
365#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
366#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
367#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
368#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
369#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
370#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
371#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
372#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
373#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
374#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
375#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
376#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
377#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
378#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
379#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
380#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
381#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
382#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
383#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
384#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
385#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
386#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
387
388#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
389#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
390#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
391#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
392#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
393#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
394#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
395#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
396#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
397#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
398#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
399#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
400#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
401#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
402#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
403#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
404#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
405#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
406#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
407#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
408#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
409#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
410#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
411#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
412#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
413#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
414
415#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
416#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
417#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
418#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
419#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
420#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
421#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
422#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
423#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
424#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
425#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
426#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
427#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
428#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
429#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
430#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
431#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
432#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
433#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
434#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
435#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
436#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
437#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
438#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
439#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
440#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
441
442#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
443#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
444#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
445#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
446#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
447#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
448#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
449#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
450#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
451#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
452#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
453#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
454#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
455#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
456#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
457#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
458#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
459#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
460#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
461#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
462#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
463#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
464#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
465#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
466#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
467#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
468
469#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
470#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
471#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
472#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
473#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
474#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
475#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
476#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
477#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
478#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
479#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
480#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
481#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
482#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
483#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
484#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
485#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
486#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
487#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
488#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
489#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
490#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
491#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
492#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
493#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
494#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
495
496#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
497#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
498#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
499#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
500#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
501#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
502#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
503#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
504#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
505#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
506#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
507#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
508#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
509#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
510#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
511#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
512#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
513#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
514#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
515#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
516#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
517#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
518#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
519#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
520#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
521#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
522
523#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
524#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
525#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
526#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
527#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
528#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
529#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
530#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
531#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
532#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
533#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
534#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
535#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
536#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
537#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
538#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
539#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
540#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
541#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
542#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
543#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
544#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
545#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
546#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
547#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
548#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
549
550/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
551#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
552#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
553#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
554#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
555#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
556#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
557
558/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
559#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
560#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
561#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
562#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
563#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
564#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
565#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
566#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
567
568/* UART Controller */
569#define bfin_read_UART_THR() bfin_read16(UART_THR)
570#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
571#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
572#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
573#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
574#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
575#define bfin_read_UART_IER() bfin_read16(UART_IER)
576#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
577#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
578#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
579#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
580#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
581#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
582#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
583#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
584#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
585#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
586#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
587/*
588#define UART_MSR
589*/
590#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
591#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
592#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
593#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
594
595/* SPI Controller */
596#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
597#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
598#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
599#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
600#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
601#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
602#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
603#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
604#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
605#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
606#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
607#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
608#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
609#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
610
611/* TIMER 0, 1, 2 Registers */
612#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
613#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
614#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
615#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
616#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
617#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
618#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
619#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
620
621#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
622#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
623#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
624#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
625#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
626#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
627#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
628#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
629
630#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
631#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
632#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
633#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
634#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
635#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
636#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
637#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
638
639#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
640#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
641#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
642#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
643#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
644#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
645
646/* SPORT0 Controller */
647#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
648#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
649#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
650#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
651#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
652#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
653#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
654#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
655#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
656#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
657#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
658#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
659#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
660#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
661#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
662#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
663#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
664#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
665#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
666#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
667#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
668#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
669#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
670#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
671#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
672#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
673#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
674#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
675#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
676#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
677#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
678#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
679#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
680#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
681#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
682#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
683#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
684#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
685#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
686#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
687#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
688#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
689#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
690#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
691#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
692#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
693#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
694#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
695#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
696#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
697#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
698#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
699
700/* SPORT1 Controller */
701#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
702#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
703#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
704#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
705#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
706#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
707#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
708#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
709#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
710#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
711#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
712#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
713#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
714#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
715#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
716#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
717#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
718#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
719#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
720#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
721#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
722#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
723#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
724#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
725#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
726#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
727#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
728#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
729#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
730#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
731#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
732#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
733#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
734#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
735#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
736#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
737#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
738#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
739#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
740#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
741#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
742#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
743#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
744#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
745#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
746#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
747#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
748#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
749#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
750#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
751#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
752#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
753
754/* Parallel Peripheral Interface (PPI) */
755#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
756#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
757#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
758#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
759#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
760#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
761#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
762#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
763#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
764#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
765#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
766
767#endif /* _CDEF_BF532_H */
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