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diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
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1/*
2 * file: include/asm-blackfin/mach-bf527/dma.h
3 * based on: include/asm-blackfin/mach-bf537/dma.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system DMA map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0 /* PPI receive/transmit or NFC */
38#define CH_NFC 0 /* PPI receive/transmit or NFC */
39#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
40#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
41#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
42#define CH_SPORT0_RX 3 /* SPORT0 receive */
43#define CH_SPORT0_TX 4 /* SPORT0 transmit */
44#define CH_SPORT1_RX 5 /* SPORT1 receive */
45#define CH_SPORT1_TX 6 /* SPORT1 transmit */
46#define CH_SPI 7 /* SPI transmit/receive */
47#define CH_UART0_RX 8 /* UART0 receive */
48#define CH_UART0_TX 9 /* UART0 transmit */
49#define CH_UART1_RX 10 /* UART1 receive */
50#define CH_UART1_TX 11 /* UART1 transmit */
51
52#define CH_MEM_STREAM0_DEST 12 /* TX */
53#define CH_MEM_STREAM0_SRC 13 /* RX */
54#define CH_MEM_STREAM1_DEST 14 /* TX */
55#define CH_MEM_STREAM1_SRC 15 /* RX */
56
57extern int channel2irq(unsigned int channel);
58extern struct dma_register *base_addr[];
59
60#endif