diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf527/defBF52x_base.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/defBF52x_base.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h index b1ff67db01f8..d6c24c54699d 100644 --- a/include/asm-blackfin/mach-bf527/defBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h | |||
| @@ -52,13 +52,13 @@ | |||
| 52 | #define SYSCR 0xFFC00104 /* System Configuration Register */ | 52 | #define SYSCR 0xFFC00104 /* System Configuration Register */ |
| 53 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ | 53 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ |
| 54 | 54 | ||
| 55 | #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ | 55 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ |
| 56 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | 56 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ |
| 57 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | 57 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ |
| 58 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | 58 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ |
| 59 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ | 59 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
| 60 | #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ | 60 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ |
| 61 | #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ | 61 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ |
| 62 | 62 | ||
| 63 | /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ | 63 | /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ |
| 64 | #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ | 64 | #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ |
| @@ -691,6 +691,8 @@ | |||
| 691 | 691 | ||
| 692 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ | 692 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ |
| 693 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ | 693 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ |
| 694 | |||
| 695 | #if 0 | ||
| 694 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ | 696 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ |
| 695 | 697 | ||
| 696 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ | 698 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ |
| @@ -732,6 +734,7 @@ | |||
| 732 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ | 734 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ |
| 733 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ | 735 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ |
| 734 | #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ | 736 | #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ |
| 737 | #endif | ||
| 735 | 738 | ||
| 736 | /* SIC_IAR0 Macros */ | 739 | /* SIC_IAR0 Macros */ |
| 737 | #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ | 740 | #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ |