diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf527/cdefBF52x_base.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/cdefBF52x_base.h | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h index 5f801a0ef797..3f4de5d9d4cb 100644 --- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h | |||
| @@ -45,8 +45,8 @@ | |||
| 45 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | 45 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) |
| 46 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 46 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| 47 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) | 47 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) |
| 48 | #define bfin_read_CHIPID() bfin_read16(CHIPID) | 48 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
| 49 | #define bfin_write_CHIPID(val) bfin_write16(CHIPID, val) | 49 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) |
| 50 | 50 | ||
| 51 | 51 | ||
| 52 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | 52 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ |
| @@ -59,9 +59,8 @@ | |||
| 59 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) | 59 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) |
| 60 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) | 60 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) |
| 61 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) | 61 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) |
| 62 | /* legacy register name (below) provided for backwards code compatibility */ | 62 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) |
| 63 | #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) | 63 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) |
| 64 | #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) | ||
| 65 | 64 | ||
| 66 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | 65 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
| 67 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | 66 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) |
| @@ -74,15 +73,13 @@ | |||
| 74 | 73 | ||
| 75 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) | 74 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) |
| 76 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | 75 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) |
| 77 | /* legacy register name (below) provided for backwards code compatibility */ | 76 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) |
| 78 | #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) | 77 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) |
| 79 | #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) | ||
| 80 | 78 | ||
| 81 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) | 79 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) |
| 82 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | 80 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) |
| 83 | /* legacy register name (below) provided for backwards code compatibility */ | 81 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) |
| 84 | #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) | 82 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) |
| 85 | #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) | ||
| 86 | 83 | ||
| 87 | /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ | 84 | /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ |
| 88 | 85 | ||