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Diffstat (limited to 'include/asm-blackfin/mach-bf527/cdefBF52x_base.h')
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h1204
1 files changed, 0 insertions, 1204 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
deleted file mode 100644
index 9dbdbec8ea1b..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ /dev/null
@@ -1,1204 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H
33
34#include <asm/system.h>
35#include <asm/blackfin.h>
36
37#include "defBF52x_base.h"
38
39/* Include core specific register pointer definitions */
40#include <asm/mach-common/cdef_LPBlackfin.h>
41
42/* ==== begin from cdefBF534.h ==== */
43
44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
72#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
100#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
101#define bfin_read_CHIPID() bfin_read32(CHIPID)
102#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
103
104
105/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
106#define bfin_read_SWRST() bfin_read16(SWRST)
107#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
108#define bfin_read_SYSCR() bfin_read16(SYSCR)
109#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
110
111#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
112#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
113#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
114#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
115#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
116#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
117
118#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
119#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
120#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
121#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
122#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
123#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
124#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
125#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
126
127#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
128#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
129#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
130#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
131
132#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
133#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
134#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
135#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
136
137/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
138
139#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
140#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
141#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
142#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
143#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
144#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
145#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
146#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
147#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
148#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
149#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
150#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
151#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
152#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
153
154/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
155#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
156#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
157#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
158#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
159#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
160#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
161
162
163/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
164#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
165#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
166#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
167#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
168#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
169#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
170#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
171#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
172#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
173#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
174#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
175#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
176#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
177#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
178
179
180/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
181#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
182#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
183#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
184#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
185#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
186#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
187#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
188#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
189#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
190#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
191#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
192#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
193#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
194#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
195#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
196#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
197#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
198#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
199#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
200#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
201#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
202#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
203#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
204#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
205
206
207/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
208#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
209#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
210#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
211#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
212#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
213#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
214#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
215#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
216#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
217#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
218#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
219#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
220#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
221#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
222
223
224/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
225#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
226#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
227#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
228#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
229#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
230#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
231#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
232#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
233
234#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
235#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
236#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
237#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
238#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
239#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
240#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
241#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
242
243#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
244#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
245#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
246#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
247#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
248#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
249#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
250#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
251
252#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
253#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
254#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
255#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
256#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
257#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
258#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
259#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
260
261#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
262#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
263#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
264#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
265#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
266#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
267#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
268#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
269
270#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
271#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
272#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
273#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
274#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
275#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
276#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
277#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
278
279#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
280#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
281#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
282#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
283#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
284#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
285#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
286#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
287
288#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
289#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
290#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
291#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
292#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
293#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
294#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
295#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
296
297#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
298#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
299#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
300#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
301#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
302#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
303
304
305/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
306#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
307#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
308#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
309#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
310#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
311#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
312#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
313#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
314#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
315#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
316#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
317#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
318#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
319#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
320#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
321#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
322#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
323#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
324#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
325#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
326#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
327#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
328#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
329#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
330#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
331#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
332#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
333#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
334#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
335#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
336#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
337#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
338#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
339#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
340
341
342/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
343#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
344#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
345#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
346#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
347#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
348#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
349#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
350#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
351#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
352#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
353#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
354#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
355#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
356#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
357#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
358#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
359#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
360#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
361#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
362#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
363#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
364#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
365#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
366#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
367#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
368#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
369#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
370#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
371#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
372#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
373#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
374#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
375#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
376#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
377#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
378#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
379#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
380#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
381#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
382#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
383#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
384#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
385#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
386#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
387#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
388#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
389#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
390#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
391#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
392#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
393#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
394#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
395
396
397/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
398#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
399#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
400#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
401#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
402#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
403#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
404#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
405#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
406#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
407#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
408#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
409#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
410#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
411#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
412#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
413#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
414#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
415#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
416#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
417#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
418#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
419#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
420#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
421#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
422#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
423#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
424#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
425#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
426#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
427#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
428#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
429#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
430#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
431#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
432#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
433#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
434#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
435#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
436#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
437#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
438#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
439#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
440#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
441#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
442#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
443#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
444#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
445#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
446#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
447#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
448#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
449#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
450
451
452/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
453#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
454#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
455#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
456#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
457#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
458#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
459#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
460#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
461#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
462#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
463#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
464#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
465#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
466#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
467
468
469/* DMA Traffic Control Registers */
470#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
471#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
472#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
473#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
474
475/* Alternate deprecated register names (below) provided for backwards code compatibility */
476#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
477#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
478#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
479#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
480
481/* DMA Controller */
482#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
483#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
484#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
485#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
486#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
487#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
488#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
489#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
490#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
491#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
492#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
493#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
494#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
495#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
496#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
497#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
498#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
499#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
500#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
501#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
502#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
503#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
504#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
505#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
506#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
507#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
508
509#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
510#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
511#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
512#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
513#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
514#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
515#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
516#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
517#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
518#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
519#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
520#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
521#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
522#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
523#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
524#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
525#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
526#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
527#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
528#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
529#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
530#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
531#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
532#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
533#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
534#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
535
536#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
537#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
538#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
539#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
540#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
541#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
542#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
543#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
544#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
545#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
546#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
547#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
548#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
549#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
550#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
551#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
552#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
553#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
554#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
555#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
556#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
557#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
558#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
559#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
560#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
561#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
562
563#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
564#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
565#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
566#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
567#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
568#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
569#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
570#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
571#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
572#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
573#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
574#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
575#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
576#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
577#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
578#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
579#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
580#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
581#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
582#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
583#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
584#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
585#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
586#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
587#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
588#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
589
590#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
591#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
592#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
593#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
594#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
595#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
596#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
597#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
598#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
599#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
600#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
601#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
602#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
603#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
604#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
605#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
606#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
607#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
608#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
609#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
610#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
611#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
612#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
613#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
614#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
615#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
616
617#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
618#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
619#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
620#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
621#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
622#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
623#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
624#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
625#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
626#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
627#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
628#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
629#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
630#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
631#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
632#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
633#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
634#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
635#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
636#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
637#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
638#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
639#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
640#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
641#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
642#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
643
644#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
645#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
646#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
647#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
648#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
649#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
650#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
651#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
652#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
653#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
654#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
655#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
656#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
657#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
658#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
659#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
660#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
661#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
662#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
663#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
664#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
665#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
666#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
667#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
668#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
669#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
670
671#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
672#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
673#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
674#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
675#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
676#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
677#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
678#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
679#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
680#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
681#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
682#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
683#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
684#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
685#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
686#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
687#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
688#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
689#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
690#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
691#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
692#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
693#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
694#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
695#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
696#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
697
698#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
699#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
700#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
701#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
702#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
703#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
704#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
705#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
706#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
707#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
708#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
709#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
710#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
711#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
712#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
713#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
714#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
715#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
716#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
717#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
718#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
719#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
720#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
721#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
722#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
723#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
724
725#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
726#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
727#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
728#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
729#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
730#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
731#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
732#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
733#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
734#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
735#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
736#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
737#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
738#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
739#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
740#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
741#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
742#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
743#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
744#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
745#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
746#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
747#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
748#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
749#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
750#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
751
752#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
753#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
754#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
755#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
756#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
757#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
758#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
759#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
760#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
761#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
762#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
763#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
764#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
765#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
766#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
767#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
768#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
769#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
770#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
771#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
772#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
773#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
774#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
775#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
776#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
777#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
778
779#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
780#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
781#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
782#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
783#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
784#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
785#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
786#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
787#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
788#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
789#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
790#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
791#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
792#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
793#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
794#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
795#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
796#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
797#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
798#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
799#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
800#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
801#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
802#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
803#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
804#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
805
806#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
807#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
808#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
809#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
810#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
811#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
812#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
813#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
814#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
815#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
816#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
817#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
818#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
819#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
820#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
821#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
822#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
823#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
824#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
825#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
826#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
827#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
828#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
829#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
830#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
831#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
832
833#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
834#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
835#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
836#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
837#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
838#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
839#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
840#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
841#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
842#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
843#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
844#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
845#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
846#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
847#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
848#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
849#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
850#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
851#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
852#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
853#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
854#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
855#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
856#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
857#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
858#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
859
860#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
861#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
862#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
863#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
864#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
865#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
866#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
867#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
868#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
869#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
870#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
871#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
872#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
873#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
874#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
875#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
876#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
877#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
878#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
879#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
880#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
881#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
882#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
883#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
884#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
885#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
886
887#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
888#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
889#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
890#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
891#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
892#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
893#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
894#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
895#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
896#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
897#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
898#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
899#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
900#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
901#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
902#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
903#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
904#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
905#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
906#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
907#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
908#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
909#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
910#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
911#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
912#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
913
914
915/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
916#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
917#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
918#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
919#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
920#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
921#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
922#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
923#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
924#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
925#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
926
927
928/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
929
930/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
931#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
932#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
933#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
934#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
935#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
936#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
937#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
938#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
939#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
940#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
941#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
942#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
943#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
944#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
945#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
946#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
947#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
948#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
949#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
950#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
951#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
952#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
953#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
954#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
955#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
956#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
957#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
958#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
959#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
960#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
961#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
962#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
963#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
964#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
965
966
967/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
968#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
969#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
970#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
971#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
972#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
973#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
974#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
975#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
976#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
977#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
978#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
979#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
980#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
981#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
982#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
983#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
984#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
985#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
986#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
987#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
988#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
989#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
990#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
991#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
992#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
993#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
994#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
995#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
996#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
997#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
998#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
999#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
1000#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
1001#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
1002
1003
1004/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
1005#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
1006#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1007#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
1008#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1009#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
1010#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1011#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
1012#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
1013#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
1014#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1015#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
1016#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
1017#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1018#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1019#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1020#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1021#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1022#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1023#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1024#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1025#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1026#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1027#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1028#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1029
1030/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
1031
1032/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1033#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1034#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1035#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1036#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1037#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1038#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1039#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
1040#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
1041
1042
1043/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1044#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1045#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1046#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1047#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1048#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1049#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1050#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1051#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1052#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1053#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1054#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1055#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1056#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1057#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1058
1059#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1060#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1061#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1062#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1063#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1064#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1065#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1066#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1067#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1068#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1069#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1070#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1071#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1072#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1073
1074/* ==== end from cdefBF534.h ==== */
1075
1076/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
1077
1078#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
1079#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
1080#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
1081#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
1082#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
1083#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
1084
1085#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
1086#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1087#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1088#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1089#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1090#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1091#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1092#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1093#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1094#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1095#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1096#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1097#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1098#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1099#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1100#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1101#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1102#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1103#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1104#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1105#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1106#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1107#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1108#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1109
1110/* HOST Port Registers */
1111
1112#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1113#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1114#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1115#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1116#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1117#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1118
1119/* Counter Registers */
1120
1121#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1122#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1123#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1124#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1125#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1126#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1127#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1128#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1129#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1130#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1131#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1132#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1133#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1134#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1135#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1136#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1137
1138/* OTP/FUSE Registers */
1139
1140#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1141#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1142#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1143#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1144#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1145#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1146#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1147#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1148
1149/* Security Registers */
1150
1151#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1152#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1153#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1154#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1155#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1156#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1157
1158/* OTP Read/Write Data Buffer Registers */
1159
1160#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1161#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1162#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1163#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1164#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1165#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1166#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1167#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1168
1169/* NFC Registers */
1170
1171#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1172#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1173#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1174#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1175#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1176#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1177#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1178#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1179#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1180#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1181#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1182#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1183#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1184#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1185#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1186#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1187#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1188#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1189#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1190#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1191#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1192#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1193#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1194#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1195#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1196#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1197#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1198#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1199#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1200#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1201#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1202#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1203
1204#endif /* _CDEF_BF52X_H */
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