diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf527/anomaly.h')
-rw-r--r-- | include/asm-blackfin/mach-bf527/anomaly.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index 735fa02fafb2..4725268a5ada 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h | |||
@@ -15,12 +15,16 @@ | |||
15 | 15 | ||
16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
17 | #define ANOMALY_05000074 (1) | 17 | #define ANOMALY_05000074 (1) |
18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | ||
19 | #define ANOMALY_05000119 (1) | ||
18 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
19 | #define ANOMALY_05000122 (1) | 21 | #define ANOMALY_05000122 (1) |
20 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ |
21 | #define ANOMALY_05000245 (1) | 23 | #define ANOMALY_05000245 (1) |
22 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
23 | #define ANOMALY_05000265 (1) | 25 | #define ANOMALY_05000265 (1) |
26 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | ||
27 | #define ANOMALY_05000312 (1) | ||
24 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | 28 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
25 | #define ANOMALY_05000328 (1) | 29 | #define ANOMALY_05000328 (1) |
26 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | 30 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
@@ -92,7 +96,6 @@ | |||
92 | #define ANOMALY_05000266 (0) | 96 | #define ANOMALY_05000266 (0) |
93 | #define ANOMALY_05000273 (0) | 97 | #define ANOMALY_05000273 (0) |
94 | #define ANOMALY_05000311 (0) | 98 | #define ANOMALY_05000311 (0) |
95 | #define ANOMALY_05000312 (0) | ||
96 | #define ANOMALY_05000323 (0) | 99 | #define ANOMALY_05000323 (0) |
97 | #define ANOMALY_05000363 (0) | 100 | #define ANOMALY_05000363 (0) |
98 | 101 | ||