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Diffstat (limited to 'include/asm-blackfin/dpmc.h')
-rw-r--r--include/asm-blackfin/dpmc.h82
1 files changed, 31 insertions, 51 deletions
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
index 7f34cd384f12..de28e6e018b3 100644
--- a/include/asm-blackfin/dpmc.h
+++ b/include/asm-blackfin/dpmc.h
@@ -7,63 +7,18 @@
7#ifndef _BLACKFIN_DPMC_H_ 7#ifndef _BLACKFIN_DPMC_H_
8#define _BLACKFIN_DPMC_H_ 8#define _BLACKFIN_DPMC_H_
9 9
10#define SLEEP_MODE 1
11#define DEEP_SLEEP_MODE 2
12#define ACTIVE_PLL_DISABLED 3
13#define FULLON_MODE 4
14#define ACTIVE_PLL_ENABLED 5
15#define HIBERNATE_MODE 6
16
17#define IOCTL_FULL_ON_MODE _IO('s', 0xA0)
18#define IOCTL_ACTIVE_MODE _IO('s', 0xA1)
19#define IOCTL_SLEEP_MODE _IO('s', 0xA2)
20#define IOCTL_DEEP_SLEEP_MODE _IO('s', 0xA3)
21#define IOCTL_HIBERNATE_MODE _IO('s', 0xA4)
22#define IOCTL_CHANGE_FREQUENCY _IOW('s', 0xA5, unsigned long)
23#define IOCTL_CHANGE_VOLTAGE _IOW('s', 0xA6, unsigned long)
24#define IOCTL_SET_CCLK _IOW('s', 0xA7, unsigned long)
25#define IOCTL_SET_SCLK _IOW('s', 0xA8, unsigned long)
26#define IOCTL_GET_PLLSTATUS _IOW('s', 0xA9, unsigned long)
27#define IOCTL_GET_CORECLOCK _IOW('s', 0xAA, unsigned long)
28#define IOCTL_GET_SYSTEMCLOCK _IOW('s', 0xAB, unsigned long)
29#define IOCTL_GET_VCO _IOW('s', 0xAC, unsigned long)
30#define IOCTL_DISABLE_WDOG_TIMER _IO('s', 0xAD)
31#define IOCTL_UNMASK_WDOG_WAKEUP_EVENT _IO('s',0xAE)
32#define IOCTL_PROGRAM_WDOG_TIMER _IOW('s',0xAF,unsigned long)
33#define IOCTL_CLEAR_WDOG_WAKEUP_EVENT _IO('s',0xB0)
34#define IOCTL_SLEEP_DEEPER_MODE _IO('s',0xB1)
35
36#define DPMC_MINOR 254
37
38#define ON 0
39#define OFF 1
40
41#ifdef __KERNEL__ 10#ifdef __KERNEL__
11#ifndef __ASSEMBLY__
42 12
43unsigned long calc_volt(void);
44int calc_vlev(int vlt);
45unsigned long change_voltage(unsigned long volt);
46int calc_msel(int vco_hz);
47unsigned long change_frequency(unsigned long vco_mhz);
48int set_pll_div(unsigned short sel, unsigned char flag);
49int get_vco(void);
50unsigned long change_system_clock(unsigned long clock);
51unsigned long change_core_clock(unsigned long clock);
52unsigned long get_pll_status(void);
53void change_baud(int baud);
54void fullon_mode(void);
55void active_mode(void);
56void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 13void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
57void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 14void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
58void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 15void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
59void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 16void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
60void program_wdog_timer(unsigned long); 17void do_hibernate(int wakeup);
61void unmask_wdog_wakeup_evt(void); 18void set_dram_srfs(void);
62void clear_wdog_wakeup_evt(void); 19void unset_dram_srfs(void);
63void disable_wdog_timer(void);
64 20
65extern unsigned long get_cclk(void); 21#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
66extern unsigned long get_sclk(void);
67 22
68struct bfin_dpmc_platform_data { 23struct bfin_dpmc_platform_data {
69 const unsigned int *tuple_tab; 24 const unsigned int *tuple_tab;
@@ -71,8 +26,33 @@ struct bfin_dpmc_platform_data {
71 unsigned short vr_settling_time; /* in us */ 26 unsigned short vr_settling_time; /* in us */
72}; 27};
73 28
74#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) 29#else
30
31#define PM_PUSH(x) \
32 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
33 [--SP] = R0;\
34
35#define PM_POP(x) \
36 R0 = [SP++];\
37 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
38
39#define PM_SYS_PUSH(x) \
40 R0 = [P0 + (x - PLL_CTL)];\
41 [--SP] = R0;\
42
43#define PM_SYS_POP(x) \
44 R0 = [SP++];\
45 [P0 + (x - PLL_CTL)] = R0;\
46
47#define PM_SYS_PUSH16(x) \
48 R0 = w[P0 + (x - PLL_CTL)];\
49 [--SP] = R0;\
50
51#define PM_SYS_POP16(x) \
52 R0 = [SP++];\
53 w[P0 + (x - PLL_CTL)] = R0;\
75 54
55#endif
76#endif /* __KERNEL__ */ 56#endif /* __KERNEL__ */
77 57
78#endif /*_BLACKFIN_DPMC_H_*/ 58#endif /*_BLACKFIN_DPMC_H_*/