diff options
Diffstat (limited to 'include/asm-blackfin/bfin5xx_spi.h')
-rw-r--r-- | include/asm-blackfin/bfin5xx_spi.h | 44 |
1 files changed, 6 insertions, 38 deletions
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h index 1a0b57f6a3d4..9fa19158e38d 100644 --- a/include/asm-blackfin/bfin5xx_spi.h +++ b/include/asm-blackfin/bfin5xx_spi.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /************************************************************ | 1 | /************************************************************ |
2 | * | 2 | |
3 | * Copyright (C) 2004, Analog Devices. All Rights Reserved | 3 | * Copyright (C) 2006-2008, Analog Devices. All Rights Reserved |
4 | * | 4 | * |
5 | * FILE bfin5xx_spi.h | 5 | * FILE bfin5xx_spi.h |
6 | * PROGRAMMER(S): Luke Yang (Analog Devices Inc.) | 6 | * PROGRAMMER(S): Luke Yang (Analog Devices Inc.) |
@@ -32,42 +32,6 @@ | |||
32 | #define SPI_BAUD_OFF 0x14 | 32 | #define SPI_BAUD_OFF 0x14 |
33 | #define SPI_SHAW_OFF 0x18 | 33 | #define SPI_SHAW_OFF 0x18 |
34 | 34 | ||
35 | #define CMD_SPI_OUT_ENABLE 1 | ||
36 | #define CMD_SPI_SET_BAUDRATE 2 | ||
37 | #define CMD_SPI_SET_POLAR 3 | ||
38 | #define CMD_SPI_SET_PHASE 4 | ||
39 | #define CMD_SPI_SET_MASTER 5 | ||
40 | #define CMD_SPI_SET_SENDOPT 6 | ||
41 | #define CMD_SPI_SET_RECVOPT 7 | ||
42 | #define CMD_SPI_SET_ORDER 8 | ||
43 | #define CMD_SPI_SET_LENGTH16 9 | ||
44 | #define CMD_SPI_GET_STAT 11 | ||
45 | #define CMD_SPI_GET_CFG 12 | ||
46 | #define CMD_SPI_SET_CSAVAIL 13 | ||
47 | #define CMD_SPI_SET_CSHIGH 14 /* CS unavail */ | ||
48 | #define CMD_SPI_SET_CSLOW 15 /* CS avail */ | ||
49 | #define CMD_SPI_MISO_ENABLE 16 | ||
50 | #define CMD_SPI_SET_CSENABLE 17 | ||
51 | #define CMD_SPI_SET_CSDISABLE 18 | ||
52 | |||
53 | #define CMD_SPI_SET_TRIGGER_MODE 19 | ||
54 | #define CMD_SPI_SET_TRIGGER_SENSE 20 | ||
55 | #define CMD_SPI_SET_TRIGGER_EDGE 21 | ||
56 | #define CMD_SPI_SET_TRIGGER_LEVEL 22 | ||
57 | |||
58 | #define CMD_SPI_SET_TIME_SPS 23 | ||
59 | #define CMD_SPI_SET_TIME_SAMPLES 24 | ||
60 | #define CMD_SPI_GET_SYSTEMCLOCK 25 | ||
61 | |||
62 | #define CMD_SPI_SET_WRITECONTINUOUS 26 | ||
63 | #define CMD_SPI_SET_SKFS 27 | ||
64 | |||
65 | #define CMD_SPI_GET_ALLCONFIG 32 /* For debug */ | ||
66 | |||
67 | #define SPI_DEFAULT_BARD 0x0100 | ||
68 | |||
69 | #define SPI0_IRQ_NUM IRQ_SPI | ||
70 | #define SPI_ERR_TRIG -1 | ||
71 | 35 | ||
72 | #define BIT_CTL_ENABLE 0x4000 | 36 | #define BIT_CTL_ENABLE 0x4000 |
73 | #define BIT_CTL_OPENDRAIN 0x2000 | 37 | #define BIT_CTL_OPENDRAIN 0x2000 |
@@ -148,6 +112,10 @@ | |||
148 | #define CFG_SPI_CS6VALUE 6 | 112 | #define CFG_SPI_CS6VALUE 6 |
149 | #define CFG_SPI_CS7VALUE 7 | 113 | #define CFG_SPI_CS7VALUE 7 |
150 | 114 | ||
115 | #define CMD_SPI_SET_BAUDRATE 2 | ||
116 | #define CMD_SPI_GET_SYSTEMCLOCK 25 | ||
117 | #define CMD_SPI_SET_WRITECONTINUOUS 26 | ||
118 | |||
151 | /* device.platform_data for SSP controller devices */ | 119 | /* device.platform_data for SSP controller devices */ |
152 | struct bfin5xx_spi_master { | 120 | struct bfin5xx_spi_master { |
153 | u16 num_chipselect; | 121 | u16 num_chipselect; |