diff options
Diffstat (limited to 'include/asm-avr32')
| -rw-r--r-- | include/asm-avr32/arch-at32ap/time.h | 112 |
1 files changed, 0 insertions, 112 deletions
diff --git a/include/asm-avr32/arch-at32ap/time.h b/include/asm-avr32/arch-at32ap/time.h deleted file mode 100644 index cc8a43418a4d..000000000000 --- a/include/asm-avr32/arch-at32ap/time.h +++ /dev/null | |||
| @@ -1,112 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2007 Atmel Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H | ||
| 10 | #define _ASM_AVR32_ARCH_AT32AP_TIME_H | ||
| 11 | |||
| 12 | #include <linux/platform_device.h> | ||
| 13 | |||
| 14 | extern struct irqaction timer_irqaction; | ||
| 15 | extern struct platform_device at32_systc0_device; | ||
| 16 | extern void local_timer_interrupt(int irq, void *dev_id); | ||
| 17 | |||
| 18 | #define TIMER_BCR 0x000000c0 | ||
| 19 | #define TIMER_BCR_SYNC 0 | ||
| 20 | #define TIMER_BMR 0x000000c4 | ||
| 21 | #define TIMER_BMR_TC0XC0S 0 | ||
| 22 | #define TIMER_BMR_TC1XC1S 2 | ||
| 23 | #define TIMER_BMR_TC2XC2S 4 | ||
| 24 | #define TIMER_CCR 0x00000000 | ||
| 25 | #define TIMER_CCR_CLKDIS 1 | ||
| 26 | #define TIMER_CCR_CLKEN 0 | ||
| 27 | #define TIMER_CCR_SWTRG 2 | ||
| 28 | #define TIMER_CMR 0x00000004 | ||
| 29 | #define TIMER_CMR_ABETRG 10 | ||
| 30 | #define TIMER_CMR_ACPA 16 | ||
| 31 | #define TIMER_CMR_ACPC 18 | ||
| 32 | #define TIMER_CMR_AEEVT 20 | ||
| 33 | #define TIMER_CMR_ASWTRG 22 | ||
| 34 | #define TIMER_CMR_BCPB 24 | ||
| 35 | #define TIMER_CMR_BCPC 26 | ||
| 36 | #define TIMER_CMR_BEEVT 28 | ||
| 37 | #define TIMER_CMR_BSWTRG 30 | ||
| 38 | #define TIMER_CMR_BURST 4 | ||
| 39 | #define TIMER_CMR_CLKI 3 | ||
| 40 | #define TIMER_CMR_CPCDIS 7 | ||
| 41 | #define TIMER_CMR_CPCSTOP 6 | ||
| 42 | #define TIMER_CMR_CPCTRG 14 | ||
| 43 | #define TIMER_CMR_EEVT 10 | ||
| 44 | #define TIMER_CMR_EEVTEDG 8 | ||
| 45 | #define TIMER_CMR_ENETRG 12 | ||
| 46 | #define TIMER_CMR_ETRGEDG 8 | ||
| 47 | #define TIMER_CMR_LDBDIS 7 | ||
| 48 | #define TIMER_CMR_LDBSTOP 6 | ||
| 49 | #define TIMER_CMR_LDRA 16 | ||
| 50 | #define TIMER_CMR_LDRB 18 | ||
| 51 | #define TIMER_CMR_TCCLKS 0 | ||
| 52 | #define TIMER_CMR_WAVE 15 | ||
| 53 | #define TIMER_CMR_WAVSEL 13 | ||
| 54 | #define TIMER_CV 0x00000010 | ||
| 55 | #define TIMER_CV_CV 0 | ||
| 56 | #define TIMER_IDR 0x00000028 | ||
| 57 | #define TIMER_IDR_COVFS 0 | ||
| 58 | #define TIMER_IDR_CPAS 2 | ||
| 59 | #define TIMER_IDR_CPBS 3 | ||
| 60 | #define TIMER_IDR_CPCS 4 | ||
| 61 | #define TIMER_IDR_ETRGS 7 | ||
| 62 | #define TIMER_IDR_LDRAS 5 | ||
| 63 | #define TIMER_IDR_LDRBS 6 | ||
| 64 | #define TIMER_IDR_LOVRS 1 | ||
| 65 | #define TIMER_IER 0x00000024 | ||
| 66 | #define TIMER_IER_COVFS 0 | ||
| 67 | #define TIMER_IER_CPAS 2 | ||
| 68 | #define TIMER_IER_CPBS 3 | ||
| 69 | #define TIMER_IER_CPCS 4 | ||
| 70 | #define TIMER_IER_ETRGS 7 | ||
| 71 | #define TIMER_IER_LDRAS 5 | ||
| 72 | #define TIMER_IER_LDRBS 6 | ||
| 73 | #define TIMER_IER_LOVRS 1 | ||
| 74 | #define TIMER_IMR 0x0000002c | ||
| 75 | #define TIMER_IMR_COVFS 0 | ||
| 76 | #define TIMER_IMR_CPAS 2 | ||
| 77 | #define TIMER_IMR_CPBS 3 | ||
| 78 | #define TIMER_IMR_CPCS 4 | ||
| 79 | #define TIMER_IMR_ETRGS 7 | ||
| 80 | #define TIMER_IMR_LDRAS 5 | ||
| 81 | #define TIMER_IMR_LDRBS 6 | ||
| 82 | #define TIMER_IMR_LOVRS 1 | ||
| 83 | #define TIMER_RA 0x00000014 | ||
| 84 | #define TIMER_RA_RA 0 | ||
| 85 | #define TIMER_RB 0x00000018 | ||
| 86 | #define TIMER_RB_RB 0 | ||
| 87 | #define TIMER_RC 0x0000001c | ||
| 88 | #define TIMER_RC_RC 0 | ||
| 89 | #define TIMER_SR 0x00000020 | ||
| 90 | #define TIMER_SR_CLKSTA 16 | ||
| 91 | #define TIMER_SR_COVFS 0 | ||
| 92 | #define TIMER_SR_CPAS 2 | ||
| 93 | #define TIMER_SR_CPBS 3 | ||
| 94 | #define TIMER_SR_CPCS 4 | ||
| 95 | #define TIMER_SR_ETRGS 7 | ||
| 96 | #define TIMER_SR_LDRAS 5 | ||
| 97 | #define TIMER_SR_LDRBS 6 | ||
| 98 | #define TIMER_SR_LOVRS 1 | ||
| 99 | #define TIMER_SR_MTIOA 17 | ||
| 100 | #define TIMER_SR_MTIOB 18 | ||
| 101 | |||
| 102 | /* Bit manipulation macros */ | ||
| 103 | #define TIMER_BIT(name) (1 << TIMER_##name) | ||
| 104 | #define TIMER_BF(name,value) ((value) << TIMER_##name) | ||
| 105 | |||
| 106 | /* Register access macros */ | ||
| 107 | #define timer_read(port,instance,reg) \ | ||
| 108 | __raw_readl(port + (0x40 * instance) + TIMER_##reg) | ||
| 109 | #define timer_write(port,instance,reg,value) \ | ||
| 110 | __raw_writel((value), port + (0x40 * instance) + TIMER_##reg) | ||
| 111 | |||
| 112 | #endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */ | ||