2 files changed, 15 insertions, 7 deletions

diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 5e56b47446e0..3241cd6f0778 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -17,16 +17,21 @@
 
 #define IO_SPACE_LIMIT          0xffffffff
 #define __mem_pci(a)            (a)
-#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
 
 /*
- * The IXP2400 before revision B0 asserts byte lanes for PCI I/O
+ * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
  * transactions the other way round (MEM transactions don't have this
- * issue), so we need to override the standard functions.  B0 and later
- * have a bit that can be set to 1 to get the 'proper' behavior, but
- * since that isn't available on the A? revisions we just keep doing
- * things manually.
+ * issue), so if we want to support those models, we need to override
+ * the standard I/O functions.
+ *
+ * B0 and later have a bit that can be set to 1 to get the proper
+ * behavior for I/O transactions, which then allows us to use the
+ * standard I/O functions.  This is what we do if the user does not
+ * explicitly ask for support for pre-B0.
  */
+#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
+#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+
 #define alignb(addr)            (void __iomem *)((unsigned long)(addr) ^ 3)
 #define alignw(addr)            (void __iomem *)((unsigned long)(addr) ^ 2)
 
@@ -119,6 +124,9 @@
 #define ioport_map(port, nr)    ___io(port)
 
 #define ioport_unmap(addr)
+#else
+#define __io(p)                 ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#endif
 
 
 #ifdef CONFIG_ARCH_IXDP2X01
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index a1d9e181b10f..5eb47d4bfbf6 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -241,7 +241,7 @@
 #define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
 #define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
 #define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
-#define PCI_CONTROL_PNR                 (1 << 17)       /* PCI Not Reset bit */
+#define PCI_CONTROL_IEE                 (1 << 17)       /* I/O cycle Endian swap Enable */
 
 #define IXP2000_PCI_RST_REL             (1 << 2)
 #define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)