6 files changed, 175 insertions, 45 deletions

diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 5f531ea03059..afad32c76e6c 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -185,9 +185,15 @@ struct cpu_cache_fns {
         void (*coherent_user_range)(unsigned long, unsigned long);
         void (*flush_kern_dcache_page)(void *);
 
-        void (*dma_inv_range)(unsigned long, unsigned long);
-        void (*dma_clean_range)(unsigned long, unsigned long);
-        void (*dma_flush_range)(unsigned long, unsigned long);
+        void (*dma_inv_range)(const void *, const void *);
+        void (*dma_clean_range)(const void *, const void *);
+        void (*dma_flush_range)(const void *, const void *);
+};
+
+struct outer_cache_fns {
+        void (*inv_range)(unsigned long, unsigned long);
+        void (*clean_range)(unsigned long, unsigned long);
+        void (*flush_range)(unsigned long, unsigned long);
 };
 
 /*
@@ -240,9 +246,40 @@ extern void __cpuc_flush_dcache_page(void *);
 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 
-extern void dmac_inv_range(unsigned long, unsigned long);
-extern void dmac_clean_range(unsigned long, unsigned long);
-extern void dmac_flush_range(unsigned long, unsigned long);
+extern void dmac_inv_range(const void *, const void *);
+extern void dmac_clean_range(const void *, const void *);
+extern void dmac_flush_range(const void *, const void *);
+
+#endif
+
+#ifdef CONFIG_OUTER_CACHE
+
+extern struct outer_cache_fns outer_cache;
+
+static inline void outer_inv_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.inv_range)
+                outer_cache.inv_range(start, end);
+}
+static inline void outer_clean_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.clean_range)
+                outer_cache.clean_range(start, end);
+}
+static inline void outer_flush_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.flush_range)
+                outer_cache.flush_range(start, end);
+}
+
+#else
+
+static inline void outer_inv_range(unsigned long start, unsigned long end)
+{ }
+static inline void outer_clean_range(unsigned long start, unsigned long end)
+{ }
+static inline void outer_flush_range(unsigned long start, unsigned long end)
+{ }
 
 #endif
 
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index 9bc46b486afb..a1d574cdcc14 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -17,7 +17,7 @@
  * platforms with CONFIG_DMABOUNCE.
  * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  */
-extern void consistent_sync(void *kaddr, size_t size, int rw);
+extern void consistent_sync(const void *kaddr, size_t size, int rw);
 
 /*
  * Return whether the given device DMA address mask can be supported
diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h
index 4c2885abbe6c..3c12a7625304 100644
--- a/include/asm-arm/domain.h
+++ b/include/asm-arm/domain.h
@@ -57,6 +57,7 @@
         __asm__ __volatile__(                           \
         "mcr    p15, 0, %0, c3, c0      @ set domain"   \
           : : "r" (x));                                 \
+        isb();                                          \
         } while (0)
 
 #define modify_domain(dom,type)                                 \
diff --git a/include/asm-arm/hardware/cache-l2x0.h b/include/asm-arm/hardware/cache-l2x0.h
new file mode 100644
index 000000000000..54029a740396
--- /dev/null
+++ b/include/asm-arm/hardware/cache-l2x0.h
@@ -0,0 +1,56 @@
+/*
+ * include/asm-arm/hardware/cache-l2x0.h
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_HARDWARE_L2X0_H
+#define __ASM_ARM_HARDWARE_L2X0_H
+
+#define L2X0_CACHE_ID                   0x000
+#define L2X0_CACHE_TYPE                 0x004
+#define L2X0_CTRL                       0x100
+#define L2X0_AUX_CTRL                   0x104
+#define L2X0_EVENT_CNT_CTRL             0x200
+#define L2X0_EVENT_CNT1_CFG             0x204
+#define L2X0_EVENT_CNT0_CFG             0x208
+#define L2X0_EVENT_CNT1_VAL             0x20C
+#define L2X0_EVENT_CNT0_VAL             0x210
+#define L2X0_INTR_MASK                  0x214
+#define L2X0_MASKED_INTR_STAT           0x218
+#define L2X0_RAW_INTR_STAT              0x21C
+#define L2X0_INTR_CLEAR                 0x220
+#define L2X0_CACHE_SYNC                 0x730
+#define L2X0_INV_LINE_PA                0x770
+#define L2X0_INV_WAY                    0x77C
+#define L2X0_CLEAN_LINE_PA              0x7B0
+#define L2X0_CLEAN_LINE_IDX             0x7B8
+#define L2X0_CLEAN_WAY                  0x7BC
+#define L2X0_CLEAN_INV_LINE_PA          0x7F0
+#define L2X0_CLEAN_INV_LINE_IDX         0x7F8
+#define L2X0_CLEAN_INV_WAY              0x7FC
+#define L2X0_LOCKDOWN_WAY_D             0x900
+#define L2X0_LOCKDOWN_WAY_I             0x904
+#define L2X0_TEST_OPERATION             0xF00
+#define L2X0_LINE_DATA                  0xF10
+#define L2X0_LINE_TAG                   0xF30
+#define L2X0_DEBUG_CTRL                 0xF40
+
+#ifndef __ASSEMBLY__
+extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+#endif
+
+#endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index aa223fc546af..f4386906b200 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -140,6 +140,40 @@ static inline int cpu_is_xsc3(void)
 #define cpu_is_xscale() 1
 #endif
 
+#define UDBG_UNDEFINED  (1 << 0)
+#define UDBG_SYSCALL    (1 << 1)
+#define UDBG_BADABORT   (1 << 2)
+#define UDBG_SEGV       (1 << 3)
+#define UDBG_BUS        (1 << 4)
+
+extern unsigned int user_debug;
+
+#if __LINUX_ARM_ARCH__ >= 4
+#define vectors_high()  (cr_alignment & CR_V)
+#else
+#define vectors_high()  (0)
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 6
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+                                    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+                                    : : "r" (0) : "memory")
+#else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#endif
+#define mb() dmb()
+#define rmb() mb()
+#define wmb() mb()
+#define read_barrier_depends() do { } while(0)
+#define set_mb(var, value)  do { var = value; mb(); } while (0)
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 
@@ -154,6 +188,7 @@ static inline void set_cr(unsigned int val)
 {
         asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
           : : "r" (val) : "cc");
+        isb();
 }
 
 #ifndef CONFIG_SMP
@@ -176,34 +211,9 @@ static inline void set_copro_access(unsigned int val)
 {
         asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
           : : "r" (val) : "cc");
+        isb();
 }
 
-#define UDBG_UNDEFINED  (1 << 0)
-#define UDBG_SYSCALL    (1 << 1)
-#define UDBG_BADABORT   (1 << 2)
-#define UDBG_SEGV       (1 << 3)
-#define UDBG_BUS        (1 << 4)
-
-extern unsigned int user_debug;
-
-#if __LINUX_ARM_ARCH__ >= 4
-#define vectors_high()  (cr_alignment & CR_V)
-#else
-#define vectors_high()  (0)
-#endif
-
-#if __LINUX_ARM_ARCH__ >= 6
-#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
-                                   : : "r" (0) : "memory")
-#else
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-#endif
-#define rmb() mb()
-#define wmb() mb()
-#define read_barrier_depends() do { } while(0)
-#define set_mb(var, value)  do { var = value; mb(); } while (0)
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
 /*
  * switch_mm() may do a full cache flush over the context switch,
  * so enable interrupts over the context switch to avoid high
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index cd10a0b5f8ae..08c6991dc9c9 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -247,7 +247,7 @@ static inline void local_flush_tlb_all(void)
         const unsigned int __tlb_flag = __cpu_tlb_flags;
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+                dsb();
 
         if (tlb_flag(TLB_V3_FULL))
                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
@@ -257,6 +257,15 @@ static inline void local_flush_tlb_all(void)
                 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
+
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+                isb();
+        }
 }
 
 static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -266,7 +275,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
         const unsigned int __tlb_flag = __cpu_tlb_flags;
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+                dsb();
 
         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
                 if (tlb_flag(TLB_V3_FULL))
@@ -285,6 +294,14 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
                 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
         if (tlb_flag(TLB_V6_I_ASID))
                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
+
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+        }
 }
 
 static inline void
@@ -296,7 +313,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
         uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero));
+                dsb();
 
         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
                 if (tlb_flag(TLB_V3_PAGE))
@@ -317,6 +334,14 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
+
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+        }
 }
 
 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -327,7 +352,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
         kaddr &= PAGE_MASK;
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+                dsb();
 
         if (tlb_flag(TLB_V3_PAGE))
                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
@@ -347,11 +372,14 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 
-        /* The ARM ARM states that the completion of a TLB maintenance
-         * operation is only guaranteed by a DSB instruction
-         */
-        if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+                isb();
+        }
 }
 
 /*
@@ -369,15 +397,13 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
  */
 static inline void flush_pmd_entry(pmd_t *pmd)
 {
-        const unsigned int zero = 0;
         const unsigned int __tlb_flag = __cpu_tlb_flags;
 
         if (tlb_flag(TLB_DCLEAN))
                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                         : : "r" (pmd) : "cc");
         if (tlb_flag(TLB_WB))
-                asm("mcr        p15, 0, %0, c7, c10, 4  @ flush_pmd"
-                        : : "r" (zero) : "cc");
+                dsb();
 }
 
 static inline void clean_pmd_entry(pmd_t *pmd)