diff options
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-clock.h | 6 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-gpio.h | 5 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/uncompress.h | 5 |
3 files changed, 12 insertions, 4 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index 34360706e016..6c92faffe985 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h | |||
@@ -114,7 +114,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) | |||
114 | 114 | ||
115 | #endif /* __ASSEMBLY__ */ | 115 | #endif /* __ASSEMBLY__ */ |
116 | 116 | ||
117 | #ifdef CONFIG_CPU_S3C2440 | 117 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) |
118 | 118 | ||
119 | /* extra registers */ | 119 | /* extra registers */ |
120 | #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) | 120 | #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) |
@@ -136,7 +136,9 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) | |||
136 | #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) | 136 | #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) |
137 | #define S3C2440_CAMDIVN_DVSEN (1<<12) | 137 | #define S3C2440_CAMDIVN_DVSEN (1<<12) |
138 | 138 | ||
139 | #endif /* CONFIG_CPU_S3C2440 */ | 139 | #define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) |
140 | |||
141 | #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ | ||
140 | 142 | ||
141 | 143 | ||
142 | #endif /* __ASM_ARM_REGS_CLOCK */ | 144 | #endif /* __ASM_ARM_REGS_CLOCK */ |
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index d2574084697f..5f10334f06bf 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h | |||
@@ -450,12 +450,14 @@ | |||
450 | #define S3C2410_GPD0_OUTP (0x01 << 0) | 450 | #define S3C2410_GPD0_OUTP (0x01 << 0) |
451 | #define S3C2410_GPD0_VD8 (0x02 << 0) | 451 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
452 | #define S3C2400_GPD0_VFRAME (0x02 << 0) | 452 | #define S3C2400_GPD0_VFRAME (0x02 << 0) |
453 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) | ||
453 | 454 | ||
454 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) | 455 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) |
455 | #define S3C2410_GPD1_INP (0x00 << 2) | 456 | #define S3C2410_GPD1_INP (0x00 << 2) |
456 | #define S3C2410_GPD1_OUTP (0x01 << 2) | 457 | #define S3C2410_GPD1_OUTP (0x01 << 2) |
457 | #define S3C2410_GPD1_VD9 (0x02 << 2) | 458 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
458 | #define S3C2400_GPD1_VM (0x02 << 2) | 459 | #define S3C2400_GPD1_VM (0x02 << 2) |
460 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) | ||
459 | 461 | ||
460 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) | 462 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) |
461 | #define S3C2410_GPD2_INP (0x00 << 4) | 463 | #define S3C2410_GPD2_INP (0x00 << 4) |
@@ -858,6 +860,7 @@ | |||
858 | #define S3C2410_GPG12_OUTP (0x01 << 24) | 860 | #define S3C2410_GPG12_OUTP (0x01 << 24) |
859 | #define S3C2410_GPG12_EINT20 (0x02 << 24) | 861 | #define S3C2410_GPG12_EINT20 (0x02 << 24) |
860 | #define S3C2410_GPG12_XMON (0x03 << 24) | 862 | #define S3C2410_GPG12_XMON (0x03 << 24) |
863 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) | ||
861 | 864 | ||
862 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) | 865 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) |
863 | #define S3C2410_GPG13_INP (0x00 << 26) | 866 | #define S3C2410_GPG13_INP (0x00 << 26) |
@@ -943,6 +946,7 @@ | |||
943 | #define S3C2410_GPH9_INP (0x00 << 18) | 946 | #define S3C2410_GPH9_INP (0x00 << 18) |
944 | #define S3C2410_GPH9_OUTP (0x01 << 18) | 947 | #define S3C2410_GPH9_OUTP (0x01 << 18) |
945 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) | 948 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) |
949 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) | ||
946 | 950 | ||
947 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) | 951 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) |
948 | #define S3C2410_GPH10_INP (0x00 << 20) | 952 | #define S3C2410_GPH10_INP (0x00 << 20) |
@@ -1051,6 +1055,7 @@ | |||
1051 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) | 1055 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) |
1052 | #define S3C2410_GSTATUS1_2410 (0x32410000) | 1056 | #define S3C2410_GSTATUS1_2410 (0x32410000) |
1053 | #define S3C2410_GSTATUS1_2440 (0x32440000) | 1057 | #define S3C2410_GSTATUS1_2440 (0x32440000) |
1058 | #define S3C2410_GSTATUS1_2442 (0x32440aaa) | ||
1054 | 1059 | ||
1055 | #define S3C2410_GSTATUS2_WTRESET (1<<2) | 1060 | #define S3C2410_GSTATUS2_WTRESET (1<<2) |
1056 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) | 1061 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) |
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index a6f6a0e44afa..bbd9ee1ff75a 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h | |||
@@ -82,7 +82,8 @@ static void putc(int ch) | |||
82 | while (1) { | 82 | while (1) { |
83 | level = uart_rd(S3C2410_UFSTAT); | 83 | level = uart_rd(S3C2410_UFSTAT); |
84 | 84 | ||
85 | if (cpuid == S3C2410_GSTATUS1_2440) { | 85 | if (cpuid == S3C2410_GSTATUS1_2440 || |
86 | cpuid == S3C2410_GSTATUS1_2442) { | ||
86 | level &= S3C2440_UFSTAT_TXMASK; | 87 | level &= S3C2440_UFSTAT_TXMASK; |
87 | level >>= S3C2440_UFSTAT_TXSHIFT; | 88 | level >>= S3C2440_UFSTAT_TXSHIFT; |
88 | } else { | 89 | } else { |
@@ -130,7 +131,7 @@ static void arch_decomp_wdog_start(void) | |||
130 | { | 131 | { |
131 | __raw_writel(WDOG_COUNT, S3C2410_WTDAT); | 132 | __raw_writel(WDOG_COUNT, S3C2410_WTDAT); |
132 | __raw_writel(WDOG_COUNT, S3C2410_WTCNT); | 133 | __raw_writel(WDOG_COUNT, S3C2410_WTCNT); |
133 | __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); | 134 | __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); |
134 | } | 135 | } |
135 | 136 | ||
136 | #else | 137 | #else |