aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-aaec2000/io.h1
-rw-r--r--include/asm-arm/arch-clps711x/io.h1
-rw-r--r--include/asm-arm/arch-ebsa285/io.h8
-rw-r--r--include/asm-arm/arch-ep93xx/ep93xx-regs.h2
-rw-r--r--include/asm-arm/arch-ep93xx/platform.h1
-rw-r--r--include/asm-arm/arch-integrator/io.h1
-rw-r--r--include/asm-arm/arch-iop3xx/io.h1
-rw-r--r--include/asm-arm/arch-l7200/io.h1
-rw-r--r--include/asm-arm/arch-lh7a40x/io.h1
-rw-r--r--include/asm-arm/arch-netx/io.h1
-rw-r--r--include/asm-arm/arch-omap/io.h1
-rw-r--r--include/asm-arm/arch-pxa/io.h1
-rw-r--r--include/asm-arm/arch-realview/io.h1
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S10
-rw-r--r--include/asm-arm/arch-s3c2410/entry-macro.S30
-rw-r--r--include/asm-arm/arch-s3c2410/map.h16
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h63
-rw-r--r--include/asm-arm/arch-s3c2410/regs-dsc.h3
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h63
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpioj.h5
-rw-r--r--include/asm-arm/arch-s3c2410/regs-irq.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-serial.h15
-rw-r--r--include/asm-arm/arch-sa1100/io.h1
-rw-r--r--include/asm-arm/arch-versatile/io.h1
-rw-r--r--include/asm-arm/ucontext.h79
25 files changed, 263 insertions, 50 deletions
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
index 8d67907fd4f0..d710204ac747 100644
--- a/include/asm-arm/arch-aaec2000/io.h
+++ b/include/asm-arm/arch-aaec2000/io.h
@@ -16,6 +16,5 @@
16 */ 16 */
17#define __io(a) ((void __iomem *)(a)) 17#define __io(a) ((void __iomem *)(a))
18#define __mem_pci(a) (a) 18#define __mem_pci(a) (a)
19#define __mem_isa(a) (a)
20 19
21#endif 20#endif
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
index 62613b0e2d96..53d790202c19 100644
--- a/include/asm-arm/arch-clps711x/io.h
+++ b/include/asm-arm/arch-clps711x/io.h
@@ -26,7 +26,6 @@
26 26
27#define __io(a) ((void __iomem *)(a)) 27#define __io(a) ((void __iomem *)(a))
28#define __mem_pci(a) (a) 28#define __mem_pci(a) (a)
29#define __mem_isa(a) (a)
30 29
31/* 30/*
32 * We don't support ins[lb]/outs[lb]. Make them fault. 31 * We don't support ins[lb]/outs[lb]. Make them fault.
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
index 776f9d377057..f9c729141860 100644
--- a/include/asm-arm/arch-ebsa285/io.h
+++ b/include/asm-arm/arch-ebsa285/io.h
@@ -24,7 +24,6 @@
24#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) 24#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
25#if 1 25#if 1
26#define __mem_pci(a) (a) 26#define __mem_pci(a) (a)
27#define __mem_isa(a) ((a) + PCIMEM_BASE)
28#else 27#else
29 28
30static inline void __iomem *___mem_pci(void __iomem *p) 29static inline void __iomem *___mem_pci(void __iomem *p)
@@ -34,14 +33,7 @@ static inline void __iomem *___mem_pci(void __iomem *p)
34 return p; 33 return p;
35} 34}
36 35
37static inline void __iomem *___mem_isa(void __iomem *p)
38{
39 unsigned long a = (unsigned long)p;
40 BUG_ON(a >= 16*1048576);
41 return p + PCIMEM_BASE;
42}
43#define __mem_pci(a) ___mem_pci(a) 36#define __mem_pci(a) ___mem_pci(a)
44#define __mem_isa(a) ___mem_isa(a)
45#endif 37#endif
46 38
47#endif 39#endif
diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
index 71cea0b5841b..8c322975f96e 100644
--- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h
+++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
@@ -115,6 +115,8 @@
115#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 115#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000
116#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) 116#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
117#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) 117#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
118#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
119#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
118#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) 120#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80)
119#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 121#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000
120#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) 122#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
diff --git a/include/asm-arm/arch-ep93xx/platform.h b/include/asm-arm/arch-ep93xx/platform.h
index df9cbb6ef660..d7a34ce20293 100644
--- a/include/asm-arm/arch-ep93xx/platform.h
+++ b/include/asm-arm/arch-ep93xx/platform.h
@@ -8,6 +8,7 @@ void ep93xx_map_io(void);
8void ep93xx_init_irq(void); 8void ep93xx_init_irq(void);
9void ep93xx_init_time(unsigned long); 9void ep93xx_init_time(unsigned long);
10void ep93xx_init_devices(void); 10void ep93xx_init_devices(void);
11void ep93xx_clock_init(void);
11extern struct sys_timer ep93xx_timer; 12extern struct sys_timer ep93xx_timer;
12 13
13 14
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
index 31f2deab51b0..c8f2175948bd 100644
--- a/include/asm-arm/arch-integrator/io.h
+++ b/include/asm-arm/arch-integrator/io.h
@@ -32,6 +32,5 @@
32 32
33#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) 33#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
34#define __mem_pci(a) (a) 34#define __mem_pci(a) (a)
35#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
36 35
37#endif 36#endif
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h
index f39046a6ab14..36adbdf5055a 100644
--- a/include/asm-arm/arch-iop3xx/io.h
+++ b/include/asm-arm/arch-iop3xx/io.h
@@ -17,6 +17,5 @@
17 17
18#define __io(p) ((void __iomem *)(p)) 18#define __io(p) ((void __iomem *)(p))
19#define __mem_pci(a) (a) 19#define __mem_pci(a) (a)
20#define __mem_isa(a) (a)
21 20
22#endif 21#endif
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index cab8ad0adf09..cd080d8384d9 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -19,7 +19,6 @@
19 */ 19 */
20#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a))) 20#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a)))
21#define __mem_pci(a) (a) 21#define __mem_pci(a) (a)
22#define __mem_isa(a) (a)
23 22
24#define __ioaddr(p) __io_pci(p) 23#define __ioaddr(p) __io_pci(p)
25 24
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
index bbcd4335f441..17bc94097481 100644
--- a/include/asm-arm/arch-lh7a40x/io.h
+++ b/include/asm-arm/arch-lh7a40x/io.h
@@ -18,6 +18,5 @@
18/* No ISA or PCI bus on this machine. */ 18/* No ISA or PCI bus on this machine. */
19#define __io(a) ((void __iomem *)(a)) 19#define __io(a) ((void __iomem *)(a))
20#define __mem_pci(a) (a) 20#define __mem_pci(a) (a)
21#define __mem_isa(a) (a)
22 21
23#endif /* __ASM_ARCH_IO_H */ 22#endif /* __ASM_ARCH_IO_H */
diff --git a/include/asm-arm/arch-netx/io.h b/include/asm-arm/arch-netx/io.h
index 81b7bc47747e..a7a53f80165d 100644
--- a/include/asm-arm/arch-netx/io.h
+++ b/include/asm-arm/arch-netx/io.h
@@ -24,6 +24,5 @@
24 24
25#define __io(a) ((void __iomem *)(a)) 25#define __io(a) ((void __iomem *)(a))
26#define __mem_pci(a) (a) 26#define __mem_pci(a) (a)
27#define __mem_isa(a) (a)
28 27
29#endif 28#endif
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index b726acfcab14..78f68e6a4f0c 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -44,7 +44,6 @@
44 */ 44 */
45#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) 45#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
46#define __mem_pci(a) (a) 46#define __mem_pci(a) (a)
47#define __mem_isa(a) (a)
48 47
49/* 48/*
50 * ---------------------------------------------------------------------------- 49 * ----------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
index eb2dd58d397f..7f8d817b446f 100644
--- a/include/asm-arm/arch-pxa/io.h
+++ b/include/asm-arm/arch-pxa/io.h
@@ -16,6 +16,5 @@
16 */ 16 */
17#define __io(a) ((void __iomem *)(a)) 17#define __io(a) ((void __iomem *)(a))
18#define __mem_pci(a) (a) 18#define __mem_pci(a) (a)
19#define __mem_isa(a) (a)
20 19
21#endif 20#endif
diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h
index d444a68ac330..c70f1dfbe135 100644
--- a/include/asm-arm/arch-realview/io.h
+++ b/include/asm-arm/arch-realview/io.h
@@ -29,6 +29,5 @@ static inline void __iomem *__io(unsigned long addr)
29 29
30#define __io(a) __io(a) 30#define __io(a) __io(a)
31#define __mem_pci(a) (a) 31#define __mem_pci(a) (a)
32#define __mem_isa(a) (a)
33 32
34#endif 33#endif
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 5f8223e700d3..b7d15d125458 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -33,7 +33,7 @@
33 .endm 33 .endm
34 34
35 .macro senduart,rd,rx 35 .macro senduart,rd,rx
36 str \rd, [\rx, # S3C2410_UTXH ] 36 strb \rd, [\rx, # S3C2410_UTXH ]
37 .endm 37 .endm
38 38
39 .macro busyuart, rd, rx 39 .macro busyuart, rd, rx
@@ -42,6 +42,12 @@
42 beq 1001f @ 42 beq 1001f @
43 @ FIFO enabled... 43 @ FIFO enabled...
441003: 441003:
45 @ check for arm920 vs arm926. currently assume all arm926
46 @ devices have an 64 byte FIFO identical to the s3c2440
47 mrc p15, 0, \rd, c0, c0
48 and \rd, \rd, #0xff0
49 teq \rd, #0x260
50 beq 1004f
45 mrc p15, 0, \rd, c1, c0 51 mrc p15, 0, \rd, c1, c0
46 tst \rd, #1 52 tst \rd, #1
47 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) 53 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -50,7 +56,7 @@
50 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] 56 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
51 and \rd, \rd, #0x00ff0000 57 and \rd, \rd, #0x00ff0000
52 teq \rd, #0x00440000 @ is it 2440? 58 teq \rd, #0x00440000 @ is it 2440?
53 591004:
54 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 60 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
55 moveq \rd, \rd, lsr #SHIFT_2440TXF 61 moveq \rd, \rd, lsr #SHIFT_2440TXF
56 tst \rd, #S3C2410_UFSTAT_TXFULL 62 tst \rd, #S3C2410_UFSTAT_TXFULL
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
index 894c35cf3b1e..e09a6b8ec153 100644
--- a/include/asm-arm/arch-s3c2410/entry-macro.S
+++ b/include/asm-arm/arch-s3c2410/entry-macro.S
@@ -18,8 +18,6 @@
18 18
19#define INTPND (0x10) 19#define INTPND (0x10)
20#define INTOFFSET (0x14) 20#define INTOFFSET (0x14)
21#define EXTINTPEND (0xa8)
22#define EXTINTMASK (0xa4)
23 21
24#include <asm/hardware.h> 22#include <asm/hardware.h>
25#include <asm/arch/irqs.h> 23#include <asm/arch/irqs.h>
@@ -28,37 +26,23 @@
28 26
29 mov \base, #S3C24XX_VA_IRQ 27 mov \base, #S3C24XX_VA_IRQ
30 28
31 ldr \irqstat, [ \base, #INTPND]
32 bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ
33 beq 2000f
34
35 @@ try the interrupt offset register, since it is there 29 @@ try the interrupt offset register, since it is there
36 30
31 ldr \irqstat, [ \base, #INTPND ]
32 teq \irqstat, #0
33 beq 1002f
37 ldr \irqnr, [ \base, #INTOFFSET ] 34 ldr \irqnr, [ \base, #INTOFFSET ]
38 mov \tmp, #1 35 mov \tmp, #1
39 tst \irqstat, \tmp, lsl \irqnr 36 tst \irqstat, \tmp, lsl \irqnr
40 addne \irqnr, \irqnr, #IRQ_EINT0
41 bne 1001f 37 bne 1001f
42 38
43 @@ the number specified is not a valid irq, so try 39 @@ the number specified is not a valid irq, so try
44 @@ and work it out for ourselves 40 @@ and work it out for ourselves
45 41
46 mov \irqnr, #IRQ_EINT0 @@ start here 42 mov \irqnr, #0 @@ start here
47 b 3000f
48
492000:
50 @@ load the GPIO interrupt register, and check it
51
52 add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
53 ldr \irqstat, [ \tmp, # EXTINTPEND ]
54 ldr \irqnr, [ \tmp, # EXTINTMASK ]
55 bics \irqstat, \irqstat, \irqnr
56 beq 1001f
57
58 mov \irqnr, #(IRQ_EINT4 - 4)
59 43
60 @@ work out which irq (if any) we got 44 @@ work out which irq (if any) we got
613000: 45
62 movs \tmp, \irqstat, lsl#16 46 movs \tmp, \irqstat, lsl#16
63 addeq \irqnr, \irqnr, #16 47 addeq \irqnr, \irqnr, #16
64 moveq \irqstat, \irqstat, lsr#16 48 moveq \irqstat, \irqstat, lsr#16
@@ -75,9 +59,9 @@
75 addeq \irqnr, \irqnr, #1 59 addeq \irqnr, \irqnr, #1
76 60
77 @@ we have the value 61 @@ we have the value
78 movs \irqnr, \irqnr
79
801001: 621001:
63 adds \irqnr, \irqnr, #IRQ_EINT0
641002:
81 @@ exit here, Z flag unset if IRQ 65 @@ exit here, Z flag unset if IRQ
82 66
83 .endm 67 .endm
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 5e4c8c37bc66..fae2766ff32b 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -236,4 +236,20 @@
236#define S3C24XX_PA_SPI S3C2410_PA_SPI 236#define S3C24XX_PA_SPI S3C2410_PA_SPI
237#endif 237#endif
238 238
239/* deal with the registers that move under the 2412/2413 */
240
241#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
242#ifndef __ASSEMBLY__
243extern void __iomem *s3c24xx_va_gpio2;
244#endif
245#ifdef CONFIG_CPU_S3C2412_ONLY
246#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
247#else
248#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
249#endif
250#else
251#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
252#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
253#endif
254
239#endif /* __ASM_ARCH_MAP_H */ 255#endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 6c92faffe985..a7c61feb8433 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -1,6 +1,6 @@
1/* linux/include/asm/arch-s3c2410/regs-clock.h 1/* linux/include/asm/arch-s3c2410/regs-clock.h
2 * 2 *
3 * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk> 3 * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
@@ -140,5 +140,66 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
140 140
141#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ 141#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
142 142
143#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
144
145#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
146#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
147
148#define S3C2412_PLLCON_OFF (1<<20)
149
150#define S3C2412_CLKDIVN_PDIVN (1<<2)
151#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
152#define S3C2421_CLKDIVN_ARMDIVN (1<<3)
153#define S3C2412_CLKDIVN_USB48DIV (1<<6)
154#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
155#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
156#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
157#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
158#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
159#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
160
161#define S3C2412_CLKCON_WDT (1<<28)
162#define S3C2412_CLKCON_SPI (1<<27)
163#define S3C2412_CLKCON_IIS (1<<26)
164#define S3C2412_CLKCON_IIC (1<<25)
165#define S3C2412_CLKCON_ADC (1<<24)
166#define S3C2412_CLKCON_RTC (1<<23)
167#define S3C2412_CLKCON_GPIO (1<<22)
168#define S3C2412_CLKCON_UART2 (1<<21)
169#define S3C2412_CLKCON_UART1 (1<<20)
170#define S3C2412_CLKCON_UART0 (1<<19)
171#define S3C2412_CLKCON_SDI (1<<18)
172#define S3C2412_CLKCON_PWMT (1<<17)
173#define S3C2412_CLKCON_USBD (1<<16)
174#define S3C2412_CLKCON_CAMCLK (1<<15)
175#define S3C2412_CLKCON_UARTCLK (1<<14)
176/* missing 13 */
177#define S3C2412_CLKCON_USB_HOST48 (1<<12)
178#define S3C2412_CLKCON_USB_DEV48 (1<<11)
179#define S3C2412_CLKCON_HCLKdiv2 (1<<10)
180#define S3C2412_CLKCON_HCLKx2 (1<<9)
181#define S3C2412_CLKCON_SDRAM (1<<8)
182/* missing 7 */
183#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
184#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
185#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
186#define S3C2412_CLKCON_DMA3 (1<<3)
187#define S3C2412_CLKCON_DMA2 (1<<2)
188#define S3C2412_CLKCON_DMA1 (1<<1)
189#define S3C2412_CLKCON_DMA0 (1<<0)
190
191/* clock sourec controls */
192
193#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
194#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
195#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
196#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
197#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
198#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
199#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
200#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
201#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
202
203#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
143 204
144#endif /* __ASM_ARM_REGS_CLOCK */ 205#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index ba13a2c9e547..84aca61cbaa3 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -23,6 +23,9 @@
23#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) 23#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
24#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) 24#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
25 25
26#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
27#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
28
26#define S3C2440_SELECT_DSC0 (0) 29#define S3C2440_SELECT_DSC0 (0)
27#define S3C2440_SELECT_DSC1 (1<<31) 30#define S3C2440_SELECT_DSC1 (1<<31)
28 31
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 5f10334f06bf..6dd17f0f84e0 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -45,7 +45,7 @@
45#define S3C24XX_MISCCR S3C2400_MISCCR 45#define S3C24XX_MISCCR S3C2400_MISCCR
46#else 46#else
47#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) 47#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
48#define S3C24XX_MISCCR S3C2410_MISCCR 48#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
49#endif /* CONFIG_CPU_S3C2400 */ 49#endif /* CONFIG_CPU_S3C2400 */
50 50
51 51
@@ -73,9 +73,15 @@
73#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */ 73#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
74#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ 74#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
75 75
76/* configure GPIO ports A..G */ 76/* register address for the GPIO registers.
77 * S3C24XX_GPIOREG2 is for the second set of registers in the
78 * GPIO which move between s3c2410 and s3c2412 type systems */
77 79
78#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) 80#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
81#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
82
83
84/* configure GPIO ports A..G */
79 85
80/* port A - S3C2410: 22bits, zero in bit X makes pin X output 86/* port A - S3C2410: 22bits, zero in bit X makes pin X output
81 * S3C2400: 18bits, zero in bit X makes pin X output 87 * S3C2400: 18bits, zero in bit X makes pin X output
@@ -953,11 +959,18 @@
953#define S3C2410_GPH10_OUTP (0x01 << 20) 959#define S3C2410_GPH10_OUTP (0x01 << 20)
954#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 960#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
955 961
962/* The S3C2412 and S3C2413 move the GPJ register set to after
963 * GPH, which means all registers after 0x80 are now offset by 0x10
964 * for the 2412/2413 from the 2410/2440/2442
965*/
966
956/* miscellaneous control */ 967/* miscellaneous control */
957#define S3C2400_MISCCR S3C2410_GPIOREG(0x54) 968#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
958#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 969#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
959#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) 970#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
960 971
972#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
973
961/* see clock.h for dclk definitions */ 974/* see clock.h for dclk definitions */
962 975
963/* pullup control on databus */ 976/* pullup control on databus */
@@ -985,6 +998,8 @@
985#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) 998#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
986#define S3C2410_MISCCR_CLK0_MASK (7<<4) 999#define S3C2410_MISCCR_CLK0_MASK (7<<4)
987 1000
1001#define S3C2412_MISCCR_CLK0_RTC (2<<4)
1002
988#define S3C2410_MISCCR_CLK1_MPLL (0<<8) 1003#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
989#define S3C2410_MISCCR_CLK1_UPLL (1<<8) 1004#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
990#define S3C2410_MISCCR_CLK1_FCLK (2<<8) 1005#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
@@ -993,6 +1008,8 @@
993#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) 1008#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
994#define S3C2410_MISCCR_CLK1_MASK (7<<8) 1009#define S3C2410_MISCCR_CLK1_MASK (7<<8)
995 1010
1011#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
1012
996#define S3C2410_MISCCR_USBSUSPND0 (1<<12) 1013#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
997#define S3C2410_MISCCR_USBSUSPND1 (1<<13) 1014#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
998 1015
@@ -1000,7 +1017,7 @@
1000 1017
1001#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) 1018#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
1002#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) 1019#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
1003#define S3C2410_MISCCR_nEN_SCLKE (1<<19) 1020#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
1004#define S3C2410_MISCCR_SDSLEEP (7<<17) 1021#define S3C2410_MISCCR_SDSLEEP (7<<17)
1005 1022
1006/* external interrupt control... */ 1023/* external interrupt control... */
@@ -1017,6 +1034,10 @@
1017#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 1034#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
1018#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 1035#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
1019 1036
1037#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
1038#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
1039#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
1040
1020/* values for S3C2410_EXTINT0/1/2 */ 1041/* values for S3C2410_EXTINT0/1/2 */
1021#define S3C2410_EXTINT_LOWLEV (0x00) 1042#define S3C2410_EXTINT_LOWLEV (0x00)
1022#define S3C2410_EXTINT_HILEV (0x01) 1043#define S3C2410_EXTINT_HILEV (0x01)
@@ -1030,6 +1051,11 @@
1030#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) 1051#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
1031#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) 1052#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
1032 1053
1054#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
1055#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
1056#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
1057#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
1058
1033/* values for interrupt filtering */ 1059/* values for interrupt filtering */
1034#define S3C2410_EINTFLT_PCLK (0x00) 1060#define S3C2410_EINTFLT_PCLK (0x00)
1035#define S3C2410_EINTFLT_EXTCLK (1<<7) 1061#define S3C2410_EINTFLT_EXTCLK (1<<7)
@@ -1039,6 +1065,7 @@
1039 1065
1040/* GSTATUS have miscellaneous information in them 1066/* GSTATUS have miscellaneous information in them
1041 * 1067 *
1068 * These move between s3c2410 and s3c2412 style systems.
1042 */ 1069 */
1043 1070
1044#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) 1071#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
@@ -1047,6 +1074,18 @@
1047#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) 1074#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
1048#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) 1075#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
1049 1076
1077#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
1078#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
1079#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
1080#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
1081#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
1082
1083#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
1084#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
1085#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
1086#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
1087#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
1088
1050#define S3C2410_GSTATUS0_nWAIT (1<<3) 1089#define S3C2410_GSTATUS0_nWAIT (1<<3)
1051#define S3C2410_GSTATUS0_NCON (1<<2) 1090#define S3C2410_GSTATUS0_NCON (1<<2)
1052#define S3C2410_GSTATUS0_RnB (1<<1) 1091#define S3C2410_GSTATUS0_RnB (1<<1)
@@ -1054,6 +1093,7 @@
1054 1093
1055#define S3C2410_GSTATUS1_IDMASK (0xffff0000) 1094#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
1056#define S3C2410_GSTATUS1_2410 (0x32410000) 1095#define S3C2410_GSTATUS1_2410 (0x32410000)
1096#define S3C2410_GSTATUS1_2412 (0x32412001)
1057#define S3C2410_GSTATUS1_2440 (0x32440000) 1097#define S3C2410_GSTATUS1_2440 (0x32440000)
1058#define S3C2410_GSTATUS1_2442 (0x32440aaa) 1098#define S3C2410_GSTATUS1_2442 (0x32440aaa)
1059 1099
@@ -1077,5 +1117,22 @@
1077#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) 1117#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
1078#define S3C2400_OPENCR_OPC_MOSIEN (1<<5) 1118#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
1079 1119
1120/* 2412/2413 sleep configuration registers */
1121
1122#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
1123#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
1124#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
1125#define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
1126#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
1127#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
1128#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
1129
1130/* definitions for each pin bit */
1131#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
1132#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2))
1133#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
1134#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2))
1135#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
1136
1080#endif /* __ASM_ARCH_REGS_GPIO_H */ 1137#endif /* __ASM_ARCH_REGS_GPIO_H */
1081 1138
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
index 3ad2324acc39..18edae50d0b8 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -32,6 +32,11 @@
32#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4) 32#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
33#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8) 33#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
34 34
35#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
36#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
37#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
38#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
39
35#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0) 40#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
36#define S3C2440_GPJ0_INP (0x00 << 0) 41#define S3C2440_GPJ0_INP (0x00 << 0)
37#define S3C2440_GPJ0_OUTP (0x01 << 0) 42#define S3C2440_GPJ0_OUTP (0x01 << 0)
diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
index 24b7292df79e..572fca5d9acf 100644
--- a/include/asm-arm/arch-s3c2410/regs-irq.h
+++ b/include/asm-arm/arch-s3c2410/regs-irq.h
@@ -23,6 +23,7 @@
23 23
24#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) 24#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
25#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) 25#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
26#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
26 27
27#define S3C2410_SRCPND S3C2410_IRQREG(0x000) 28#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
28#define S3C2410_INTMOD S3C2410_IRQREG(0x004) 29#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
@@ -40,5 +41,10 @@
40 41
41#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) 42#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
42#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) 43#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
44#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
45#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
46
47#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
48#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
43 49
44#endif /* ___ASM_ARCH_REGS_IRQ_H */ 50#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
index 83b01254c4ac..93f651ae2967 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -82,6 +82,12 @@
82#define S3C2440_UCON2_DIVMASK (7 << 12) 82#define S3C2440_UCON2_DIVMASK (7 << 12)
83#define S3C2440_UCON_DIVSHIFT (12) 83#define S3C2440_UCON_DIVSHIFT (12)
84 84
85#define S3C2412_UCON_CLKMASK (3<<10)
86#define S3C2412_UCON_UCLK (1<<10)
87#define S3C2412_UCON_USYSCLK (3<<10)
88#define S3C2412_UCON_PCLK (0<<10)
89#define S3C2412_UCON_PCLK2 (2<<10)
90
85#define S3C2410_UCON_UCLK (1<<10) 91#define S3C2410_UCON_UCLK (1<<10)
86#define S3C2410_UCON_SBREAK (1<<4) 92#define S3C2410_UCON_SBREAK (1<<4)
87 93
@@ -124,6 +130,15 @@
124#define S3C2410_UMCOM_AFC (1<<4) 130#define S3C2410_UMCOM_AFC (1<<4)
125#define S3C2410_UMCOM_RTS_LOW (1<<0) 131#define S3C2410_UMCOM_RTS_LOW (1<<0)
126 132
133#define S3C2412_UMCON_AFC_63 (0<<5)
134#define S3C2412_UMCON_AFC_56 (1<<5)
135#define S3C2412_UMCON_AFC_48 (2<<5)
136#define S3C2412_UMCON_AFC_40 (3<<5)
137#define S3C2412_UMCON_AFC_32 (4<<5)
138#define S3C2412_UMCON_AFC_24 (5<<5)
139#define S3C2412_UMCON_AFC_16 (6<<5)
140#define S3C2412_UMCON_AFC_8 (7<<5)
141
127#define S3C2410_UFSTAT_TXFULL (1<<9) 142#define S3C2410_UFSTAT_TXFULL (1<<9)
128#define S3C2410_UFSTAT_RXFULL (1<<8) 143#define S3C2410_UFSTAT_RXFULL (1<<8)
129#define S3C2410_UFSTAT_TXMASK (15<<4) 144#define S3C2410_UFSTAT_TXMASK (15<<4)
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
index 040ccde7a11e..0756269404b1 100644
--- a/include/asm-arm/arch-sa1100/io.h
+++ b/include/asm-arm/arch-sa1100/io.h
@@ -22,6 +22,5 @@ static inline void __iomem *__io(unsigned long addr)
22} 22}
23#define __io(a) __io(a) 23#define __io(a) __io(a)
24#define __mem_pci(a) (a) 24#define __mem_pci(a) (a)
25#define __mem_isa(a) (a)
26 25
27#endif 26#endif
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h
index 47e904cf25c7..c4d01948e00b 100644
--- a/include/asm-arm/arch-versatile/io.h
+++ b/include/asm-arm/arch-versatile/io.h
@@ -28,6 +28,5 @@ static inline void __iomem *__io(unsigned long addr)
28} 28}
29#define __io(a) __io(a) 29#define __io(a) __io(a)
30#define __mem_pci(a) (a) 30#define __mem_pci(a) (a)
31#define __mem_isa(a) (a)
32 31
33#endif 32#endif
diff --git a/include/asm-arm/ucontext.h b/include/asm-arm/ucontext.h
index f853130137cc..9e6f7ca9f5ae 100644
--- a/include/asm-arm/ucontext.h
+++ b/include/asm-arm/ucontext.h
@@ -1,12 +1,89 @@
1#ifndef _ASMARM_UCONTEXT_H 1#ifndef _ASMARM_UCONTEXT_H
2#define _ASMARM_UCONTEXT_H 2#define _ASMARM_UCONTEXT_H
3 3
4#include <asm/fpstate.h>
5
6/*
7 * struct sigcontext only has room for the basic registers, but struct
8 * ucontext now has room for all registers which need to be saved and
9 * restored. Coprocessor registers are stored in uc_regspace. Each
10 * coprocessor's saved state should start with a documented 32-bit magic
11 * number, followed by a 32-bit word giving the coproccesor's saved size.
12 * uc_regspace may be expanded if necessary, although this takes some
13 * coordination with glibc.
14 */
15
4struct ucontext { 16struct ucontext {
5 unsigned long uc_flags; 17 unsigned long uc_flags;
6 struct ucontext *uc_link; 18 struct ucontext *uc_link;
7 stack_t uc_stack; 19 stack_t uc_stack;
8 struct sigcontext uc_mcontext; 20 struct sigcontext uc_mcontext;
9 sigset_t uc_sigmask; /* mask last for extensibility */ 21 sigset_t uc_sigmask;
22 /* Allow for uc_sigmask growth. Glibc uses a 1024-bit sigset_t. */
23 int __unused[32 - (sizeof (sigset_t) / sizeof (int))];
24 /* Last for extensibility. Eight byte aligned because some
25 coprocessors require eight byte alignment. */
26 unsigned long uc_regspace[128] __attribute__((__aligned__(8)));
10}; 27};
11 28
29#ifdef __KERNEL__
30
31/*
32 * Coprocessor save state. The magic values and specific
33 * coprocessor's layouts are part of the userspace ABI. Each one of
34 * these should be a multiple of eight bytes and aligned to eight
35 * bytes, to prevent unpredictable padding in the signal frame.
36 */
37
38#ifdef CONFIG_IWMMXT
39/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */
40#define IWMMXT_MAGIC 0x12ef842a
41#define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8)
42
43struct iwmmxt_sigframe {
44 unsigned long magic;
45 unsigned long size;
46 struct iwmmxt_struct storage;
47} __attribute__((__aligned__(8)));
48#endif /* CONFIG_IWMMXT */
49
50#ifdef CONFIG_VFP
51#if __LINUX_ARM_ARCH__ < 6
52/* For ARM pre-v6, we use fstmiax and fldmiax. This adds one extra
53 * word after the registers, and a word of padding at the end for
54 * alignment. */
55#define VFP_MAGIC 0x56465001
56#define VFP_STORAGE_SIZE 152
57#else
58#define VFP_MAGIC 0x56465002
59#define VFP_STORAGE_SIZE 144
60#endif
61
62struct vfp_sigframe
63{
64 unsigned long magic;
65 unsigned long size;
66 union vfp_state storage;
67};
68#endif /* CONFIG_VFP */
69
70/*
71 * Auxiliary signal frame. This saves stuff like FP state.
72 * The layout of this structure is not part of the user ABI,
73 * because the config options aren't. uc_regspace is really
74 * one of these.
75 */
76struct aux_sigframe {
77#ifdef CONFIG_IWMMXT
78 struct iwmmxt_sigframe iwmmxt;
79#endif
80#if 0 && defined CONFIG_VFP /* Not yet saved. */
81 struct vfp_sigframe vfp;
82#endif
83 /* Something that isn't a valid magic number for any coprocessor. */
84 unsigned long end_magic;
85} __attribute__((__aligned__(8)));
86
87#endif
88
12#endif /* !_ASMARM_UCONTEXT_H */ 89#endif /* !_ASMARM_UCONTEXT_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 16:41:22 -0500