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-rw-r--r--include/asm-arm/arch-at91/at91_mci.h3
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h43
-rw-r--r--include/asm-arm/arch-iop13xx/system.h34
-rw-r--r--include/asm-arm/arch-iop13xx/uncompress.h3
-rw-r--r--include/asm-arm/arch-iop32x/uncompress.h2
-rw-r--r--include/asm-arm/arch-mxc/board-mx31ads.h142
-rw-r--r--include/asm-arm/arch-mxc/common.h20
-rw-r--r--include/asm-arm/arch-mxc/dma.h21
-rw-r--r--include/asm-arm/arch-mxc/entry-macro.S39
-rw-r--r--include/asm-arm/arch-mxc/hardware.h52
-rw-r--r--include/asm-arm/arch-mxc/io.h33
-rw-r--r--include/asm-arm/arch-mxc/irqs.h38
-rw-r--r--include/asm-arm/arch-mxc/memory.h36
-rw-r--r--include/asm-arm/arch-mxc/mx31.h335
-rw-r--r--include/asm-arm/arch-mxc/mxc.h149
-rw-r--r--include/asm-arm/arch-mxc/system.h50
-rw-r--r--include/asm-arm/arch-mxc/timex.h25
-rw-r--r--include/asm-arm/arch-mxc/uncompress.h79
-rw-r--r--include/asm-arm/arch-mxc/vmalloc.h36
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-bbu.h28
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-mem.h6
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-sys.h2
-rw-r--r--include/asm-arm/arch-pxa/pm.h16
-rw-r--r--include/asm-arm/arch-s3c2400/map.h66
-rw-r--r--include/asm-arm/arch-s3c2400/memory.h23
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S84
-rw-r--r--include/asm-arm/arch-s3c2410/map.h85
-rw-r--r--include/asm-arm/arch-s3c2410/memory.h13
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h2
-rw-r--r--include/asm-arm/arch-s3c2410/system.h2
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h145
-rw-r--r--include/asm-arm/arch-sa1100/jornada720.h27
-rw-r--r--include/asm-arm/elf.h3
-rw-r--r--include/asm-arm/floppy.h18
-rw-r--r--include/asm-arm/hardware/iop3xx.h33
-rw-r--r--include/asm-arm/pgtable-nommu.h3
-rw-r--r--include/asm-arm/plat-s3c/debug-macro.S75
-rw-r--r--include/asm-arm/plat-s3c/iic.h (renamed from include/asm-arm/arch-s3c2410/iic.h)0
-rw-r--r--include/asm-arm/plat-s3c/map.h40
-rw-r--r--include/asm-arm/plat-s3c/nand.h (renamed from include/asm-arm/arch-s3c2410/nand.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-ac97.h (renamed from include/asm-arm/arch-s3c2410/regs-ac97.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-adc.h (renamed from include/asm-arm/arch-s3c2410/regs-adc.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-iic.h (renamed from include/asm-arm/arch-s3c2410/regs-iic.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-nand.h (renamed from include/asm-arm/arch-s3c2410/regs-nand.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-rtc.h (renamed from include/asm-arm/arch-s3c2410/regs-rtc.h)0
-rw-r--r--include/asm-arm/plat-s3c/regs-serial.h (renamed from include/asm-arm/arch-s3c2410/regs-serial.h)8
-rw-r--r--include/asm-arm/plat-s3c/regs-timer.h (renamed from include/asm-arm/arch-s3c2410/regs-timer.h)16
-rw-r--r--include/asm-arm/plat-s3c/regs-watchdog.h (renamed from include/asm-arm/arch-s3c2410/regs-watchdog.h)8
-rw-r--r--include/asm-arm/plat-s3c/uncompress.h155
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-iis.h (renamed from include/asm-arm/arch-s3c2410/regs-iis.h)0
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-spi.h (renamed from include/asm-arm/arch-s3c2410/regs-spi.h)0
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-udc.h (renamed from include/asm-arm/arch-s3c2410/regs-udc.h)0
-rw-r--r--include/asm-arm/plat-s3c24xx/udc.h (renamed from include/asm-arm/arch-s3c2410/udc.h)0
-rw-r--r--include/asm-arm/thread_info.h1
-rw-r--r--include/asm-arm/unistd.h1
-rw-r--r--include/asm-arm/vfp.h4
56 files changed, 1673 insertions, 331 deletions
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index 40a9876b661a..c2e11cc374ba 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -26,6 +26,9 @@
26#define AT91_MCI_MR 0x04 /* Mode Register */ 26#define AT91_MCI_MR 0x04 /* Mode Register */
27#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ 27#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
28#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ 28#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
29#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
30#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
31#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
29#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ 32#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
30#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ 33#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
31#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ 34#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index d4e4f828577c..52b7fab7ef60 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void)
19 return id; 19 return id;
20} 20}
21 21
22/* WDTCR CP6 R7 Page 9 */
23static inline u32 read_wdtcr(void)
24{
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
27 return val;
28}
29static inline void write_wdtcr(u32 val)
30{
31 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
32}
33
34/* WDTSR CP6 R8 Page 9 */
35static inline u32 read_wdtsr(void)
36{
37 u32 val;
38 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
39 return val;
40}
41static inline void write_wdtsr(u32 val)
42{
43 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
44}
45
46/* RCSR - Reset Cause Status Register */
47static inline u32 read_rcsr(void)
48{
49 u32 val;
50 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
51 return val;
52}
53
54extern unsigned long get_iop_tick_rate(void);
22#endif 55#endif
23 56
24/* 57/*
@@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void)
480#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) 513#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
481 514
482#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) 515#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
516
517/* Watchdog timer definitions */
518#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
519#define IOP_WDTCR_EN 0xe1e1e1e1
520#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
521#define IOP_WDTCR_DIS 0xf1f1f1f1
522#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
523#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
524#define IOP13XX_WDTCR_IB_RESET (1 << 0)
525
483#endif /* _IOP13XX_HW_H_ */ 526#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index 127827058e1f..8575af8db78c 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -13,43 +13,13 @@ static inline void arch_idle(void)
13 cpu_do_idle(); 13 cpu_do_idle();
14} 14}
15 15
16/* WDTCR CP6 R7 Page 9 */
17static inline u32 read_wdtcr(void)
18{
19 u32 val;
20 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
21 return val;
22}
23static inline void write_wdtcr(u32 val)
24{
25 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
26}
27
28/* WDTSR CP6 R8 Page 9 */
29static inline u32 read_wdtsr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtsr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
38}
39
40#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
41#define IOP13XX_WDTCR_EN 0xe1e1e1e1
42#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
43#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
44#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
45#define IOP13XX_WDTCR_IB_RESET (1 << 0)
46static inline void arch_reset(char mode) 16static inline void arch_reset(char mode)
47{ 17{
48 /* 18 /*
49 * Reset the internal bus (warning both cores are reset) 19 * Reset the internal bus (warning both cores are reset)
50 */ 20 */
51 write_wdtcr(IOP13XX_WDTCR_EN_ARM); 21 write_wdtcr(IOP_WDTCR_EN_ARM);
52 write_wdtcr(IOP13XX_WDTCR_EN); 22 write_wdtcr(IOP_WDTCR_EN);
53 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); 23 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
54 write_wdtcr(0x1000); 24 write_wdtcr(0x1000);
55 25
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
index b9525d59b7ad..dd9c2934190e 100644
--- a/include/asm-arm/arch-iop13xx/uncompress.h
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -1,7 +1,6 @@
1#include <asm/types.h> 1#include <asm/types.h>
2#include <linux/serial_reg.h> 2#include <linux/serial_reg.h>
3#include <asm/hardware.h> 3#include <asm/hardware.h>
4#include <asm/processor.h>
5 4
6#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) 5#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
7#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) 6#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
@@ -9,7 +8,7 @@
9static inline void putc(char c) 8static inline void putc(char c)
10{ 9{
11 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) 10 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
12 cpu_relax(); 11 barrier();
13 UART_BASE[UART_TX] = c; 12 UART_BASE[UART_TX] = c;
14} 13}
15 14
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
index e64f52bf2bce..070f15818fe7 100644
--- a/include/asm-arm/arch-iop32x/uncompress.h
+++ b/include/asm-arm/arch-iop32x/uncompress.h
@@ -26,7 +26,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
26{ 26{
27 if (machine_is_iq80321()) 27 if (machine_is_iq80321())
28 uart_base = (volatile u8 *)IQ80321_UART; 28 uart_base = (volatile u8 *)IQ80321_UART;
29 else if (machine_is_iq31244()) 29 else if (machine_is_iq31244() || machine_is_em7210())
30 uart_base = (volatile u8 *)IQ31244_UART; 30 uart_base = (volatile u8 *)IQ31244_UART;
31 else 31 else
32 uart_base = (volatile u8 *)0xfe800000; 32 uart_base = (volatile u8 *)0xfe800000;
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
new file mode 100644
index 000000000000..be29b83ad4ae
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -0,0 +1,142 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14/*!
15 * @name PBC Controller parameters
16 */
17/*! @{ */
18/*!
19 * Base address of PBC controller
20 */
21#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
22/* Offsets for the PBC Controller register */
23/*!
24 * PBC Board status register offset
25 */
26#define PBC_BSTAT 0x000002
27/*!
28 * PBC Board control register 1 set address.
29 */
30#define PBC_BCTRL1_SET 0x000004
31/*!
32 * PBC Board control register 1 clear address.
33 */
34#define PBC_BCTRL1_CLEAR 0x000006
35/*!
36 * PBC Board control register 2 set address.
37 */
38#define PBC_BCTRL2_SET 0x000008
39/*!
40 * PBC Board control register 2 clear address.
41 */
42#define PBC_BCTRL2_CLEAR 0x00000A
43/*!
44 * PBC Board control register 3 set address.
45 */
46#define PBC_BCTRL3_SET 0x00000C
47/*!
48 * PBC Board control register 3 clear address.
49 */
50#define PBC_BCTRL3_CLEAR 0x00000E
51/*!
52 * PBC Board control register 4 set address.
53 */
54#define PBC_BCTRL4_SET 0x000010
55/*!
56 * PBC Board control register 4 clear address.
57 */
58#define PBC_BCTRL4_CLEAR 0x000012
59/*!
60 * PBC Board status register 1.
61 */
62#define PBC_BSTAT1 0x000014
63/*!
64 * PBC Board interrupt status register.
65 */
66#define PBC_INTSTATUS 0x000016
67/*!
68 * PBC Board interrupt current status register.
69 */
70#define PBC_INTCURR_STATUS 0x000018
71/*!
72 * PBC Interrupt mask register set address.
73 */
74#define PBC_INTMASK_SET 0x00001A
75/*!
76 * PBC Interrupt mask register clear address.
77 */
78#define PBC_INTMASK_CLEAR 0x00001C
79
80/*!
81 * External UART A.
82 */
83#define PBC_SC16C652_UARTA 0x010000
84/*!
85 * External UART B.
86 */
87#define PBC_SC16C652_UARTB 0x010010
88/*!
89 * Ethernet Controller IO base address.
90 */
91#define PBC_CS8900A_IOBASE 0x020000
92/*!
93 * Ethernet Controller Memory base address.
94 */
95#define PBC_CS8900A_MEMBASE 0x021000
96/*!
97 * Ethernet Controller DMA base address.
98 */
99#define PBC_CS8900A_DMABASE 0x022000
100/*!
101 * External chip select 0.
102 */
103#define PBC_XCS0 0x040000
104/*!
105 * LCD Display enable.
106 */
107#define PBC_LCD_EN_B 0x060000
108/*!
109 * Code test debug enable.
110 */
111#define PBC_CODE_B 0x070000
112/*!
113 * PSRAM memory select.
114 */
115#define PBC_PSRAM_B 0x5000000
116
117#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
118#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
119#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
120#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
121#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
122
123#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
124#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
125#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
126#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
127#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
128#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
129#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
130#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
131#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
132#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
133#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
134#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
135#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
136#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
137#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
138#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
139
140#define MXC_MAX_EXP_IO_LINES 16
141
142#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
new file mode 100644
index 000000000000..23b4350edbd6
--- /dev/null
+++ b/include/asm-arm/arch-mxc/common.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
14struct sys_timer;
15
16extern void mxc_map_io(void);
17extern void mxc_init_irq(void);
18extern struct sys_timer mxc_timer;
19
20#endif
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
new file mode 100644
index 000000000000..65e639d51d2b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_DMA_H__
12#define __ASM_ARCH_MXC_DMA_H__
13
14/*!
15 * @file dma.h
16 * @brief This file contains Unified DMA API for all MXC platforms.
17 * The API is platform independent.
18 *
19 * @ingroup SDMA
20 */
21#endif
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S
new file mode 100644
index 000000000000..b542433afb1b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 @ this macro disables fast irq (not implemented)
13 .macro disable_fiq
14 .endm
15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
22 @ this macro checks which interrupt occured
23 @ and returns its number in irqnr
24 @ and returns if an interrupt occured in irqstat
25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26 ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
27 @ Load offset & priority of the highest priority
28 @ interrupt pending from AVIC_NIVECSR
29 ldr \irqstat, [\base, #0x40]
30 @ Shift to get the decoded IRQ number, using ASR so
31 @ 'no interrupt pending' becomes 0xffffffff
32 mov \irqnr, \irqstat, asr #16
33 @ set zero flag if IRQ + 1 == 0
34 adds \tmp, \irqnr, #1
35 .endm
36
37 @ irq priority table (not used)
38 .macro irq_prio_table
39 .endm
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
new file mode 100644
index 000000000000..3c09b92fef0d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*!
12 * @file hardware.h
13 * @brief This file contains the hardware definitions of the board.
14 *
15 * @ingroup System
16 */
17#ifndef __ASM_ARCH_MXC_HARDWARE_H__
18#define __ASM_ARCH_MXC_HARDWARE_H__
19
20#include <asm/sizes.h>
21
22#include <asm/arch/mx31.h>
23
24#include <asm/arch/mxc.h>
25
26#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
27
28/*
29 * ---------------------------------------------------------------------------
30 * Board specific defines
31 * ---------------------------------------------------------------------------
32 */
33#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
34
35#include <asm/arch/board-mx31ads.h>
36
37#ifndef MXC_MAX_EXP_IO_LINES
38#define MXC_MAX_EXP_IO_LINES 0
39#endif
40
41#define MXC_MAX_VIRTUAL_INTS 16
42#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
43#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
44#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
45#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
46
47#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \
48 MXC_MAX_GPIO_LINES + \
49 MXC_MAX_EXP_IO_LINES + \
50 MXC_MAX_VIRTUAL_INTS)
51
52#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
new file mode 100644
index 000000000000..cf6c83a4b9f7
--- /dev/null
+++ b/include/asm-arm/arch-mxc/io.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*!
12 * @file io.h
13 * @brief This file contains some memory mapping macros.
14 * @note There is no real ISA or PCI buses. But have to define these macros
15 * for some drivers to compile.
16 *
17 * @ingroup System
18 */
19
20#ifndef __ASM_ARCH_MXC_IO_H__
21#define __ASM_ARCH_MXC_IO_H__
22
23/*! Allow IO space to be anywhere in the memory */
24#define IO_SPACE_LIMIT 0xffffffff
25
26/*!
27 * io address mapping macro
28 */
29#define __io(a) ((void __iomem *)(a))
30
31#define __mem_pci(a) (a)
32
33#endif
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
new file mode 100644
index 000000000000..e4686c6bc4bf
--- /dev/null
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_IRQS_H__
12#define __ASM_ARCH_MXC_IRQS_H__
13
14#include <asm/hardware.h>
15
16/*!
17 * @file irqs.h
18 * @brief This file defines the number of normal interrupts and fast interrupts
19 *
20 * @ingroup Interrupt
21 */
22
23#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
24
25#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
26#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
27
28/*!
29 * Number of normal interrupts
30 */
31#define NR_IRQS MXC_MAX_INTS
32
33/*!
34 * Number of fast interrupts
35 */
36#define NR_FIQS MXC_MAX_INTS
37
38#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
new file mode 100644
index 000000000000..c89aac83a407
--- /dev/null
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MEMORY_H__
12#define __ASM_ARCH_MXC_MEMORY_H__
13
14#include <asm/hardware.h>
15
16/*!
17 * @file memory.h
18 * @brief This file contains macros needed by the Linux kernel and drivers.
19 *
20 * @ingroup Memory
21 */
22
23/*!
24 * Virtual view <-> DMA view memory address translations
25 * This macro is used to translate the virtual address to an address
26 * suitable to be passed to set_dma_addr()
27 */
28#define __virt_to_bus(a) __virt_to_phys(a)
29
30/*!
31 * Used to convert an address for DMA operations to an address that the
32 * kernel can use.
33 */
34#define __bus_to_virt(a) __phys_to_virt(a)
35
36#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
new file mode 100644
index 000000000000..85c49c9e5d15
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -0,0 +1,335 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*!
19 * defines the hardware clock tick rate
20 */
21#define CLOCK_TICK_RATE 16625000
22
23/*
24 * MX31 memory map:
25 *
26 * Virt Phys Size What
27 * ---------------------------------------------------------------------------
28 * F8000000 1FFC0000 16K IRAM
29 * F9000000 30000000 256M L2CC
30 * FC000000 43F00000 1M AIPS 1
31 * FC100000 50000000 1M SPBA
32 * FC200000 53F00000 1M AIPS 2
33 * FC500000 60000000 128M ROMPATCH
34 * FC400000 68000000 128M AVIC
35 * 70000000 256M IPU (MAX M2)
36 * 80000000 256M CSD0 SDRAM/DDR
37 * 90000000 256M CSD1 SDRAM/DDR
38 * A0000000 128M CS0 Flash
39 * A8000000 128M CS1 Flash
40 * B0000000 32M CS2
41 * B2000000 32M CS3
42 * F4000000 B4000000 32M CS4
43 * B6000000 32M CS5
44 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
45 * C0000000 64M PCMCIA/CF
46 */
47
48#define CS0_BASE_ADDR 0xA0000000
49#define CS1_BASE_ADDR 0xA8000000
50#define CS2_BASE_ADDR 0xB0000000
51#define CS3_BASE_ADDR 0xB2000000
52
53#define CS4_BASE_ADDR 0xB4000000
54#define CS4_BASE_ADDR_VIRT 0xF4000000
55#define CS4_SIZE SZ_32M
56
57#define CS5_BASE_ADDR 0xB6000000
58#define PCMCIA_MEM_BASE_ADDR 0xBC000000
59
60/*
61 * IRAM
62 */
63#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
64#define IRAM_BASE_ADDR_VIRT 0xF8000000
65#define IRAM_SIZE SZ_16K
66
67/*
68 * L2CC
69 */
70#define L2CC_BASE_ADDR 0x30000000
71#define L2CC_BASE_ADDR_VIRT 0xF9000000
72#define L2CC_SIZE SZ_1M
73
74/*
75 * AIPS 1
76 */
77#define AIPS1_BASE_ADDR 0x43F00000
78#define AIPS1_BASE_ADDR_VIRT 0xFC000000
79#define AIPS1_SIZE SZ_1M
80
81#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
82#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
83#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
84#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
85#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
86#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
87#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
88#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
89#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
90#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
91#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
92#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
93#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
94#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
95#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
96#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
97#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
98#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
99#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
100#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
101#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
102#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
103
104/*
105 * SPBA global module enabled #0
106 */
107#define SPBA0_BASE_ADDR 0x50000000
108#define SPBA0_BASE_ADDR_VIRT 0xFC100000
109#define SPBA0_SIZE SZ_1M
110
111#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
112#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
113#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
114#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
115#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
116#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
117#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
118#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
119#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
120#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
121#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
122
123/*
124 * AIPS 2
125 */
126#define AIPS2_BASE_ADDR 0x53F00000
127#define AIPS2_BASE_ADDR_VIRT 0xFC200000
128#define AIPS2_SIZE SZ_1M
129#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
130#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
131#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
132#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
133#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
134#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
135#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
136#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
137#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
138#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
139#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
140#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
141#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
142#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
143#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
144#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
145#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
146#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
147#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
148#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
149#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
150
151/*
152 * ROMP and AVIC
153 */
154#define ROMP_BASE_ADDR 0x60000000
155#define ROMP_BASE_ADDR_VIRT 0xFC500000
156#define ROMP_SIZE SZ_1M
157
158#define AVIC_BASE_ADDR 0x68000000
159#define AVIC_BASE_ADDR_VIRT 0xFC400000
160#define AVIC_SIZE SZ_1M
161
162/*
163 * NAND, SDRAM, WEIM, M3IF, EMI controllers
164 */
165#define X_MEMC_BASE_ADDR 0xB8000000
166#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
167#define X_MEMC_SIZE SZ_64K
168
169#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
170#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
171#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
172#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
173#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
174#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
175
176/*
177 * Memory regions and CS
178 */
179#define IPU_MEM_BASE_ADDR 0x70000000
180#define CSD0_BASE_ADDR 0x80000000
181#define CSD1_BASE_ADDR 0x90000000
182#define CS0_BASE_ADDR 0xA0000000
183#define CS1_BASE_ADDR 0xA8000000
184#define CS2_BASE_ADDR 0xB0000000
185#define CS3_BASE_ADDR 0xB2000000
186
187#define CS4_BASE_ADDR 0xB4000000
188#define CS4_BASE_ADDR_VIRT 0xF4000000
189#define CS4_SIZE SZ_32M
190
191#define CS5_BASE_ADDR 0xB6000000
192#define PCMCIA_MEM_BASE_ADDR 0xBC000000
193
194/*!
195 * This macro defines the physical to virtual address mapping for all the
196 * peripheral modules. It is used by passing in the physical address as x
197 * and returning the virtual address. If the physical address is not mapped,
198 * it returns 0xDEADBEEF
199 */
200#define IO_ADDRESS(x) \
201 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
202 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
203 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
204 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
205 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
206 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
207 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
208 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
209 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
210 0xDEADBEEF)
211
212/*
213 * define the address mapping macros: in physical address order
214 */
215
216#define IRAM_IO_ADDRESS(x) \
217 (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
218
219#define L2CC_IO_ADDRESS(x) \
220 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
221
222#define AIPS1_IO_ADDRESS(x) \
223 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
224
225#define SPBA0_IO_ADDRESS(x) \
226 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
227
228#define AIPS2_IO_ADDRESS(x) \
229 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
230
231#define ROMP_IO_ADDRESS(x) \
232 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
233
234#define AVIC_IO_ADDRESS(x) \
235 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
236
237#define CS4_IO_ADDRESS(x) \
238 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
239
240#define X_MEMC_IO_ADDRESS(x) \
241 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
242
243#define PCMCIA_IO_ADDRESS(x) \
244 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
245
246/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
247#define PHYS_OFFSET CSD0_BASE_ADDR
248
249/*
250 * Interrupt numbers
251 */
252#define MXC_INT_PEN_ADS7843 0
253#define MXC_INT_RESV1 1
254#define MXC_INT_CS8900A 2
255#define MXC_INT_I2C3 3
256#define MXC_INT_I2C2 4
257#define MXC_INT_MPEG4_ENCODER 5
258#define MXC_INT_RTIC 6
259#define MXC_INT_FIRI 7
260#define MXC_INT_MMC_SDHC2 8
261#define MXC_INT_MMC_SDHC1 9
262#define MXC_INT_I2C 10
263#define MXC_INT_SSI2 11
264#define MXC_INT_SSI1 12
265#define MXC_INT_CSPI2 13
266#define MXC_INT_CSPI1 14
267#define MXC_INT_ATA 15
268#define MXC_INT_MBX 16
269#define MXC_INT_CSPI3 17
270#define MXC_INT_UART3 18
271#define MXC_INT_IIM 19
272#define MXC_INT_SIM2 20
273#define MXC_INT_SIM1 21
274#define MXC_INT_RNGA 22
275#define MXC_INT_EVTMON 23
276#define MXC_INT_KPP 24
277#define MXC_INT_RTC 25
278#define MXC_INT_PWM 26
279#define MXC_INT_EPIT2 27
280#define MXC_INT_EPIT1 28
281#define MXC_INT_GPT 29
282#define MXC_INT_RESV30 30
283#define MXC_INT_RESV31 31
284#define MXC_INT_UART2 32
285#define MXC_INT_NANDFC 33
286#define MXC_INT_SDMA 34
287#define MXC_INT_USB1 35
288#define MXC_INT_USB2 36
289#define MXC_INT_USB3 37
290#define MXC_INT_USB4 38
291#define MXC_INT_MSHC1 39
292#define MXC_INT_MSHC2 40
293#define MXC_INT_IPU_ERR 41
294#define MXC_INT_IPU_SYN 42
295#define MXC_INT_RESV43 43
296#define MXC_INT_RESV44 44
297#define MXC_INT_UART1 45
298#define MXC_INT_UART4 46
299#define MXC_INT_UART5 47
300#define MXC_INT_ECT 48
301#define MXC_INT_SCC_SCM 49
302#define MXC_INT_SCC_SMN 50
303#define MXC_INT_GPIO2 51
304#define MXC_INT_GPIO1 52
305#define MXC_INT_CCM 53
306#define MXC_INT_PCMCIA 54
307#define MXC_INT_WDOG 55
308#define MXC_INT_GPIO3 56
309#define MXC_INT_RESV57 57
310#define MXC_INT_EXT_POWER 58
311#define MXC_INT_EXT_TEMPER 59
312#define MXC_INT_EXT_SENSOR60 60
313#define MXC_INT_EXT_SENSOR61 61
314#define MXC_INT_EXT_WDOG 62
315#define MXC_INT_EXT_TV 63
316
317#define MXC_MAX_INT_LINES 64
318
319#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
320
321/*!
322 * Number of GPIO port as defined in the IC Spec
323 */
324#define GPIO_PORT_NUM 3
325/*!
326 * Number of GPIO pins per port
327 */
328#define GPIO_NUM_PIN 32
329
330#define PROD_SIGNATURE 0x1 /* For MX31 */
331
332#define SYSTEM_REV_MIN CHIP_REV_1_0
333#define SYSTEM_REV_NUM 3
334
335#endif /* __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
new file mode 100644
index 000000000000..0837f1f9ca31
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -0,0 +1,149 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_H__
12#define __ASM_ARCH_MXC_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 *****************************************
20 * GPT Register definitions *
21 *****************************************
22 */
23#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
24#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
25#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
26#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
27#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
28#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
29#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
30#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
31#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
32#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
33
34/*!
35 * GPT Control register bit definitions
36 */
37#define GPTCR_FO3 (1 << 31)
38#define GPTCR_FO2 (1 << 30)
39#define GPTCR_FO1 (1 << 29)
40
41#define GPTCR_OM3_SHIFT 26
42#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
43#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
44#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
45#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
46#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
47#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
48
49#define GPTCR_OM2_SHIFT 23
50#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
51#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
52#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
53#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
54#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
55#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
56
57#define GPTCR_OM1_SHIFT 20
58#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
59#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
60#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
61#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
62#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
63#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
64
65#define GPTCR_IM2_SHIFT 18
66#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
67#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
68#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
69#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
70#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
71
72#define GPTCR_IM1_SHIFT 16
73#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
74#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
75#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
76#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
77#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
78
79#define GPTCR_SWR (1 << 15)
80#define GPTCR_FRR (1 << 9)
81
82#define GPTCR_CLKSRC_SHIFT 6
83#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
84#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
85#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
86#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
87#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
88
89#define GPTCR_STOPEN (1 << 5)
90#define GPTCR_DOZEN (1 << 4)
91#define GPTCR_WAITEN (1 << 3)
92#define GPTCR_DBGEN (1 << 2)
93
94#define GPTCR_ENMOD (1 << 1)
95#define GPTCR_ENABLE (1 << 0)
96
97#define GPTSR_OF1 (1 << 0)
98#define GPTSR_OF2 (1 << 1)
99#define GPTSR_OF3 (1 << 2)
100#define GPTSR_IF1 (1 << 3)
101#define GPTSR_IF2 (1 << 4)
102#define GPTSR_ROV (1 << 5)
103
104#define GPTIR_OF1IE GPTSR_OF1
105#define GPTIR_OF2IE GPTSR_OF2
106#define GPTIR_OF3IE GPTSR_OF3
107#define GPTIR_IF1IE GPTSR_IF1
108#define GPTIR_IF2IE GPTSR_IF2
109#define GPTIR_ROVIE GPTSR_ROV
110
111/*
112 *****************************************
113 * AVIC Registers *
114 *****************************************
115 */
116#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
117#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
118#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
119#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
120#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
121#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
122#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
123#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
124#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
125#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
126#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
127#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
128#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
129#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
130#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
131#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
132#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
133#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
134#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
135#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
136#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
137#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
138#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
139#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
140#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
141#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
142#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
143
144#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
145#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
146#define IIM_PROD_REV_SH 3
147#define IIM_PROD_REV_LEN 5
148
149#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
new file mode 100644
index 000000000000..109956b41aca
--- /dev/null
+++ b/include/asm-arm/arch-mxc/system.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_MXC_SYSTEM_H__
22#define __ASM_ARCH_MXC_SYSTEM_H__
23
24/*!
25 * @file system.h
26 * @brief This file contains idle and reset functions.
27 *
28 * @ingroup System
29 */
30
31/*!
32 * This function puts the CPU into idle mode. It is called by default_idle()
33 * in process.c file.
34 */
35static inline void arch_idle(void)
36{
37 cpu_do_idle();
38}
39
40/*
41 * This function resets the system. It is called by machine_restart().
42 *
43 * @param mode indicates different kinds of resets
44 */
45static inline void arch_reset(char mode)
46{
47 cpu_reset(0);
48}
49
50#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h
new file mode 100644
index 000000000000..59019fa58f82
--- /dev/null
+++ b/include/asm-arm/arch-mxc/timex.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARCH_MXC_TIMEX_H__
21#define __ASM_ARCH_MXC_TIMEX_H__
22
23#include <asm/hardware.h> /* for CLOCK_TICK_RATE */
24
25#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
new file mode 100644
index 000000000000..ec5787d0e78c
--- /dev/null
+++ b/include/asm-arm/arch-mxc/uncompress.h
@@ -0,0 +1,79 @@
1/*
2 * include/asm-arm/arch-mxc/uncompress.h
3 *
4 *
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) Shane Nay (shane@minirl.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
24#define __ASM_ARCH_MXC_UNCOMPRESS_H__
25
26#define __MXC_BOOT_UNCOMPRESS
27
28#include <asm/hardware.h>
29#include <asm/processor.h>
30
31#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
32
33#define USR2 0x98
34#define USR2_TXFE (1<<14)
35#define TXR 0x40
36#define UCR1 0x80
37#define UCR1_UARTEN 1
38
39/*
40 * The following code assumes the serial port has already been
41 * initialized by the bootloader. We search for the first enabled
42 * port in the most probable order. If you didn't setup a port in
43 * your bootloader then nothing will appear (which might be desired).
44 *
45 * This does not append a newline
46 */
47
48static void putc(int ch)
49{
50 static unsigned long serial_port = 0;
51
52 if (unlikely(serial_port == 0)) {
53 do {
54 serial_port = UART1_BASE_ADDR;
55 if (UART(UCR1) & UCR1_UARTEN)
56 break;
57 serial_port = UART2_BASE_ADDR;
58 if (UART(UCR1) & UCR1_UARTEN)
59 break;
60 return;
61 } while (0);
62 }
63
64 while (!(UART(USR2) & USR2_TXFE))
65 cpu_relax();
66
67 UART(TXR) = ch;
68}
69
70#define flush() do { } while (0)
71
72/*
73 * nothing to do
74 */
75#define arch_decomp_setup()
76
77#define arch_decomp_wdog()
78
79#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
new file mode 100644
index 000000000000..83a73da895eb
--- /dev/null
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright (C) 2000 Russell King.
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARCH_MXC_VMALLOC_H__
21#define __ASM_ARCH_MXC_VMALLOC_H__
22
23/*!
24 * @file vmalloc.h
25 *
26 * @brief This file contains platform specific macros for vmalloc.
27 *
28 * @ingroup System
29 */
30
31/*!
32 * vmalloc ending address
33 */
34#define VMALLOC_END 0xF4000000
35
36#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h
index e26269546240..7ee194dc6354 100644
--- a/include/asm-arm/arch-ns9xxx/regs-bbu.h
+++ b/include/asm-arm/arch-ns9xxx/regs-bbu.h
@@ -15,7 +15,31 @@
15 15
16/* BBus Utility */ 16/* BBus Utility */
17 17
18/* GPIO Configuration Register */ 18/* GPIO Configuration Registers block 1 */
19#define BBU_GC(x) __REG2(0x9060000c, (x)) 19/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
20 * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register
21 * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
22#define BBU_GCONFb1(x) __REG2(0x90600010, (x))
23#define BBU_GCONFb2(x) __REG2(0x90600100, (x))
24
25#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2))
26#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
27#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1)
28#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2))
29#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0)
30#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1)
31#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
32#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0)
33#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1)
34#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2)
35#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3)
36
37#define BBU_GCTRL1 __REG(0x90600030)
38#define BBU_GCTRL2 __REG(0x90600034)
39#define BBU_GCTRL3 __REG(0x90600120)
40
41#define BBU_GSTAT1 __REG(0x90600040)
42#define BBU_GSTAT2 __REG(0x90600044)
43#define BBU_GSTAT3 __REG(0x90600130)
20 44
21#endif /* ifndef __ASM_ARCH_REGSBBU_H */ 45#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h b/include/asm-arm/arch-ns9xxx/regs-mem.h
index 8ed8448767b9..fb455a0ed845 100644
--- a/include/asm-arm/arch-ns9xxx/regs-mem.h
+++ b/include/asm-arm/arch-ns9xxx/regs-mem.h
@@ -79,9 +79,9 @@
79#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3) 79#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
80 80
81/* Static Memory Configuration Register x: Write protect */ 81/* Static Memory Configuration Register x: Write protect */
82#define MEM_SMC_WSMC __REGBIT(20) 82#define MEM_SMC_PSMC __REGBIT(20)
83#define MEM_SMC_WSMC_OFF __REGVAL(MEM_SMC_WSMC, 0) 83#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0)
84#define MEM_SMC_WSMC_ON __REGVAL(MEM_SMC_WSMC, 1) 84#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1)
85 85
86/* Static Memory Configuration Register x: Buffer enable */ 86/* Static Memory Configuration Register x: Buffer enable */
87#define MEM_SMC_BSMC __REGBIT(19) 87#define MEM_SMC_BSMC __REGBIT(19)
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys.h
index a42546aeb92a..749262f86204 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys.h
@@ -64,7 +64,7 @@
64 64
65/* Timer x Control register: Timer enable */ 65/* Timer x Control register: Timer enable */
66#define SYS_TCx_TEN __REGBIT(15) 66#define SYS_TCx_TEN __REGBIT(15)
67#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 1) 67#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0)
68#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1) 68#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1)
69 69
70/* Timer x Control register: CPU debug mode */ 70/* Timer x Control register: CPU debug mode */
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
index 52243a62c4e7..6903db7fae15 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -7,5 +7,19 @@
7 * 7 *
8 */ 8 */
9 9
10extern int pxa_pm_prepare(suspend_state_t state); 10struct pxa_cpu_pm_fns {
11 int save_size;
12 void (*save)(unsigned long *);
13 void (*restore)(unsigned long *);
14 int (*valid)(suspend_state_t state);
15 void (*enter)(suspend_state_t state);
16};
17
18extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
19
20/* sleep.S */
21extern void pxa25x_cpu_suspend(unsigned int);
22extern void pxa27x_cpu_suspend(unsigned int);
23extern void pxa_cpu_resume(void);
24
11extern int pxa_pm_enter(suspend_state_t state); 25extern int pxa_pm_enter(suspend_state_t state);
diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h
new file mode 100644
index 000000000000..1184d907b31e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/map.h
@@ -0,0 +1,66 @@
1/* linux/include/asm-arm/arch-s3c2400/map.h
2 *
3 * Copyright 2003,2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Copyright 2003, Lucas Correia Villa Real
8 *
9 * S3C2400 - Memory map definitions
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#define S3C2400_PA_MEMCTRL (0x14000000)
17#define S3C2400_PA_USBHOST (0x14200000)
18#define S3C2400_PA_IRQ (0x14400000)
19#define S3C2400_PA_DMA (0x14600000)
20#define S3C2400_PA_CLKPWR (0x14800000)
21#define S3C2400_PA_LCD (0x14A00000)
22#define S3C2400_PA_UART (0x15000000)
23#define S3C2400_PA_TIMER (0x15100000)
24#define S3C2400_PA_USBDEV (0x15200140)
25#define S3C2400_PA_WATCHDOG (0x15300000)
26#define S3C2400_PA_IIC (0x15400000)
27#define S3C2400_PA_IIS (0x15508000)
28#define S3C2400_PA_GPIO (0x15600000)
29#define S3C2400_PA_RTC (0x15700040)
30#define S3C2400_PA_ADC (0x15800000)
31#define S3C2400_PA_SPI (0x15900000)
32
33#define S3C2400_PA_MMC (0x15A00000)
34#define S3C2400_SZ_MMC SZ_1M
35
36/* physical addresses of all the chip-select areas */
37
38#define S3C2400_CS0 (0x00000000)
39#define S3C2400_CS1 (0x02000000)
40#define S3C2400_CS2 (0x04000000)
41#define S3C2400_CS3 (0x06000000)
42#define S3C2400_CS4 (0x08000000)
43#define S3C2400_CS5 (0x0A000000)
44#define S3C2400_CS6 (0x0C000000)
45#define S3C2400_CS7 (0x0E000000)
46
47#define S3C2400_SDRAM_PA (S3C2400_CS6)
48
49/* Use a single interface for common resources between S3C24XX cpus */
50
51#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
52#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
53#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
54#define S3C24XX_PA_DMA S3C2400_PA_DMA
55#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
56#define S3C24XX_PA_LCD S3C2400_PA_LCD
57#define S3C24XX_PA_UART S3C2400_PA_UART
58#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
59#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
60#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
61#define S3C24XX_PA_IIC S3C2400_PA_IIC
62#define S3C24XX_PA_IIS S3C2400_PA_IIS
63#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
64#define S3C24XX_PA_RTC S3C2400_PA_RTC
65#define S3C24XX_PA_ADC S3C2400_PA_ADC
66#define S3C24XX_PA_SPI S3C2400_PA_SPI
diff --git a/include/asm-arm/arch-s3c2400/memory.h b/include/asm-arm/arch-s3c2400/memory.h
new file mode 100644
index 000000000000..fb0381dde704
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/memory.h
@@ -0,0 +1,23 @@
1/* linux/include/asm-arm/arch-s3c2400/memory.h
2 * from linux/include/asm-arm/arch-rpc/memory.h
3 *
4 * Copyright 2007 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * Copyright (C) 1996,1997,1998 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_MEMORY_H
16#define __ASM_ARCH_MEMORY_H
17
18#define PHYS_OFFSET UL(0x0C000000)
19
20#define __virt_to_bus(x) __virt_to_phys(x)
21#define __bus_to_virt(x) __phys_to_virt(x)
22
23#endif
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 93064860e0e5..9c8cd9abb82b 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -13,32 +13,23 @@
13*/ 13*/
14 14
15#include <asm/arch/map.h> 15#include <asm/arch/map.h>
16#include <asm/arch/regs-serial.h>
17#include <asm/arch/regs-gpio.h> 16#include <asm/arch/regs-gpio.h>
17#include <asm/plat-s3c/regs-serial.h>
18 18
19#define S3C2410_UART1_OFF (0x4000) 19#define S3C2410_UART1_OFF (0x4000)
20#define SHIFT_2440TXF (14-9) 20#define SHIFT_2440TXF (14-9)
21 21
22 .macro addruart, rx 22 .macro addruart, rx
23 mrc p15, 0, \rx, c1, c0 23 mrc p15, 0, \rx, c1, c0
24 tst \rx, #1 24 tst \rx, #1
25 ldreq \rx, = S3C24XX_PA_UART 25 ldreq \rx, = S3C24XX_PA_UART
26 ldrne \rx, = S3C24XX_VA_UART 26 ldrne \rx, = S3C24XX_VA_UART
27#if CONFIG_DEBUG_S3C2410_UART != 0 27#if CONFIG_DEBUG_S3C_UART != 0
28 add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART) 28 add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
29#endif 29#endif
30 .endm 30 .endm
31 31
32 .macro senduart,rd,rx 32 .macro fifo_full_s3c24xx rd, rx
33 strb \rd, [\rx, # S3C2410_UTXH ]
34 .endm
35
36 .macro busyuart, rd, rx
37 ldr \rd, [ \rx, # S3C2410_UFCON ]
38 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
39 beq 1001f @
40 @ FIFO enabled...
411003:
42 @ check for arm920 vs arm926. currently assume all arm926 33 @ check for arm920 vs arm926. currently assume all arm926
43 @ devices have an 64 byte FIFO identical to the s3c2440 34 @ devices have an 64 byte FIFO identical to the s3c2440
44 mrc p15, 0, \rd, c0, c0 35 mrc p15, 0, \rd, c0, c0
@@ -57,25 +48,22 @@
57 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 48 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
58 moveq \rd, \rd, lsr #SHIFT_2440TXF 49 moveq \rd, \rd, lsr #SHIFT_2440TXF
59 tst \rd, #S3C2410_UFSTAT_TXFULL 50 tst \rd, #S3C2410_UFSTAT_TXFULL
60 bne 1003b 51 .endm
61 b 1002f
62
631001:
64 @ busy waiting for non fifo
65 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
66 tst \rd, #S3C2410_UTRSTAT_TXFE
67 beq 1001b
68 52
691002: @ exit busyuart 53 .macro fifo_full_s3c2410 rd, rx
70 .endm 54 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
55 tst \rd, #S3C2410_UFSTAT_TXFULL
56 .endm
71 57
72 .macro waituart,rd,rx 58/* fifo level reading */
73 59
74 ldr \rd, [ \rx, # S3C2410_UFCON ] 60 .macro fifo_level_s3c24xx rd, rx
75 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? 61 @ check for arm920 vs arm926. currently assume all arm926
76 beq 1001f @ 62 @ devices have an 64 byte FIFO identical to the s3c2440
77 @ FIFO enabled... 63 mrc p15, 0, \rd, c0, c0
781003: 64 and \rd, \rd, #0xff0
65 teq \rd, #0x260
66 beq 10000f
79 mrc p15, 0, \rd, c1, c0 67 mrc p15, 0, \rd, c1, c0
80 tst \rd, #1 68 tst \rd, #1
81 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) 69 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -85,18 +73,32 @@
85 and \rd, \rd, #0x00ff0000 73 and \rd, \rd, #0x00ff0000
86 teq \rd, #0x00440000 @ is it 2440? 74 teq \rd, #0x00440000 @ is it 2440?
87 75
7610000:
88 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 77 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
89 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK 78 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
90 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK 79 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
91 teq \rd, #0 80 .endm
92 bne 1003b 81
93 b 1002f 82 .macro fifo_level_s3c2410 rd, rx
83 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
84 and \rd, \rd, #S3C2410_UFSTAT_TXMASK
85 .endm
86
87/* Select the correct implementation depending on the configuration. The
88 * S3C2440 will get selected by default, as these are the most widely
89 * used variants of these
90*/
91
92#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
93#define fifo_full fifo_full_s3c2410
94#define fifo_level fifo_level_s3c2410
95#warning 2410only
96#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
97#define fifo_full fifo_full_s3c24xx
98#define fifo_level fifo_level_s3c24xx
99#warning generic
100#endif
94 101
951001: 102/* include the reset of the code which will do the work */
96 @ idle waiting for non fifo
97 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
98 tst \rd, #S3C2410_UTRSTAT_TXFE
99 beq 1001b
100 103
1011002: @ exit busyuart 104#include <asm/plat-s3c/debug-macro.S>
102 .endm
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 19e77f038042..b33ed3b05ef5 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -13,58 +13,36 @@
13#ifndef __ASM_ARCH_MAP_H 13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H 14#define __ASM_ARCH_MAP_H
15 15
16/* we have a bit of a tight squeeze to fit all our registers from 16#include <asm/plat-s3c/map.h>
17 * 0xF00000000 upwards, since we use all of the nGCS space in some
18 * capacity, and also need to fit the S3C2410 registers in as well...
19 *
20 * we try to ensure stuff like the IRQ registers are available for
21 * an single MOVS instruction (ie, only 8 bits of set data)
22 *
23 * Note, we are trying to remove some of these from the implementation
24 * as they are only useful to certain drivers...
25 */
26
27#ifndef __ASSEMBLY__
28#define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x))
29#else
30#define S3C2410_ADDR(x) (0xF0000000 + (x))
31#endif
32 17
33#define S3C2400_ADDR(x) S3C2410_ADDR(x) 18#define S3C2410_ADDR(x) S3C_ADDR(x)
34 19
35/* interrupt controller is the first thing we put in, to make 20/* interrupt controller is the first thing we put in, to make
36 * the assembly code for the irq detection easier 21 * the assembly code for the irq detection easier
37 */ 22 */
38#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000) 23#define S3C24XX_VA_IRQ S3C_VA_IRQ
39#define S3C2400_PA_IRQ (0x14400000)
40#define S3C2410_PA_IRQ (0x4A000000) 24#define S3C2410_PA_IRQ (0x4A000000)
41#define S3C24XX_SZ_IRQ SZ_1M 25#define S3C24XX_SZ_IRQ SZ_1M
42 26
43/* memory controller registers */ 27/* memory controller registers */
44#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000) 28#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
45#define S3C2400_PA_MEMCTRL (0x14000000)
46#define S3C2410_PA_MEMCTRL (0x48000000) 29#define S3C2410_PA_MEMCTRL (0x48000000)
47#define S3C24XX_SZ_MEMCTRL SZ_1M 30#define S3C24XX_SZ_MEMCTRL SZ_1M
48 31
49/* USB host controller */ 32/* USB host controller */
50#define S3C2400_PA_USBHOST (0x14200000)
51#define S3C2410_PA_USBHOST (0x49000000) 33#define S3C2410_PA_USBHOST (0x49000000)
52#define S3C24XX_SZ_USBHOST SZ_1M 34#define S3C24XX_SZ_USBHOST SZ_1M
53 35
54/* DMA controller */ 36/* DMA controller */
55#define S3C2400_PA_DMA (0x14600000)
56#define S3C2410_PA_DMA (0x4B000000) 37#define S3C2410_PA_DMA (0x4B000000)
57#define S3C24XX_SZ_DMA SZ_1M 38#define S3C24XX_SZ_DMA SZ_1M
58 39
59/* Clock and Power management */ 40/* Clock and Power management */
60#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000) 41#define S3C24XX_VA_CLKPWR S3C_VA_SYS
61#define S3C2400_PA_CLKPWR (0x14800000)
62#define S3C2410_PA_CLKPWR (0x4C000000) 42#define S3C2410_PA_CLKPWR (0x4C000000)
63#define S3C24XX_SZ_CLKPWR SZ_1M 43#define S3C24XX_SZ_CLKPWR SZ_1M
64 44
65/* LCD controller */ 45/* LCD controller */
66#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000)
67#define S3C2400_PA_LCD (0x14A00000)
68#define S3C2410_PA_LCD (0x4D000000) 46#define S3C2410_PA_LCD (0x4D000000)
69#define S3C24XX_SZ_LCD SZ_1M 47#define S3C24XX_SZ_LCD SZ_1M
70 48
@@ -72,41 +50,30 @@
72#define S3C2410_PA_NAND (0x4E000000) 50#define S3C2410_PA_NAND (0x4E000000)
73#define S3C24XX_SZ_NAND SZ_1M 51#define S3C24XX_SZ_NAND SZ_1M
74 52
75/* MMC controller - available on the S3C2400 */
76#define S3C2400_PA_MMC (0x15A00000)
77#define S3C2400_SZ_MMC SZ_1M
78
79/* UARTs */ 53/* UARTs */
80#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000) 54#define S3C24XX_VA_UART S3C_VA_UART
81#define S3C2400_PA_UART (0x15000000)
82#define S3C2410_PA_UART (0x50000000) 55#define S3C2410_PA_UART (0x50000000)
83#define S3C24XX_SZ_UART SZ_1M 56#define S3C24XX_SZ_UART SZ_1M
84 57
85/* Timers */ 58/* Timers */
86#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000) 59#define S3C24XX_VA_TIMER S3C_VA_TIMER
87#define S3C2400_PA_TIMER (0x15100000)
88#define S3C2410_PA_TIMER (0x51000000) 60#define S3C2410_PA_TIMER (0x51000000)
89#define S3C24XX_SZ_TIMER SZ_1M 61#define S3C24XX_SZ_TIMER SZ_1M
90 62
91/* USB Device port */ 63/* USB Device port */
92#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000)
93#define S3C2400_PA_USBDEV (0x15200140)
94#define S3C2410_PA_USBDEV (0x52000000) 64#define S3C2410_PA_USBDEV (0x52000000)
95#define S3C24XX_SZ_USBDEV SZ_1M 65#define S3C24XX_SZ_USBDEV SZ_1M
96 66
97/* Watchdog */ 67/* Watchdog */
98#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000) 68#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
99#define S3C2400_PA_WATCHDOG (0x15300000)
100#define S3C2410_PA_WATCHDOG (0x53000000) 69#define S3C2410_PA_WATCHDOG (0x53000000)
101#define S3C24XX_SZ_WATCHDOG SZ_1M 70#define S3C24XX_SZ_WATCHDOG SZ_1M
102 71
103/* IIC hardware controller */ 72/* IIC hardware controller */
104#define S3C2400_PA_IIC (0x15400000)
105#define S3C2410_PA_IIC (0x54000000) 73#define S3C2410_PA_IIC (0x54000000)
106#define S3C24XX_SZ_IIC SZ_1M 74#define S3C24XX_SZ_IIC SZ_1M
107 75
108/* IIS controller */ 76/* IIS controller */
109#define S3C2400_PA_IIS (0x15508000)
110#define S3C2410_PA_IIS (0x55000000) 77#define S3C2410_PA_IIS (0x55000000)
111#define S3C24XX_SZ_IIS SZ_1M 78#define S3C24XX_SZ_IIS SZ_1M
112 79
@@ -116,27 +83,23 @@
116 * it is the same distance apart from the UART in the 83 * it is the same distance apart from the UART in the
117 * phsyical address space, as the initial mapping for the IO 84 * phsyical address space, as the initial mapping for the IO
118 * is done as a 1:1 maping. This puts it (currently) at 85 * is done as a 1:1 maping. This puts it (currently) at
119 * 0xF6800000, which is not in the way of any current mapping 86 * 0xFA800000, which is not in the way of any current mapping
120 * by the base system. 87 * by the base system.
121*/ 88*/
122 89
123#define S3C2400_PA_GPIO (0x15600000)
124#define S3C2410_PA_GPIO (0x56000000) 90#define S3C2410_PA_GPIO (0x56000000)
125#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) 91#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
126#define S3C24XX_SZ_GPIO SZ_1M 92#define S3C24XX_SZ_GPIO SZ_1M
127 93
128/* RTC */ 94/* RTC */
129#define S3C2400_PA_RTC (0x15700040)
130#define S3C2410_PA_RTC (0x57000000) 95#define S3C2410_PA_RTC (0x57000000)
131#define S3C24XX_SZ_RTC SZ_1M 96#define S3C24XX_SZ_RTC SZ_1M
132 97
133/* ADC */ 98/* ADC */
134#define S3C2400_PA_ADC (0x15800000)
135#define S3C2410_PA_ADC (0x58000000) 99#define S3C2410_PA_ADC (0x58000000)
136#define S3C24XX_SZ_ADC SZ_1M 100#define S3C24XX_SZ_ADC SZ_1M
137 101
138/* SPI */ 102/* SPI */
139#define S3C2400_PA_SPI (0x15900000)
140#define S3C2410_PA_SPI (0x59000000) 103#define S3C2410_PA_SPI (0x59000000)
141#define S3C24XX_SZ_SPI SZ_1M 104#define S3C24XX_SZ_SPI SZ_1M
142 105
@@ -177,37 +140,8 @@
177 140
178#define S3C2410_SDRAM_PA (S3C2410_CS6) 141#define S3C2410_SDRAM_PA (S3C2410_CS6)
179 142
180#define S3C2400_CS0 (0x00000000)
181#define S3C2400_CS1 (0x02000000)
182#define S3C2400_CS2 (0x04000000)
183#define S3C2400_CS3 (0x06000000)
184#define S3C2400_CS4 (0x08000000)
185#define S3C2400_CS5 (0x0A000000)
186#define S3C2400_CS6 (0x0C000000)
187#define S3C2400_CS7 (0x0E000000)
188
189#define S3C2400_SDRAM_PA (S3C2400_CS6)
190
191/* Use a single interface for common resources between S3C24XX cpus */ 143/* Use a single interface for common resources between S3C24XX cpus */
192 144
193#ifdef CONFIG_CPU_S3C2400
194#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
195#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
196#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
197#define S3C24XX_PA_DMA S3C2400_PA_DMA
198#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
199#define S3C24XX_PA_LCD S3C2400_PA_LCD
200#define S3C24XX_PA_UART S3C2400_PA_UART
201#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
202#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
203#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
204#define S3C24XX_PA_IIC S3C2400_PA_IIC
205#define S3C24XX_PA_IIS S3C2400_PA_IIS
206#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
207#define S3C24XX_PA_RTC S3C2400_PA_RTC
208#define S3C24XX_PA_ADC S3C2400_PA_ADC
209#define S3C24XX_PA_SPI S3C2400_PA_SPI
210#else
211#define S3C24XX_PA_IRQ S3C2410_PA_IRQ 145#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
212#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL 146#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
213#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST 147#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
@@ -224,7 +158,6 @@
224#define S3C24XX_PA_RTC S3C2410_PA_RTC 158#define S3C24XX_PA_RTC S3C2410_PA_RTC
225#define S3C24XX_PA_ADC S3C2410_PA_ADC 159#define S3C24XX_PA_ADC S3C2410_PA_ADC
226#define S3C24XX_PA_SPI S3C2410_PA_SPI 160#define S3C24XX_PA_SPI S3C2410_PA_SPI
227#endif
228 161
229/* deal with the registers that move under the 2412/2413 */ 162/* deal with the registers that move under the 2412/2413 */
230 163
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 4be6a74c4303..533e2436e707 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -11,20 +11,7 @@
11#ifndef __ASM_ARCH_MEMORY_H 11#ifndef __ASM_ARCH_MEMORY_H
12#define __ASM_ARCH_MEMORY_H 12#define __ASM_ARCH_MEMORY_H
13 13
14/*
15 * DRAM starts at 0x30000000 for S3C2410/S3C2440
16 * and at 0x0C000000 for S3C2400
17 */
18#ifdef CONFIG_CPU_S3C2400
19#define PHYS_OFFSET UL(0x0C000000)
20#else
21#define PHYS_OFFSET UL(0x30000000) 14#define PHYS_OFFSET UL(0x30000000)
22#endif
23
24/*
25 * These are exactly the same on the S3C2410 as the
26 * physical memory view.
27*/
28 15
29#define __virt_to_bus(x) __virt_to_phys(x) 16#define __virt_to_bus(x) __virt_to_phys(x)
30#define __bus_to_virt(x) __phys_to_virt(x) 17#define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b7faeb04c0ff..76fe5f693426 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -12,7 +12,7 @@
12#ifndef ___ASM_ARCH_REGS_LCD_H 12#ifndef ___ASM_ARCH_REGS_LCD_H
13#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $" 13#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
14 14
15#define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD) 15#define S3C2410_LCDREG(x) (x)
16 16
17/* LCD control registers */ 17/* LCD control registers */
18#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) 18#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 1c74ef17da33..63891786dfa0 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -17,7 +17,7 @@
17#include <asm/arch/idle.h> 17#include <asm/arch/idle.h>
18#include <asm/arch/reset.h> 18#include <asm/arch/reset.h>
19 19
20#include <asm/arch/regs-watchdog.h> 20#include <asm/plat-s3c/regs-watchdog.h>
21#include <asm/arch/regs-clock.h> 21#include <asm/arch/regs-clock.h>
22 22
23void (*s3c24xx_idle)(void); 23void (*s3c24xx_idle)(void);
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index dcb2cef38f50..48a5731ee988 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -1,6 +1,7 @@
1/* linux/include/asm-arm/arch-s3c2410/uncompress.h 1/* linux/include/asm-arm/arch-s3c2410/uncompress.h
2 * 2 *
3 * Copyright (c) 2003 Simtec Electronics 3 * Copyright (c) 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
5 * 6 *
6 * S3C2410 - uncompress code 7 * S3C2410 - uncompress code
@@ -13,153 +14,39 @@
13#ifndef __ASM_ARCH_UNCOMPRESS_H 14#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H 15#define __ASM_ARCH_UNCOMPRESS_H
15 16
16typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ 17#include <asm/arch/regs-gpio.h>
17
18/* defines for UART registers */
19#include "asm/arch/regs-serial.h"
20#include "asm/arch/regs-gpio.h"
21#include "asm/arch/regs-watchdog.h"
22
23#include <asm/arch/map.h> 18#include <asm/arch/map.h>
24 19
25/* working in physical space... */ 20/* working in physical space... */
26#undef S3C2410_GPIOREG 21#undef S3C2410_GPIOREG
27#undef S3C2410_WDOGREG
28
29#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) 22#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
30#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
31 23
32/* how many bytes we allow into the FIFO at a time in FIFO mode */ 24#include <asm/plat-s3c/uncompress.h>
33#define FIFO_MAX (14)
34 25
35#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT) 26static inline int is_arm926(void)
36
37static __inline__ void
38uart_wr(unsigned int reg, unsigned int val)
39{ 27{
40 volatile unsigned int *ptr; 28 unsigned int cpuid;
41
42 ptr = (volatile unsigned int *)(reg + uart_base);
43 *ptr = val;
44}
45 29
46static __inline__ unsigned int 30 asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
47uart_rd(unsigned int reg)
48{
49 volatile unsigned int *ptr;
50 31
51 ptr = (volatile unsigned int *)(reg + uart_base); 32 return ((cpuid & 0xff0) == 0x260);
52 return *ptr;
53} 33}
54 34
55 35static void arch_detect_cpu(void)
56/* we can deal with the case the UARTs are being run
57 * in FIFO mode, so that we don't hold up our execution
58 * waiting for tx to happen...
59*/
60
61static void putc(int ch)
62{ 36{
63 int cpuid = S3C2410_GSTATUS1_2410; 37 unsigned int cpuid;
64 38
65#ifndef CONFIG_CPU_S3C2400
66 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); 39 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
67 cpuid &= S3C2410_GSTATUS1_IDMASK; 40 cpuid &= S3C2410_GSTATUS1_IDMASK;
68#endif
69
70 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
71 int level;
72
73 while (1) {
74 level = uart_rd(S3C2410_UFSTAT);
75
76 if (cpuid == S3C2410_GSTATUS1_2440 ||
77 cpuid == S3C2410_GSTATUS1_2442) {
78 level &= S3C2440_UFSTAT_TXMASK;
79 level >>= S3C2440_UFSTAT_TXSHIFT;
80 } else {
81 level &= S3C2410_UFSTAT_TXMASK;
82 level >>= S3C2410_UFSTAT_TXSHIFT;
83 }
84
85 if (level < FIFO_MAX)
86 break;
87 }
88 41
42 if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
43 cpuid == S3C2410_GSTATUS1_2442) {
44 fifo_mask = S3C2440_UFSTAT_TXMASK;
45 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
89 } else { 46 } else {
90 /* not using fifos */ 47 fifo_mask = S3C2410_UFSTAT_TXMASK;
91 48 fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
92 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
93 barrier();
94 } 49 }
95
96 /* write byte to transmission register */
97 uart_wr(S3C2410_UTXH, ch);
98} 50}
99 51
100static inline void flush(void)
101{
102}
103
104#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
105
106/* CONFIG_S3C2410_BOOT_WATCHDOG
107 *
108 * Simple boot-time watchdog setup, to reboot the system if there is
109 * any problem with the boot process
110*/
111
112#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
113
114#define WDOG_COUNT (0xff00)
115
116static inline void arch_decomp_wdog(void)
117{
118 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
119}
120
121static void arch_decomp_wdog_start(void)
122{
123 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
124 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
125 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
126}
127
128#else
129#define arch_decomp_wdog_start()
130#define arch_decomp_wdog()
131#endif
132
133#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
134
135static void arch_decomp_error(const char *x)
136{
137 putstr("\n\n");
138 putstr(x);
139 putstr("\n\n -- System resetting\n");
140
141 __raw_writel(0x4000, S3C2410_WTDAT);
142 __raw_writel(0x4000, S3C2410_WTCNT);
143 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
144
145 while(1);
146}
147
148#define arch_error arch_decomp_error
149#endif
150
151static void error(char *err);
152
153static void
154arch_decomp_setup(void)
155{
156 /* we may need to setup the uart(s) here if we are not running
157 * on an BAST... the BAST will have left the uarts configured
158 * after calling linux.
159 */
160
161 arch_decomp_wdog_start();
162}
163
164
165#endif /* __ASM_ARCH_UNCOMPRESS_H */ 52#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
new file mode 100644
index 000000000000..45d2bb59f9d0
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/jornada720.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-arm/arch-sa1100/jornada720.h
3 *
4 * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728
5 *
6 * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
7 * Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 /* HP Jornada 7xx microprocessor commands */
16#define GETBATTERYDATA 0xc0
17#define GETSCANKEYCODE 0x90
18#define GETTOUCHSAMPLES 0xa0
19#define GETCONTRAST 0xD0
20#define SETCONTRAST 0xD1
21#define GETBRIGHTNESS 0xD2
22#define SETBRIGHTNESS 0xD3
23#define CONTRASTOFF 0xD8
24#define BRIGHTNESSOFF 0xD9
25#define PWMOFF 0xDF
26#define TXDUMMY 0x11
27#define ERRORCODE 0x00
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index d7a777f05088..ec1c685562ce 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,13 +1,14 @@
1#ifndef __ASMARM_ELF_H 1#ifndef __ASMARM_ELF_H
2#define __ASMARM_ELF_H 2#define __ASMARM_ELF_H
3 3
4#include <asm/hwcap.h>
5
4#ifndef __ASSEMBLY__ 6#ifndef __ASSEMBLY__
5/* 7/*
6 * ELF register definitions.. 8 * ELF register definitions..
7 */ 9 */
8#include <asm/ptrace.h> 10#include <asm/ptrace.h>
9#include <asm/user.h> 11#include <asm/user.h>
10#include <asm/hwcap.h>
11 12
12typedef unsigned long elf_greg_t; 13typedef unsigned long elf_greg_t;
13typedef unsigned long elf_freg_t[3]; 14typedef unsigned long elf_freg_t[3];
diff --git a/include/asm-arm/floppy.h b/include/asm-arm/floppy.h
index 54b5ae44ed94..d595c15166a4 100644
--- a/include/asm-arm/floppy.h
+++ b/include/asm-arm/floppy.h
@@ -30,15 +30,21 @@
30#define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK) 30#define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK)
31#define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK) 31#define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK)
32 32
33static inline int fd_dma_setup(void *data, unsigned int length,
34 unsigned int mode, unsigned long addr)
35{
36 set_dma_mode(DMA_FLOPPY, mode);
37 __set_dma_addr(DMA_FLOPPY, data);
38 set_dma_count(DMA_FLOPPY, length);
39 virtual_dma_port = addr;
40 enable_dma(DMA_FLOPPY);
41 return 0;
42}
43#define fd_dma_setup fd_dma_setup
44
33#define fd_request_dma() request_dma(DMA_FLOPPY,"floppy") 45#define fd_request_dma() request_dma(DMA_FLOPPY,"floppy")
34#define fd_free_dma() free_dma(DMA_FLOPPY) 46#define fd_free_dma() free_dma(DMA_FLOPPY)
35#define fd_disable_dma() disable_dma(DMA_FLOPPY) 47#define fd_disable_dma() disable_dma(DMA_FLOPPY)
36#define fd_enable_dma() enable_dma(DMA_FLOPPY)
37#define fd_clear_dma_ff() clear_dma_ff(DMA_FLOPPY)
38#define fd_set_dma_mode(mode) set_dma_mode(DMA_FLOPPY, (mode))
39#define fd_set_dma_addr(addr) set_dma_addr(DMA_FLOPPY, virt_to_bus((addr)))
40#define fd_set_dma_count(len) set_dma_count(DMA_FLOPPY, (len))
41#define fd_cacheflush(addr,sz)
42 48
43/* need to clean up dma.h */ 49/* need to clean up dma.h */
44#define DMA_FLOPPYDISK DMA_FLOPPY 50#define DMA_FLOPPYDISK DMA_FLOPPY
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index 81ca5d3e2bff..fb90b421f31c 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -194,6 +194,13 @@ extern int init_atu;
194#define IOP_TMR_PRIVILEGED 0x08 194#define IOP_TMR_PRIVILEGED 0x08
195#define IOP_TMR_RATIO_1_1 0x00 195#define IOP_TMR_RATIO_1_1 0x00
196 196
197/* Watchdog timer definitions */
198#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
199#define IOP_WDTCR_EN 0xe1e1e1e1
200/* iop3xx does not support stopping the watchdog, so we just re-arm */
201#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
202#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
203
197/* Application accelerator unit */ 204/* Application accelerator unit */
198#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) 205#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
199#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) 206#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
@@ -274,6 +281,32 @@ static inline void write_tisr(u32 val)
274 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); 281 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
275} 282}
276 283
284static inline u32 read_wdtcr(void)
285{
286 u32 val;
287 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
288 return val;
289}
290static inline void write_wdtcr(u32 val)
291{
292 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
293}
294
295extern unsigned long get_iop_tick_rate(void);
296
297/* only iop13xx has these registers, we define these to present a
298 * common register interface for the iop_wdt driver.
299 */
300#define IOP_RCSR_WDT (0)
301static inline u32 read_rcsr(void)
302{
303 return 0;
304}
305static inline void write_wdtsr(u32 val)
306{
307 do { } while (0);
308}
309
277extern struct platform_device iop3xx_dma_0_channel; 310extern struct platform_device iop3xx_dma_0_channel;
278extern struct platform_device iop3xx_dma_1_channel; 311extern struct platform_device iop3xx_dma_1_channel;
279extern struct platform_device iop3xx_aau_channel; 312extern struct platform_device iop3xx_aau_channel;
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index 0c8be19fd66b..b186bc820e30 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -102,7 +102,8 @@ extern int is_in_rom(unsigned long);
102#define v4_tlb_fns (0) 102#define v4_tlb_fns (0)
103#define v4wb_tlb_fns (0) 103#define v4wb_tlb_fns (0)
104#define v4wbi_tlb_fns (0) 104#define v4wbi_tlb_fns (0)
105#define v6_tlb_fns (0) 105#define v6wbi_tlb_fns (0)
106#define v7wbi_tlb_fns (0)
106 107
107#define v3_user_fns (0) 108#define v3_user_fns (0)
108#define v4_user_fns (0) 109#define v4_user_fns (0)
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S
new file mode 100644
index 000000000000..84c40b847da8
--- /dev/null
+++ b/include/asm-arm/plat-s3c/debug-macro.S
@@ -0,0 +1,75 @@
1/* linux/include/asm-arm/plat-s3c/debug-macro.S
2 *
3 * Copyright 2005, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <asm/plat-s3c/regs-serial.h>
13
14/* The S3C2440 implementations are used by default as they are the
15 * most widely re-used */
16
17 .macro fifo_level_s3c2440 rd, rx
18 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
19 and \rd, \rd, #S3C2440_UFSTAT_TXMASK
20 .endm
21
22#ifndef fifo_level
23#define fifo_level fifo_level_s3c2410
24#endif
25
26 .macro fifo_full_s3c2440 rd, rx
27 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
28 tst \rd, #S3C2440_UFSTAT_TXFULL
29 .endm
30
31#ifndef fifo_full
32#define fifo_full fifo_full_s3c2440
33#endif
34
35 .macro senduart,rd,rx
36 strb \rd, [\rx, # S3C2410_UTXH ]
37 .endm
38
39 .macro busyuart, rd, rx
40 ldr \rd, [ \rx, # S3C2410_UFCON ]
41 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
42 beq 1001f @
43 @ FIFO enabled...
441003:
45 fifo_full \rd, \rx
46 bne 1003b
47 b 1002f
48
491001:
50 @ busy waiting for non fifo
51 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
52 tst \rd, #S3C2410_UTRSTAT_TXFE
53 beq 1001b
54
551002: @ exit busyuart
56 .endm
57
58 .macro waituart,rd,rx
59 ldr \rd, [ \rx, # S3C2410_UFCON ]
60 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
61 beq 1001f @
62 @ FIFO enabled...
631003:
64 fifo_level \rd, \rx
65 teq \rd, #0
66 bne 1003b
67 b 1002f
681001:
69 @ idle waiting for non fifo
70 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
71 tst \rd, #S3C2410_UTRSTAT_TXFE
72 beq 1001b
73
741002: @ exit busyuart
75 .endm
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/plat-s3c/iic.h
index 71211c8b5384..71211c8b5384 100644
--- a/include/asm-arm/arch-s3c2410/iic.h
+++ b/include/asm-arm/plat-s3c/iic.h
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
new file mode 100644
index 000000000000..95a82b0e84a1
--- /dev/null
+++ b/include/asm-arm/plat-s3c/map.h
@@ -0,0 +1,40 @@
1/* linux/include/asm-arm/plat-s3c/map.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - Memory map definitions (virtual addresses)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_MAP_H
15#define __ASM_PLAT_MAP_H __FILE__
16
17/* Fit all our registers in at 0xF4000000 upwards, trying to use as
18 * little of the VA space as possible so vmalloc and friends have a
19 * better chance of getting memory.
20 *
21 * we try to ensure stuff like the IRQ registers are available for
22 * an single MOVS instruction (ie, only 8 bits of set data)
23 */
24
25#define S3C_ADDR_BASE (0xF4000000)
26
27#ifndef __ASSEMBLY__
28#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
29#else
30#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
31#endif
32
33#define S3C_VA_IRQ S3C_ADDR(0x000000000) /* irq controller(s) */
34#define S3C_VA_SYS S3C_ADDR(0x001000000) /* system control */
35#define S3C_VA_MEM S3C_ADDR(0x002000000) /* system control */
36#define S3C_VA_TIMER S3C_ADDR(0x003000000) /* timer block */
37#define S3C_VA_WATCHDOG S3C_ADDR(0x004000000) /* watchdog */
38#define S3C_VA_UART S3C_ADDR(0x010000000) /* UART */
39
40#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/plat-s3c/nand.h
index 8816f7f9cee1..8816f7f9cee1 100644
--- a/include/asm-arm/arch-s3c2410/nand.h
+++ b/include/asm-arm/plat-s3c/nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h
index b004dee6bcaf..b004dee6bcaf 100644
--- a/include/asm-arm/arch-s3c2410/regs-ac97.h
+++ b/include/asm-arm/plat-s3c/regs-ac97.h
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
index c7f231963e76..c7f231963e76 100644
--- a/include/asm-arm/arch-s3c2410/regs-adc.h
+++ b/include/asm-arm/plat-s3c/regs-adc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
index 2ae29522f253..2ae29522f253 100644
--- a/include/asm-arm/arch-s3c2410/regs-iic.h
+++ b/include/asm-arm/plat-s3c/regs-iic.h
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
index b824d371ae0b..b824d371ae0b 100644
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ b/include/asm-arm/plat-s3c/regs-nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
index 93b03c49710a..93b03c49710a 100644
--- a/include/asm-arm/arch-s3c2410/regs-rtc.h
+++ b/include/asm-arm/plat-s3c/regs-rtc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
index 8946702a87f5..923e114db663 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/plat-s3c/regs-serial.h
@@ -32,10 +32,10 @@
32#ifndef __ASM_ARM_REGS_SERIAL_H 32#ifndef __ASM_ARM_REGS_SERIAL_H
33#define __ASM_ARM_REGS_SERIAL_H 33#define __ASM_ARM_REGS_SERIAL_H
34 34
35#define S3C24XX_VA_UART0 (S3C24XX_VA_UART) 35#define S3C24XX_VA_UART0 (S3C_VA_UART)
36#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 ) 36#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
37#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 ) 37#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
38#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 ) 38#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
39 39
40#define S3C2410_PA_UART0 (S3C24XX_PA_UART) 40#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) 41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 6f8fe432fe3a..8b0d594397b1 100644
--- a/include/asm-arm/arch-s3c2410/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -14,12 +14,12 @@
14#ifndef __ASM_ARCH_REGS_TIMER_H 14#ifndef __ASM_ARCH_REGS_TIMER_H
15#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $" 15#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
16 16
17#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x)) 17#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
18#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c)) 18#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
19 19
20#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00) 20#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
21#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04) 21#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
22#define S3C2410_TCON S3C2410_TIMERREG(0x08) 22#define S3C2410_TCON S3C_TIMERREG(0x08)
23 23
24#define S3C2410_TCFG_PRESCALER0_MASK (255<<0) 24#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
25#define S3C2410_TCFG_PRESCALER1_MASK (255<<8) 25#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
@@ -71,9 +71,9 @@
71 71
72/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ 72/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
73 73
74#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00) 74#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
75#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04) 75#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
76#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) 76#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
77 77
78#define S3C2410_TCON_T4RELOAD (1<<22) 78#define S3C2410_TCON_T4RELOAD (1<<22)
79#define S3C2410_TCON_T4MANUALUPD (1<<21) 79#define S3C2410_TCON_T4MANUALUPD (1<<21)
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
index a9c5d491bdb6..56c4193b7a46 100644
--- a/include/asm-arm/arch-s3c2410/regs-watchdog.h
+++ b/include/asm-arm/plat-s3c/regs-watchdog.h
@@ -14,11 +14,11 @@
14#ifndef __ASM_ARCH_REGS_WATCHDOG_H 14#ifndef __ASM_ARCH_REGS_WATCHDOG_H
15#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $" 15#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
16 16
17#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG) 17#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
18 18
19#define S3C2410_WTCON S3C2410_WDOGREG(0x00) 19#define S3C2410_WTCON S3C_WDOGREG(0x00)
20#define S3C2410_WTDAT S3C2410_WDOGREG(0x04) 20#define S3C2410_WTDAT S3C_WDOGREG(0x04)
21#define S3C2410_WTCNT S3C2410_WDOGREG(0x08) 21#define S3C2410_WTCNT S3C_WDOGREG(0x08)
22 22
23/* the watchdog can either generate a reset pulse, or an 23/* the watchdog can either generate a reset pulse, or an
24 * interrupt. 24 * interrupt.
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
new file mode 100644
index 000000000000..b5e6208175d1
--- /dev/null
+++ b/include/asm-arm/plat-s3c/uncompress.h
@@ -0,0 +1,155 @@
1/* linux/include/asm-arm/plat-s3c/uncompress.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - uncompress code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_UNCOMPRESS_H
15#define __ASM_PLAT_UNCOMPRESS_H
16
17typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
18
19/* uart setup */
20
21static unsigned int fifo_mask;
22static unsigned int fifo_max;
23
24/* forward declerations */
25
26static void arch_detect_cpu(void);
27
28/* defines for UART registers */
29
30#include "asm/plat-s3c/regs-serial.h"
31#include "asm/plat-s3c/regs-watchdog.h"
32
33/* working in physical space... */
34#undef S3C2410_WDOGREG
35#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
36
37/* how many bytes we allow into the FIFO at a time in FIFO mode */
38#define FIFO_MAX (14)
39
40#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
41
42static __inline__ void
43uart_wr(unsigned int reg, unsigned int val)
44{
45 volatile unsigned int *ptr;
46
47 ptr = (volatile unsigned int *)(reg + uart_base);
48 *ptr = val;
49}
50
51static __inline__ unsigned int
52uart_rd(unsigned int reg)
53{
54 volatile unsigned int *ptr;
55
56 ptr = (volatile unsigned int *)(reg + uart_base);
57 return *ptr;
58}
59
60/* we can deal with the case the UARTs are being run
61 * in FIFO mode, so that we don't hold up our execution
62 * waiting for tx to happen...
63*/
64
65static void putc(int ch)
66{
67 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
68 int level;
69
70 while (1) {
71 level = uart_rd(S3C2410_UFSTAT);
72 level &= fifo_mask;
73
74 if (level < fifo_max)
75 break;
76 }
77
78 } else {
79 /* not using fifos */
80
81 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
82 barrier();
83 }
84
85 /* write byte to transmission register */
86 uart_wr(S3C2410_UTXH, ch);
87}
88
89static inline void flush(void)
90{
91}
92
93#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
94
95/* CONFIG_S3C_BOOT_WATCHDOG
96 *
97 * Simple boot-time watchdog setup, to reboot the system if there is
98 * any problem with the boot process
99*/
100
101#ifdef CONFIG_S3C_BOOT_WATCHDOG
102
103#define WDOG_COUNT (0xff00)
104
105static inline void arch_decomp_wdog(void)
106{
107 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
108}
109
110static void arch_decomp_wdog_start(void)
111{
112 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
113 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
114 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
115}
116
117#else
118#define arch_decomp_wdog_start()
119#define arch_decomp_wdog()
120#endif
121
122#ifdef CONFIG_S3C_BOOT_ERROR_RESET
123
124static void arch_decomp_error(const char *x)
125{
126 putstr("\n\n");
127 putstr(x);
128 putstr("\n\n -- System resetting\n");
129
130 __raw_writel(0x4000, S3C2410_WTDAT);
131 __raw_writel(0x4000, S3C2410_WTCNT);
132 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
133
134 while(1);
135}
136
137#define arch_error arch_decomp_error
138#endif
139
140static void error(char *err);
141
142static void
143arch_decomp_setup(void)
144{
145 /* we may need to setup the uart(s) here if we are not running
146 * on an BAST... the BAST will have left the uarts configured
147 * after calling linux.
148 */
149
150 arch_detect_cpu();
151 arch_decomp_wdog_start();
152}
153
154
155#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h
index eaf77916a602..eaf77916a602 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/plat-s3c24xx/regs-iis.h
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 4a499a138256..4a499a138256 100644
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h
index e1e9805d2d9a..e1e9805d2d9a 100644
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ b/include/asm-arm/plat-s3c24xx/regs-udc.h
diff --git a/include/asm-arm/arch-s3c2410/udc.h b/include/asm-arm/plat-s3c24xx/udc.h
index b8aa6cb69b58..b8aa6cb69b58 100644
--- a/include/asm-arm/arch-s3c2410/udc.h
+++ b/include/asm-arm/plat-s3c24xx/udc.h
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index eae85b09db2e..69c65d56a6ac 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -24,7 +24,6 @@
24struct task_struct; 24struct task_struct;
25struct exec_domain; 25struct exec_domain;
26 26
27#include <asm/ptrace.h>
28#include <asm/types.h> 27#include <asm/types.h>
29#include <asm/domain.h> 28#include <asm/domain.h>
30 29
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index bfdbebebdc1b..d327b25c986c 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -441,7 +441,6 @@
441/* 441/*
442 * Unimplemented (or alternatively implemented) syscalls 442 * Unimplemented (or alternatively implemented) syscalls
443 */ 443 */
444#define __IGNORE_sync_file_range 1
445#define __IGNORE_fadvise64_64 1 444#define __IGNORE_fadvise64_64 1
446 445
447#endif /* __KERNEL__ */ 446#endif /* __KERNEL__ */
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index 14c5e0946c47..bd6be9d7f772 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -26,8 +26,8 @@
26#define FPSID_REV_MASK (0xF << FPSID_REV_BIT) 26#define FPSID_REV_MASK (0xF << FPSID_REV_BIT)
27 27
28/* FPEXC bits */ 28/* FPEXC bits */
29#define FPEXC_EXCEPTION (1<<31) 29#define FPEXC_EX (1 << 31)
30#define FPEXC_ENABLE (1<<30) 30#define FPEXC_EN (1 << 30)
31 31
32/* FPSCR bits */ 32/* FPSCR bits */
33#define FPSCR_DEFAULT_NAN (1<<25) 33#define FPSCR_DEFAULT_NAN (1<<25)