107 files changed, 3111 insertions, 1088 deletions

diff --git a/include/asm-arm/arch-at91/at91_lcdc.h b/include/asm-arm/arch-at91/at91_lcdc.h
deleted file mode 100644
index ab040a40d37b..000000000000
--- a/include/asm-arm/arch-at91/at91_lcdc.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_lcdc.h
- *
- * LCD Controller (LCDC).
- * Based on AT91SAM9261 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_LCDC_H
-#define AT91_LCDC_H
-
-#define AT91_LCDC_DMABADDR1     0x00            /* DMA Base Address Register 1 */
-#define AT91_LCDC_DMABADDR2     0x04            /* DMA Base Address Register 2 */
-#define AT91_LCDC_DMAFRMPT1     0x08            /* DMA Frame Pointer Register 1 */
-#define AT91_LCDC_DMAFRMPT2     0x0c            /* DMA Frame Pointer Register 2 */
-#define AT91_LCDC_DMAFRMADD1    0x10            /* DMA Frame Address Register 1 */
-#define AT91_LCDC_DMAFRMADD2    0x14            /* DMA Frame Address Register 2 */
-
-#define AT91_LCDC_DMAFRMCFG     0x18            /* DMA Frame Configuration Register */
-#define         AT91_LCDC_FRSIZE        (0x7fffff <<  0)        /* Frame Size */
-#define         AT91_LCDC_BLENGTH       (0x7f     << 24)        /* Burst Length */
-
-#define AT91_LCDC_DMACON        0x1c            /* DMA Control Register */
-#define         AT91_LCDC_DMAEN         (0x1 << 0)      /* DMA Enable */
-#define         AT91_LCDC_DMARST        (0x1 << 1)      /* DMA Reset */
-#define         AT91_LCDC_DMABUSY       (0x1 << 2)      /* DMA Busy */
-
-#define AT91_LCDC_LCDCON1       0x0800          /* LCD Control Register 1 */
-#define         AT91_LCDC_BYPASS        (1     <<  0)   /* Bypass lcd_dotck divider */
-#define         AT91_LCDC_CLKVAL        (0x1ff << 12)   /* Clock Divider */
-#define         AT91_LCDC_LINCNT        (0x7ff << 21)   /* Line Counter */
-
-#define AT91_LCDC_LCDCON2       0x0804          /* LCD Control Register 2 */
-#define         AT91_LCDC_DISTYPE       (3 << 0)        /* Display Type */
-#define                 AT91_LCDC_DISTYPE_STNMONO       (0 << 0)
-#define                 AT91_LCDC_DISTYPE_STNCOLOR      (1 << 0)
-#define                 AT91_LCDC_DISTYPE_TFT           (2 << 0)
-#define         AT91_LCDC_SCANMOD       (1 << 2)        /* Scan Mode */
-#define                 AT91_LCDC_SCANMOD_SINGLE        (0 << 2)
-#define                 AT91_LCDC_SCANMOD_DUAL          (1 << 2)
-#define         AT91_LCDC_IFWIDTH       (3 << 3)        /*Interface Width */
-#define                 AT91_LCDC_IFWIDTH_4             (0 << 3)
-#define                 AT91_LCDC_IFWIDTH_8             (1 << 3)
-#define                 AT91_LCDC_IFWIDTH_16            (2 << 3)
-#define         AT91_LCDC_PIXELSIZE     (7 << 5)        /* Bits per pixel */
-#define                 AT91_LCDC_PIXELSIZE_1           (0 << 5)
-#define                 AT91_LCDC_PIXELSIZE_2           (1 << 5)
-#define                 AT91_LCDC_PIXELSIZE_4           (2 << 5)
-#define                 AT91_LCDC_PIXELSIZE_8           (3 << 5)
-#define                 AT91_LCDC_PIXELSIZE_16          (4 << 5)
-#define                 AT91_LCDC_PIXELSIZE_24          (5 << 5)
-#define         AT91_LCDC_INVVD         (1 << 8)        /* LCD Data polarity */
-#define                 AT91_LCDC_INVVD_NORMAL          (0 << 8)
-#define                 AT91_LCDC_INVVD_INVERTED        (1 << 8)
-#define         AT91_LCDC_INVFRAME      (1 << 9 )       /* LCD VSync polarity */
-#define                 AT91_LCDC_INVFRAME_NORMAL       (0 << 9)
-#define                 AT91_LCDC_INVFRAME_INVERTED     (1 << 9)
-#define         AT91_LCDC_INVLINE       (1 << 10)       /* LCD HSync polarity */
-#define                 AT91_LCDC_INVLINE_NORMAL        (0 << 10)
-#define                 AT91_LCDC_INVLINE_INVERTED      (1 << 10)
-#define         AT91_LCDC_INVCLK        (1 << 11)       /* LCD dotclk polarity */
-#define                 AT91_LCDC_INVCLK_NORMAL         (0 << 11)
-#define                 AT91_LCDC_INVCLK_INVERTED       (1 << 11)
-#define         AT91_LCDC_INVDVAL       (1 << 12)       /* LCD dval polarity */
-#define                 AT91_LCDC_INVDVAL_NORMAL        (0 << 12)
-#define                 AT91_LCDC_INVDVAL_INVERTED      (1 << 12)
-#define         AT91_LCDC_CLKMOD        (1 << 15)       /* LCD dotclk mode */
-#define                 AT91_LCDC_CLKMOD_ACTIVEDISPLAY  (0 << 15)
-#define                 AT91_LCDC_CLKMOD_ALWAYSACTIVE   (1 << 15)
-#define         AT91_LCDC_MEMOR         (1 << 31)       /* Memory Ordering Format */
-#define                 AT91_LCDC_MEMOR_BIG             (0 << 31)
-#define                 AT91_LCDC_MEMOR_LITTLE          (1 << 31)
-
-#define AT91_LCDC_TIM1          0x0808          /* LCD Timing Register 1 */
-#define         AT91_LCDC_VFP           (0xff <<  0)    /* Vertical Front Porch */
-#define         AT91_LCDC_VBP           (0xff <<  8)    /* Vertical Back Porch */
-#define         AT91_LCDC_VPW           (0x3f << 16)    /* Vertical Synchronization Pulse Width */
-#define         AT91_LCDC_VHDLY         (0xf  << 24)    /* Vertical to Horizontal Delay */
-
-#define AT91_LCDC_TIM2          0x080c          /* LCD Timing Register 2 */
-#define         AT91_LCDC_HBP           (0xff  <<  0)   /* Horizontal Back Porch */
-#define         AT91_LCDC_HPW           (0x3f  <<  8)   /* Horizontal Synchronization Pulse Width */
-#define         AT91_LCDC_HFP           (0x7ff << 21)   /* Horizontal Front Porch */
-
-#define AT91_LCDC_LCDFRMCFG     0x0810          /* LCD Frame Configuration Register */
-#define         AT91_LCDC_LINEVAL       (0x7ff <<  0)   /* Vertical Size of LCD Module */
-#define         AT91_LCDC_HOZVAL        (0x7ff << 21)   /* Horizontal Size of LCD Module */
-
-#define AT91_LCDC_FIFO          0x0814          /* LCD FIFO Register */
-#define         AT91_LCDC_FIFOTH        (0xffff)        /* FIFO Threshold */
-
-#define AT91_LCDC_DP1_2         0x081c          /* Dithering Pattern DP1_2 Register */
-#define AT91_LCDC_DP4_7         0x0820          /* Dithering Pattern DP4_7 Register */
-#define AT91_LCDC_DP3_5         0x0824          /* Dithering Pattern DP3_5 Register */
-#define AT91_LCDC_DP2_3         0x0828          /* Dithering Pattern DP2_3 Register */
-#define AT91_LCDC_DP5_7         0x082c          /* Dithering Pattern DP5_7 Register */
-#define AT91_LCDC_DP3_4         0x0830          /* Dithering Pattern DP3_4 Register */
-#define AT91_LCDC_DP4_5         0x0834          /* Dithering Pattern DP4_5 Register */
-#define AT91_LCDC_DP6_7         0x0838          /* Dithering Pattern DP6_7 Register */
-#define         AT91_LCDC_DP1_2_VAL     (0xff)
-#define         AT91_LCDC_DP4_7_VAL     (0xfffffff)
-#define         AT91_LCDC_DP3_5_VAL     (0xfffff)
-#define         AT91_LCDC_DP2_3_VAL     (0xfff)
-#define         AT91_LCDC_DP5_7_VAL     (0xfffffff)
-#define         AT91_LCDC_DP3_4_VAL     (0xffff)
-#define         AT91_LCDC_DP4_5_VAL     (0xfffff)
-#define         AT91_LCDC_DP6_7_VAL     (0xfffffff)
-
-#define AT91_LCDC_PWRCON        0x083c          /* Power Control Register */
-#define         AT91_LCDC_PWR           (1    <<  0)    /* LCD Module Power Control */
-#define         AT91_LCDC_GUARDT        (0x7f <<  1)    /* Delay in Frame Period */
-#define         AT91_LCDC_BUSY          (1    << 31)    /* LCD Busy */
-
-#define AT91_LCDC_CONTRAST_CTR  0x0840          /* Contrast Control Register */
-#define         AT91_LCDC_PS            (3 << 0)        /* Contrast Counter Prescaler */
-#define                 AT91_LCDC_PS_DIV1               (0 << 0)
-#define                 AT91_LCDC_PS_DIV2               (1 << 0)
-#define                 AT91_LCDC_PS_DIV4               (2 << 0)
-#define                 AT91_LCDC_PS_DIV8               (3 << 0)
-#define         AT91_LCDC_POL           (1 << 2)        /* Polarity of output Pulse */
-#define                 AT91_LCDC_POL_NEGATIVE          (0 << 2)
-#define                 AT91_LCDC_POL_POSITIVE          (1 << 2)
-#define         AT91_LCDC_ENA           (1 << 3)        /* PWM generator Control */
-#define                 AT91_LCDC_ENA_PWMDISABLE        (0 << 3)
-#define                 AT91_LCDC_ENA_PWMENABLE         (1 << 3)
-
-#define AT91_LCDC_CONTRAST_VAL  0x0844          /* Contrast Value Register */
-#define         AT91_LCDC_CVAL          (0xff)          /* PWM compare value */
-
-#define AT91_LCDC_IER           0x0848          /* Interrupt Enable Register */
-#define AT91_LCDC_IDR           0x084c          /* Interrupt Disable Register */
-#define AT91_LCDC_IMR           0x0850          /* Interrupt Mask Register */
-#define AT91_LCDC_ISR           0x0854          /* Interrupt Enable Register */
-#define AT91_LCDC_ICR           0x0858          /* Interrupt Clear Register */
-#define         AT91_LCDC_LNI           (1 << 0)        /* Line Interrupt */
-#define         AT91_LCDC_LSTLNI        (1 << 1)        /* Last Line Interrupt */
-#define         AT91_LCDC_EOFI          (1 << 2)        /* DMA End Of Frame Interrupt */
-#define         AT91_LCDC_UFLWI         (1 << 4)        /* FIFO Underflow Interrupt */
-#define         AT91_LCDC_OWRI          (1 << 5)        /* FIFO Overwrite Interrupt */
-#define         AT91_LCDC_MERI          (1 << 6)        /* DMA Memory Error Interrupt */
-
-#define AT91_LCDC_LUT_(n)       (0x0c00 + ((n)*4))      /* Palette Entry 0..255 */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 33ff5b6798ee..52cd8e5dabc9 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -25,6 +25,7 @@
 #define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
 #define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
+#define         AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
 #define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
 #define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
@@ -37,7 +38,9 @@
 #define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
 #define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
 
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
+#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
+
+#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
 #define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
 #define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
@@ -52,6 +55,10 @@
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
 #define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
+#define                 AT91_PMC_USBDIV_1               (0 << 28)
+#define                 AT91_PMC_USBDIV_2               (1 << 28)
+#define                 AT91_PMC_USBDIV_4               (2 << 28)
 #define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
 
 #define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h
index bae1103fbbb2..39a32633b275 100644
--- a/include/asm-arm/arch-at91/at91_rtt.h
+++ b/include/asm-arm/arch-at91/at91_rtt.h
@@ -13,19 +13,19 @@
 #ifndef AT91_RTT_H
 #define AT91_RTT_H
 
-#define AT91_RTT_MR             (AT91_RTT + 0x00)       /* Real-time Mode Register */
+#define AT91_RTT_MR             0x00                    /* Real-time Mode Register */
 #define         AT91_RTT_RTPRES         (0xffff << 0)           /* Real-time Timer Prescaler Value */
 #define         AT91_RTT_ALMIEN         (1 << 16)               /* Alarm Interrupt Enable */
 #define         AT91_RTT_RTTINCIEN      (1 << 17)               /* Real Time Timer Increment Interrupt Enable */
 #define         AT91_RTT_RTTRST         (1 << 18)               /* Real Time Timer Restart */
 
-#define AT91_RTT_AR             (AT91_RTT + 0x04)       /* Real-time Alarm Register */
+#define AT91_RTT_AR             0x04                    /* Real-time Alarm Register */
 #define         AT91_RTT_ALMV           (0xffffffff)            /* Alarm Value */
 
-#define AT91_RTT_VR             (AT91_RTT + 0x08)       /* Real-time Value Register */
+#define AT91_RTT_VR             0x08                    /* Real-time Value Register */
 #define         AT91_RTT_CRTV           (0xffffffff)            /* Current Real-time Value */
 
-#define AT91_RTT_SR             (AT91_RTT + 0x0c)       /* Real-time Status Register */
+#define AT91_RTT_SR             0x0c                    /* Real-time Status Register */
 #define         AT91_RTT_ALMS           (1 << 0)                /* Real-time Alarm Status */
 #define         AT91_RTT_RTTINC         (1 << 1)                /* Real-time Timer Increment */
 
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h
index ca9a90733456..f9f2e3cd95c5 100644
--- a/include/asm-arm/arch-at91/at91_twi.h
+++ b/include/asm-arm/arch-at91/at91_twi.h
@@ -21,6 +21,8 @@
 #define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
 #define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
 #define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
+#define         AT91_TWI_SVEN           (1 <<  4)       /* Slave Transfer Enable [SAM9260 only] */
+#define         AT91_TWI_SVDIS          (1 <<  5)       /* Slave Transfer Disable [SAM9260 only] */
 #define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
 
 #define AT91_TWI_MMR            0x04            /* Master Mode Register */
@@ -32,6 +34,9 @@
 #define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
 #define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
 
+#define AT91_TWI_SMR            0x08            /* Slave Mode Register [SAM9260 only] */
+#define         AT91_TWI_SADR           (0x7f << 16)    /* Slave Address */
+
 #define AT91_TWI_IADR           0x0c            /* Internal Address Register */
 
 #define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
@@ -43,9 +48,15 @@
 #define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
 #define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
 #define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
+#define         AT91_TWI_SVREAD         (1 <<  3)       /* Slave Read [SAM9260 only] */
+#define         AT91_TWI_SVACC          (1 <<  4)       /* Slave Access [SAM9260 only] */
+#define         AT91_TWI_GACC           (1 <<  5)       /* General Call Access [SAM9260 only] */
 #define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
 #define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
 #define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
+#define         AT91_TWI_ARBLST         (1 <<  9)       /* Arbitration Lost [SAM9260 only] */
+#define         AT91_TWI_SCLWS          (1 << 10)       /* Clock Wait State [SAM9260 only] */
+#define         AT91_TWI_EOSACC         (1 << 11)       /* End of Slave Address [SAM9260 only] */
 
 #define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
 #define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
new file mode 100644
index 000000000000..73e1fcf4a0aa
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -0,0 +1,121 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9.h
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2007 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_H
+#define AT91CAP9_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91CAP9_ID_PIOABCD     2       /* Parallel IO Controller A, B, C and D */
+#define AT91CAP9_ID_MPB0        3       /* MP Block Peripheral 0 */
+#define AT91CAP9_ID_MPB1        4       /* MP Block Peripheral 1 */
+#define AT91CAP9_ID_MPB2        5       /* MP Block Peripheral 2 */
+#define AT91CAP9_ID_MPB3        6       /* MP Block Peripheral 3 */
+#define AT91CAP9_ID_MPB4        7       /* MP Block Peripheral 4 */
+#define AT91CAP9_ID_US0         8       /* USART 0 */
+#define AT91CAP9_ID_US1         9       /* USART 1 */
+#define AT91CAP9_ID_US2         10      /* USART 2 */
+#define AT91CAP9_ID_MCI0        11      /* Multimedia Card Interface 0 */
+#define AT91CAP9_ID_MCI1        12      /* Multimedia Card Interface 1 */
+#define AT91CAP9_ID_CAN         13      /* CAN */
+#define AT91CAP9_ID_TWI         14      /* Two-Wire Interface */
+#define AT91CAP9_ID_SPI0        15      /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SPI1        16      /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SSC0        17      /* Serial Synchronous Controller 0 */
+#define AT91CAP9_ID_SSC1        18      /* Serial Synchronous Controller 1 */
+#define AT91CAP9_ID_AC97C       19      /* AC97 Controller */
+#define AT91CAP9_ID_TCB         20      /* Timer Counter 0, 1 and 2 */
+#define AT91CAP9_ID_PWMC        21      /* Pulse Width Modulation Controller */
+#define AT91CAP9_ID_EMAC        22      /* Ethernet */
+#define AT91CAP9_ID_AESTDES     23      /* Advanced Encryption Standard, Triple DES */
+#define AT91CAP9_ID_ADC         24      /* Analog-to-Digital Converter */
+#define AT91CAP9_ID_ISI         25      /* Image Sensor Interface */
+#define AT91CAP9_ID_LCDC        26      /* LCD Controller */
+#define AT91CAP9_ID_DMA         27      /* DMA Controller */
+#define AT91CAP9_ID_UDPHS       28      /* USB High Speed Device Port */
+#define AT91CAP9_ID_UHP         29      /* USB Host Port */
+#define AT91CAP9_ID_IRQ0        30      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91CAP9_ID_IRQ1        31      /* Advanced Interrupt Controller (IRQ1) */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91CAP9_BASE_UDPHS             0xfff78000
+#define AT91CAP9_BASE_TCB0              0xfff7c000
+#define AT91CAP9_BASE_TC0               0xfff7c000
+#define AT91CAP9_BASE_TC1               0xfff7c040
+#define AT91CAP9_BASE_TC2               0xfff7c080
+#define AT91CAP9_BASE_MCI0              0xfff80000
+#define AT91CAP9_BASE_MCI1              0xfff84000
+#define AT91CAP9_BASE_TWI               0xfff88000
+#define AT91CAP9_BASE_US0               0xfff8c000
+#define AT91CAP9_BASE_US1               0xfff90000
+#define AT91CAP9_BASE_US2               0xfff94000
+#define AT91CAP9_BASE_SSC0              0xfff98000
+#define AT91CAP9_BASE_SSC1              0xfff9c000
+#define AT91CAP9_BASE_AC97C             0xfffa0000
+#define AT91CAP9_BASE_SPI0              0xfffa4000
+#define AT91CAP9_BASE_SPI1              0xfffa8000
+#define AT91CAP9_BASE_CAN               0xfffac000
+#define AT91CAP9_BASE_PWMC              0xfffb8000
+#define AT91CAP9_BASE_EMAC              0xfffbc000
+#define AT91CAP9_BASE_ADC               0xfffc0000
+#define AT91CAP9_BASE_ISI               0xfffc4000
+#define AT91_BASE_SYS                   0xffffe200
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
+#define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC    (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
+#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDC       (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+/*
+ * Internal Memory.
+ */
+#define AT91CAP9_SRAM_BASE      0x00100000      /* Internal SRAM base address */
+#define AT91CAP9_SRAM_SIZE      (32 * SZ_1K)    /* Internal SRAM size (32Kb) */
+
+#define AT91CAP9_ROM_BASE       0x00400000      /* Internal ROM base address */
+#define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
+
+#define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
+#define AT91CAP9_UDPHS_BASE     0x00600000      /* USB High Speed Device Port */
+#define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
+
+#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
new file mode 100644
index 000000000000..a641686b6c3d
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -0,0 +1,132 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9_matrix.h
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_MATRIX_H
+#define AT91CAP9_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG8       (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
+#define AT91_MATRIX_SCFG9       (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS8       (AT91_MATRIX + 0xC0)    /* Priority Register A for Slave 8 */
+#define AT91_MATRIX_PRBS8       (AT91_MATRIX + 0xC4)    /* Priority Register B for Slave 8 */
+#define AT91_MATRIX_PRAS9       (AT91_MATRIX + 0xC8)    /* Priority Register A for Slave 9 */
+#define AT91_MATRIX_PRBS9       (AT91_MATRIX + 0xCC)    /* Priority Register B for Slave 9 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
+#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
+#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
+#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define         AT91_MATRIX_RCB2                (1 << 2)
+#define         AT91_MATRIX_RCB3                (1 << 3)
+#define         AT91_MATRIX_RCB4                (1 << 4)
+#define         AT91_MATRIX_RCB5                (1 << 5)
+#define         AT91_MATRIX_RCB6                (1 << 6)
+#define         AT91_MATRIX_RCB7                (1 << 7)
+#define         AT91_MATRIX_RCB8                (1 << 8)
+#define         AT91_MATRIX_RCB9                (1 << 9)
+#define         AT91_MATRIX_RCB10               (1 << 10)
+#define         AT91_MATRIX_RCB11               (1 << 11)
+
+#define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
+#define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_BCRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
+#define                 AT91_MATRIX_EBI_CS4A_SMC_CF1            (1 << 4)
+#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
+#define                 AT91_MATRIX_EBI_CS5A_SMC_CF2            (1 << 5)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_EBI_DQSPDC          (1 << 9)        /* Data Qualifier Strobe Pull-Down Configuration */
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+
+#define AT91_MPBS2_SFR          (AT91_MATRIX + 0x12C)   /* MPBlock Slave 2 Special Function Register */
+#define AT91_MPBS3_SFR          (AT91_MATRIX + 0x130)   /* MPBlock Slave 3 Special Function Register */
+#define AT91_APB_SFR            (AT91_MATRIX + 0x134)   /* APB Bridge Special Function Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h
index aacb1e976422..a8e9fec6c735 100644
--- a/include/asm-arm/arch-at91/at91sam9260_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h
@@ -67,7 +67,7 @@
 #define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
 #define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
 #define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5 )       /* Chip Select 5 Assignment */
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
 #define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
 #define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
 #define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
index 6fc6e4be624e..72f6e668e414 100644
--- a/include/asm-arm/arch-at91/at91sam9263_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h
@@ -44,7 +44,7 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
 #define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
index b15f11b7c08d..84224174e6a1 100644
--- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -38,7 +38,7 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
 #define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index d96b10fd449f..dc189f01c5b3 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -33,12 +33,15 @@
 
 #include <linux/mtd/partitions.h>
 #include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/leds.h>
 #include <linux/spi/spi.h>
 
  /* USB Device */
 struct at91_udc_data {
         u8      vbus_pin;               /* high == host powering us */
-        u8      pullup_pin;             /* high == D+ pulled up */
+        u8      pullup_pin;             /* active == D+ pulled up */
+        u8      pullup_active_low;      /* true == pullup_pin is active low */
 };
 extern void __init at91_add_device_udc(struct at91_udc_data *data);
 
@@ -70,7 +73,7 @@ struct at91_eth_data {
 };
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
 #define eth_platform_data       at91_eth_data
 #endif
 
@@ -94,19 +97,29 @@ struct at91_nand_data {
 extern void __init at91_add_device_nand(struct at91_nand_data *data);
 
  /* I2C*/
-extern void __init at91_add_device_i2c(void);
+extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
 
  /* SPI */
 extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
 
  /* Serial */
+#define ATMEL_UART_CTS  0x01
+#define ATMEL_UART_RTS  0x02
+#define ATMEL_UART_DSR  0x04
+#define ATMEL_UART_DTR  0x08
+#define ATMEL_UART_DCD  0x10
+#define ATMEL_UART_RI   0x20
+
+extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
+extern void __init at91_set_serial_console(unsigned portnr);
+
 struct at91_uart_config {
         unsigned short  console_tty;    /* tty number of serial console */
         unsigned short  nr_tty;         /* number of serial tty's */
         short           tty_map[];      /* map UART to tty number */
 };
 extern struct platform_device *atmel_default_console_device;
-extern void __init at91_init_serial(struct at91_uart_config *config);
+extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
 
 struct atmel_uart_data {
         short           use_dma_tx;     /* use transmit DMA? */
@@ -115,6 +128,23 @@ struct atmel_uart_data {
 };
 extern void __init at91_add_device_serial(void);
 
+/*
+ * SSC -- accessed through ssc_request(id).  Drivers don't bind to SSC
+ * platform devices.  Their SSC ID is part of their configuration data,
+ * along with information about which SSC signals they should use.
+ */
+#define ATMEL_SSC_TK    0x01
+#define ATMEL_SSC_TF    0x02
+#define ATMEL_SSC_TD    0x04
+#define ATMEL_SSC_TX    (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
+
+#define ATMEL_SSC_RK    0x10
+#define ATMEL_SSC_RF    0x20
+#define ATMEL_SSC_RD    0x40
+#define ATMEL_SSC_RX    (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
+
+extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
+
  /* LCD Controller */
 struct atmel_lcdfb_info;
 extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
@@ -125,9 +155,14 @@ struct atmel_ac97_data {
 };
 extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
 
+ /* ISI */
+extern void __init at91_add_device_isi(void);
+
  /* LEDs */
-extern u8 at91_leds_cpu;
-extern u8 at91_leds_timer;
 extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
+extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
+
+/* FIXME: this needs a better location, but gets stuff building again */
+extern int at91_suspend_entering_slow_clock(void);
 
 #endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 080cbb401a87..7145166826a2 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,13 +21,13 @@
 #define ARCH_ID_AT91SAM9260     0x019803a0
 #define ARCH_ID_AT91SAM9261     0x019703a0
 #define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9RL64    0x019b03a0
+#define ARCH_ID_AT91CAP9        0x039A03A0
 
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
 
-#define ARCH_ID_AT91SAM9RL64    0x019b03a0
-
 #define ARCH_ID_AT91M40800      0x14080044
 #define ARCH_ID_AT91R40807      0x44080746
 #define ARCH_ID_AT91M40807      0x14080745
@@ -81,6 +81,11 @@ static inline unsigned long at91_arch_identify(void)
 #define cpu_is_at91sam9rl()     (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT91CAP9
+#define cpu_is_at91cap9()       (at91_cpu_identify() == ARCH_ID_AT91CAP9)
+#else
+#define cpu_is_at91cap9()       (0)
+#endif
 
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S
index cc1d850a0788..1005eee6219b 100644
--- a/include/asm-arm/arch-at91/entry-macro.S
+++ b/include/asm-arm/arch-at91/entry-macro.S
@@ -17,13 +17,13 @@
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
         .endm
 
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
 
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
         ldr     \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)]     @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
         ldr     \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)]   @ read interrupt source number
         teq     \irqstat, #0                                    @ ISR is 0 when no current interrupt, or spurious interrupt
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 8f1cdd38a969..2c826d8247a3 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -26,6 +26,8 @@
 #include <asm/arch/at91sam9263.h>
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
 #include <asm/arch/at91sam9rl.h>
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <asm/arch/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <asm/arch/at91x40.h>
 #else
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index a310698fb4da..f1933b0fa43f 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -42,6 +42,11 @@
 #define AT91SAM9_MASTER_CLOCK   100000000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
+#elif defined(CONFIG_ARCH_AT91CAP9)
+
+#define AT91CAP9_MASTER_CLOCK   100000000
+#define CLOCK_TICK_RATE         (AT91CAP9_MASTER_CLOCK/16)
+
 #elif defined(CONFIG_ARCH_AT91X40)
 
 #define AT91X40_MASTER_CLOCK    40000000
diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h
index ea24a0e0bfd6..ff8de30b2fb3 100644
--- a/include/asm-arm/arch-davinci/gpio.h
+++ b/include/asm-arm/arch-davinci/gpio.h
@@ -13,6 +13,9 @@
 #ifndef __DAVINCI_GPIO_H
 #define __DAVINCI_GPIO_H
 
+#include <linux/io.h>
+#include <asm/hardware.h>
+
 /*
  * basic gpio routines
  *
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h
index 1ee14a14cba0..9b1864bbd9a8 100644
--- a/include/asm-arm/arch-ep93xx/gpio.h
+++ b/include/asm-arm/arch-ep93xx/gpio.h
@@ -5,16 +5,6 @@
 #ifndef __ASM_ARCH_GPIO_H
 #define __ASM_ARCH_GPIO_H
 
-#define GPIO_IN                         0
-#define GPIO_OUT                        1
-
-#define EP93XX_GPIO_LOW                 0
-#define EP93XX_GPIO_HIGH                1
-
-extern void gpio_line_config(int line, int direction);
-extern int  gpio_line_get(int line);
-extern void gpio_line_set(int line, int value);
-
 /* GPIO port A.  */
 #define EP93XX_GPIO_LINE_A(x)           ((x) + 0)
 #define EP93XX_GPIO_LINE_EGPIO0         EP93XX_GPIO_LINE_A(0)
@@ -38,7 +28,7 @@ extern void gpio_line_set(int line, int value);
 #define EP93XX_GPIO_LINE_EGPIO15        EP93XX_GPIO_LINE_B(7)
 
 /* GPIO port C.  */
-#define EP93XX_GPIO_LINE_C(x)           ((x) + 16)
+#define EP93XX_GPIO_LINE_C(x)           ((x) + 40)
 #define EP93XX_GPIO_LINE_ROW0           EP93XX_GPIO_LINE_C(0)
 #define EP93XX_GPIO_LINE_ROW1           EP93XX_GPIO_LINE_C(1)
 #define EP93XX_GPIO_LINE_ROW2           EP93XX_GPIO_LINE_C(2)
@@ -71,7 +61,7 @@ extern void gpio_line_set(int line, int value);
 #define EP93XX_GPIO_LINE_IDEDA2         EP93XX_GPIO_LINE_E(7)
 
 /* GPIO port F.  */
-#define EP93XX_GPIO_LINE_F(x)           ((x) + 40)
+#define EP93XX_GPIO_LINE_F(x)           ((x) + 16)
 #define EP93XX_GPIO_LINE_WP             EP93XX_GPIO_LINE_F(0)
 #define EP93XX_GPIO_LINE_MCCD1          EP93XX_GPIO_LINE_F(1)
 #define EP93XX_GPIO_LINE_MCCD2          EP93XX_GPIO_LINE_F(2)
@@ -103,5 +93,49 @@ extern void gpio_line_set(int line, int value);
 #define EP93XX_GPIO_LINE_DD6            EP93XX_GPIO_LINE_H(6)
 #define EP93XX_GPIO_LINE_DD7            EP93XX_GPIO_LINE_H(7)
 
+/* maximum value for gpio line identifiers */
+#define EP93XX_GPIO_LINE_MAX            EP93XX_GPIO_LINE_H(7)
+
+/* maximum value for irq capable line identifiers */
+#define EP93XX_GPIO_LINE_MAX_IRQ        EP93XX_GPIO_LINE_F(7)
+
+/* new generic GPIO API - see Documentation/gpio.txt */
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        if (gpio > EP93XX_GPIO_LINE_MAX)
+                return -EINVAL;
+        return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+}
+
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+
+/*
+ * Map GPIO A0..A7  (0..7)  to irq 64..71,
+ *          B0..B7  (7..15) to irq 72..79, and
+ *          F0..F7 (16..24) to irq 80..87.
+ */
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
+                return 64 + gpio;
+
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq - gpio_to_irq(0);
+}
 
 #endif
diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h
index 2a8c63638c5e..53d4a68bfc88 100644
--- a/include/asm-arm/arch-ep93xx/irqs.h
+++ b/include/asm-arm/arch-ep93xx/irqs.h
@@ -67,12 +67,6 @@
 #define IRQ_EP93XX_SAI                  60
 #define EP93XX_VIC2_VALID_IRQ_MASK      0x1fffffff
 
-/*
- * Map GPIO A0..A7 to irq 64..71, B0..B7 to 72..79, and
- * F0..F7 to 80..87.
- */
-#define IRQ_EP93XX_GPIO(x)              (64 + (((x) + (((x) >> 2) & 8)) & 0x1f))
-
 #define NR_EP93XX_IRQS                  (64 + 24)
 
 #define EP93XX_BOARD_IRQ(x)             (NR_EP93XX_IRQS + (x))
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h
index e69639585721..27c580898958 100644
--- a/include/asm-arm/arch-ixp23xx/irqs.h
+++ b/include/asm-arm/arch-ixp23xx/irqs.h
@@ -153,7 +153,7 @@
  */
 #define NR_IXP23XX_MACH_IRQS            32
 
-#define NR_IRQS                         NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS
+#define NR_IRQS                         (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS)
 
 #define IXP23XX_MACH_IRQ(irq)           (NR_IXP23XX_IRQ + (irq))
 
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index eeeea90cd5a9..9c5d2357aff3 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -61,13 +61,13 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
         if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
                 return __arm_ioremap(addr, size, mtype);
 
-        return (void *)addr;
+        return (void __iomem *)addr;
 }
 
 static inline void
 __ixp4xx_iounmap(void __iomem *addr)
 {
-        if ((u32)addr >= VMALLOC_START)
+        if ((__force u32)addr >= VMALLOC_START)
                 __iounmap(addr);
 }
 
@@ -141,9 +141,9 @@ __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
 static inline void 
 __ixp4xx_writel(u32 value, volatile void __iomem *p)
 {
-        u32 addr = (u32)p;
+        u32 addr = (__force u32)p;
         if (addr >= VMALLOC_START) {
-                __raw_writel(value, addr);
+                __raw_writel(value, p);
                 return;
         }
 
@@ -208,11 +208,11 @@ __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
 static inline unsigned long 
 __ixp4xx_readl(const volatile void __iomem *p)
 {
-        u32 addr = (u32)p;
+        u32 addr = (__force u32)p;
         u32 data;
 
         if (addr >= VMALLOC_START)
-                return __raw_readl(addr);
+                return __raw_readl(p);
 
         if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
                 return 0xffffffff;
@@ -438,7 +438,7 @@ __ixp4xx_ioread32(const void __iomem *addr)
                 return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
         else {
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                return le32_to_cpu(__raw_readl((u32)port));
+                return le32_to_cpu((__force __le32)__raw_readl(addr));
 #else
                 return (unsigned int)__ixp4xx_readl(addr);
 #endif
@@ -523,7 +523,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
                 __ixp4xx_outl(value, port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writel(cpu_to_le32(value), port);
+                __raw_writel((u32 __force)cpu_to_le32(value), addr);
 #else
                 __ixp4xx_writel(value, addr);
 #endif
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 2a44d3d67980..2ce28e3fd325 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -76,17 +76,6 @@ extern unsigned long ixp4xx_exp_bus_size;
 #define IXP4XX_UART_XTAL                14745600
 
 /*
- * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
- * used to 
- * Used as platform_data to provide GPIO pin information to the ixp42x
- * I2C driver.
- */
-struct ixp4xx_i2c_pins {
-        unsigned long sda_pin;
-        unsigned long scl_pin;
-};
-
-/*
  * This structure provide a means for the board setup code
  * to give information to th pata_ixp4xx driver. It is
  * passed as platform_data.
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h
index 57fcf9fc82e4..6b95d77aea19 100644
--- a/include/asm-arm/arch-ks8695/regs-gpio.h
+++ b/include/asm-arm/arch-ks8695/regs-gpio.h
@@ -49,5 +49,7 @@
 #define IOPC_TM_FALLING         (4)             /* Falling Edge Detection */
 #define IOPC_TM_EDGE            (6)             /* Both Edge Detection */
 
+/* Port Data Register */
+#define IOPD_(x)                (1 << (x))      /* Signal Level of GPIO Pin x */
 
 #endif
diff --git a/include/asm-arm/arch-msm/board.h b/include/asm-arm/arch-msm/board.h
new file mode 100644
index 000000000000..763051f8ba14
--- /dev/null
+++ b/include/asm-arm/arch-msm/board.h
@@ -0,0 +1,37 @@
+/* linux/include/asm-arm/arch-msm/board.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_BOARD_H
+#define __ASM_ARCH_MSM_BOARD_H
+
+#include <linux/types.h>
+
+/* platform device data structures */
+
+struct msm_mddi_platform_data
+{
+        void (*panel_power)(int on);
+        unsigned has_vsync_irq:1;
+};
+
+/* common init routines for use by arch/arm/mach-msm/board-*.c */
+
+void __init msm_add_devices(void);
+void __init msm_map_common_io(void);
+void __init msm_init_irq(void);
+void __init msm_init_gpio(void);
+
+#endif
diff --git a/include/asm-arm/arch-msm/debug-macro.S b/include/asm-arm/arch-msm/debug-macro.S
new file mode 100644
index 000000000000..393d5272e506
--- /dev/null
+++ b/include/asm-arm/arch-msm/debug-macro.S
@@ -0,0 +1,40 @@
+/* include/asm-arm/arch-msm7200/debug-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/hardware.h>
+#include <asm/arch/msm_iomap.h>
+
+        .macro  addruart,rx
+        @ see if the MMU is enabled and select appropriate base address
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1
+        ldreq   \rx, =MSM_UART1_PHYS
+        ldrne   \rx, =MSM_UART1_BASE
+        .endm
+
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #0x0C]
+        .endm
+
+        .macro  waituart,rd,rx
+        @ wait for TX_READY
+1:      ldr     \rd, [\rx, #0x08]
+        tst     \rd, #0x04
+        beq     1b
+        .endm
+
+        .macro  busyuart,rd,rx
+        .endm
diff --git a/include/asm-arm/arch-msm/dma.h b/include/asm-arm/arch-msm/dma.h
new file mode 100644
index 000000000000..e4b565b27b35
--- /dev/null
+++ b/include/asm-arm/arch-msm/dma.h
@@ -0,0 +1,151 @@
+/* linux/include/asm-arm/arch-msm/dma.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_DMA_H
+
+#include <linux/list.h>
+#include <asm/arch/msm_iomap.h>
+
+struct msm_dmov_cmd {
+        struct list_head list;
+        unsigned int cmdptr;
+        void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result);
+/*      void (*user_result_func)(struct msm_dmov_cmd *cmd); */
+};
+
+void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
+/* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */
+
+
+
+#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
+#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
+#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
+#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+
+/* only security domain 3 is available to the ARM11
+ * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
+ */
+
+#define DMOV_CMD_PTR(ch)      DMOV_SD3(0x000, ch)
+#define DMOV_CMD_LIST         (0 << 29) /* does not work */
+#define DMOV_CMD_PTR_LIST     (1 << 29) /* works */
+#define DMOV_CMD_INPUT_CFG    (2 << 29) /* untested */
+#define DMOV_CMD_OUTPUT_CFG   (3 << 29) /* untested */
+#define DMOV_CMD_ADDR(addr)   ((addr) >> 3)
+
+#define DMOV_RSLT(ch)         DMOV_SD3(0x040, ch)
+#define DMOV_RSLT_VALID       (1 << 31) /* 0 == host has empties result fifo */
+#define DMOV_RSLT_ERROR       (1 << 3)
+#define DMOV_RSLT_FLUSH       (1 << 2)
+#define DMOV_RSLT_DONE        (1 << 1)  /* top pointer done */
+#define DMOV_RSLT_USER        (1 << 0)  /* command with FR force result */
+
+#define DMOV_FLUSH0(ch)       DMOV_SD3(0x080, ch)
+#define DMOV_FLUSH1(ch)       DMOV_SD3(0x0C0, ch)
+#define DMOV_FLUSH2(ch)       DMOV_SD3(0x100, ch)
+#define DMOV_FLUSH3(ch)       DMOV_SD3(0x140, ch)
+#define DMOV_FLUSH4(ch)       DMOV_SD3(0x180, ch)
+#define DMOV_FLUSH5(ch)       DMOV_SD3(0x1C0, ch)
+
+#define DMOV_STATUS(ch)       DMOV_SD3(0x200, ch)
+#define DMOV_STATUS_RSLT_COUNT(n)    (((n) >> 29))
+#define DMOV_STATUS_CMD_COUNT(n)     (((n) >> 27) & 3)
+#define DMOV_STATUS_RSLT_VALID       (1 << 1)
+#define DMOV_STATUS_CMD_PTR_RDY      (1 << 0)
+
+#define DMOV_ISR              DMOV_SD3(0x380, 0)
+
+#define DMOV_CONFIG(ch)       DMOV_SD3(0x300, ch)
+#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
+#define DMOV_CONFIG_FORCE_FLUSH_RSLT   (1 << 1)
+#define DMOV_CONFIG_IRQ_EN             (1 << 0)
+
+/* channel assignments */
+
+#define DMOV_NAND_CHAN        7
+#define DMOV_NAND_CRCI_CMD    5
+#define DMOV_NAND_CRCI_DATA   4
+
+#define DMOV_SDC1_CHAN        8
+#define DMOV_SDC1_CRCI        6
+
+#define DMOV_SDC2_CHAN        8
+#define DMOV_SDC2_CRCI        7
+
+#define DMOV_TSIF_CHAN        10
+#define DMOV_TSIF_CRCI        10
+
+#define DMOV_USB_CHAN         11
+
+/* no client rate control ifc (eg, ram) */
+#define DMOV_NONE_CRCI        0
+
+
+/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
+ * is going to walk a list of 32bit pointers as described below.  Each
+ * pointer points to a *array* of dmov_s, etc structs.  The last pointer
+ * in the list is marked with CMD_PTR_LP.  The last struct in each array
+ * is marked with CMD_LC (see below).
+ */
+#define CMD_PTR_ADDR(addr)  ((addr) >> 3)
+#define CMD_PTR_LP          (1 << 31) /* last pointer */
+#define CMD_PTR_PT          (3 << 29) /* ? */
+
+/* Single Item Mode */
+typedef struct {
+        unsigned cmd;
+        unsigned src;
+        unsigned dst;
+        unsigned len;
+} dmov_s;
+
+/* Scatter/Gather Mode */
+typedef struct {
+        unsigned cmd;
+        unsigned src_dscr;
+        unsigned dst_dscr;
+        unsigned _reserved;
+} dmov_sg;
+
+/* bits for the cmd field of the above structures */
+
+#define CMD_LC      (1 << 31)  /* last command */
+#define CMD_FR      (1 << 22)  /* force result -- does not work? */
+#define CMD_OCU     (1 << 21)  /* other channel unblock */
+#define CMD_OCB     (1 << 20)  /* other channel block */
+#define CMD_TCB     (1 << 19)  /* ? */
+#define CMD_DAH     (1 << 18)  /* destination address hold -- does not work?*/
+#define CMD_SAH     (1 << 17)  /* source address hold -- does not work? */
+
+#define CMD_MODE_SINGLE     (0 << 0) /* dmov_s structure used */
+#define CMD_MODE_SG         (1 << 0) /* untested */
+#define CMD_MODE_IND_SG     (2 << 0) /* untested */
+#define CMD_MODE_BOX        (3 << 0) /* untested */
+
+#define CMD_DST_SWAP_BYTES  (1 << 14) /* exchange each byte n with byte n+1 */
+#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
+#define CMD_DST_SWAP_WORDS  (1 << 16) /* exchange each word n with word n+1 */
+
+#define CMD_SRC_SWAP_BYTES  (1 << 11) /* exchange each byte n with byte n+1 */
+#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
+#define CMD_SRC_SWAP_WORDS  (1 << 13) /* exchange each word n with word n+1 */
+
+#define CMD_DST_CRCI(n)     (((n) & 15) << 7)
+#define CMD_SRC_CRCI(n)     (((n) & 15) << 3)
+
+#endif
diff --git a/include/asm-arm/arch-msm/entry-macro.S b/include/asm-arm/arch-msm/entry-macro.S
new file mode 100644
index 000000000000..ee24aece4cb0
--- /dev/null
+++ b/include/asm-arm/arch-msm/entry-macro.S
@@ -0,0 +1,38 @@
+/* include/asm-arm/arch-msm7200/entry-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/arch/msm_iomap.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        @ enable imprecise aborts
+        cpsie   a
+        mov     \base, #MSM_VIC_BASE
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ 0xD0 has irq# or old irq# if the irq has been handled
+        @ 0xD4 has irq# or -1 if none pending *but* if you just
+        @ read 0xD4 you never get the first irq for some reason
+        ldr     \irqnr, [\base, #0xD0]
+        ldr     \irqnr, [\base, #0xD4]
+        cmp     \irqnr, #0xffffffff
+        .endm
diff --git a/include/asm-arm/arch-msm/hardware.h b/include/asm-arm/arch-msm/hardware.h
new file mode 100644
index 000000000000..89af2b70182f
--- /dev/null
+++ b/include/asm-arm/arch-msm/hardware.h
@@ -0,0 +1,18 @@
+/* linux/include/asm-arm/arch-msm/hardware.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_HARDWARE_H
+
+#endif
diff --git a/include/asm-arm/arch-msm/io.h b/include/asm-arm/arch-msm/io.h
new file mode 100644
index 000000000000..4645ae26b62a
--- /dev/null
+++ b/include/asm-arm/arch-msm/io.h
@@ -0,0 +1,33 @@
+/* include/asm-arm/arch-msm/io.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __arch_ioremap __msm_ioremap
+#define __arch_iounmap __iounmap
+
+void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)         __io(a)
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
new file mode 100644
index 000000000000..565430cfaa7e
--- /dev/null
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -0,0 +1,89 @@
+/* linux/include/asm-arm/arch-msm/irqs.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_H
+
+/* MSM ARM11 Interrupt Numbers */
+/* See 80-VE113-1 A, pp219-221     */
+
+#define INT_A9_M2A_0         0
+#define INT_A9_M2A_1         1
+#define INT_A9_M2A_2         2
+#define INT_A9_M2A_3         3
+#define INT_A9_M2A_4         4
+#define INT_A9_M2A_5         5
+#define INT_A9_M2A_6         6
+#define INT_GP_TIMER_EXP     7
+#define INT_DEBUG_TIMER_EXP  8
+#define INT_UART1            9
+#define INT_UART2            10
+#define INT_UART3            11
+#define INT_UART1_RX         12
+#define INT_UART2_RX         13
+#define INT_UART3_RX         14
+#define INT_USB_OTG          15
+#define INT_MDDI_PRI         16
+#define INT_MDDI_EXT         17
+#define INT_MDDI_CLIENT      18
+#define INT_MDP              19
+#define INT_GRAPHICS         20
+#define INT_ADM_AARM         21
+#define INT_ADSP_A11         22
+#define INT_ADSP_A9_A11      23
+#define INT_SDC1_0           24
+#define INT_SDC1_1           25
+#define INT_SDC2_0           26
+#define INT_SDC2_1           27
+#define INT_KEYSENSE         28
+#define INT_TCHSCRN_SSBI     29
+#define INT_TCHSCRN1         30
+#define INT_TCHSCRN2         31
+
+#define INT_GPIO_GROUP1      (32 + 0)
+#define INT_GPIO_GROUP2      (32 + 1)
+#define INT_PWB_I2C          (32 + 2)
+#define INT_SOFTRESET        (32 + 3)
+#define INT_NAND_WR_ER_DONE  (32 + 4)
+#define INT_NAND_OP_DONE     (32 + 5)
+#define INT_PBUS_ARM11       (32 + 6)
+#define INT_AXI_MPU_SMI      (32 + 7)
+#define INT_AXI_MPU_EBI1     (32 + 8)
+#define INT_AD_HSSD          (32 + 9)
+#define INT_ARM11_PMU        (32 + 10)
+#define INT_ARM11_DMA        (32 + 11)
+#define INT_TSIF_IRQ         (32 + 12)
+#define INT_UART1DM_IRQ      (32 + 13)
+#define INT_UART1DM_RX       (32 + 14)
+#define INT_USB_HS           (32 + 15)
+#define INT_SDC3_0           (32 + 16)
+#define INT_SDC3_1           (32 + 17)
+#define INT_SDC4_0           (32 + 18)
+#define INT_SDC4_1           (32 + 19)
+#define INT_UART2DM_RX       (32 + 20)
+#define INT_UART2DM_IRQ      (32 + 21)
+
+/* 22-31 are reserved */
+
+#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))
+
+#define NR_MSM_IRQS 64
+#define NR_GPIO_IRQS 122
+#define NR_BOARD_IRQS 64
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
+
+#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
+
+#endif
diff --git a/include/asm-arm/arch-msm/memory.h b/include/asm-arm/arch-msm/memory.h
new file mode 100644
index 000000000000..b5ce0e9ac86d
--- /dev/null
+++ b/include/asm-arm/arch-msm/memory.h
@@ -0,0 +1,27 @@
+/* linux/include/asm-arm/arch-msm/memory.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/* physical offset of RAM */
+#define PHYS_OFFSET             UL(0x10000000)
+
+/* bus address and physical addresses are identical */
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#endif
+
diff --git a/include/asm-arm/arch-msm/msm_iomap.h b/include/asm-arm/arch-msm/msm_iomap.h
new file mode 100644
index 000000000000..b8955cc26fec
--- /dev/null
+++ b/include/asm-arm/arch-msm/msm_iomap.h
@@ -0,0 +1,104 @@
+/* linux/include/asm-arm/arch-msm/msm_iomap.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_H
+#define __ASM_ARCH_MSM_IOMAP_H
+
+#include <asm/sizes.h>
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * MSM_VIC_BASE must be an value that can be loaded via a "mov"
+ * instruction, otherwise entry-macro.S will not compile.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define MSM_VIC_BASE          0xE0000000
+#define MSM_VIC_PHYS          0xC0000000
+#define MSM_VIC_SIZE          SZ_4K
+
+#define MSM_CSR_BASE          0xE0001000
+#define MSM_CSR_PHYS          0xC0100000
+#define MSM_CSR_SIZE          SZ_4K
+
+#define MSM_GPT_PHYS          MSM_CSR_PHYS
+#define MSM_GPT_BASE          MSM_CSR_BASE
+#define MSM_GPT_SIZE          SZ_4K
+
+#define MSM_DMOV_BASE         0xE0002000
+#define MSM_DMOV_PHYS         0xA9700000
+#define MSM_DMOV_SIZE         SZ_4K
+
+#define MSM_UART1_BASE        0xE0003000
+#define MSM_UART1_PHYS        0xA9A00000
+#define MSM_UART1_SIZE        SZ_4K
+
+#define MSM_UART2_BASE        0xE0004000
+#define MSM_UART2_PHYS        0xA9B00000
+#define MSM_UART2_SIZE        SZ_4K
+
+#define MSM_UART3_BASE        0xE0005000
+#define MSM_UART3_PHYS        0xA9C00000
+#define MSM_UART3_SIZE        SZ_4K
+
+#define MSM_I2C_BASE          0xE0006000
+#define MSM_I2C_PHYS          0xA9900000
+#define MSM_I2C_SIZE          SZ_4K
+
+#define MSM_GPIO1_BASE        0xE0007000
+#define MSM_GPIO1_PHYS        0xA9200000
+#define MSM_GPIO1_SIZE        SZ_4K
+
+#define MSM_GPIO2_BASE        0xE0008000
+#define MSM_GPIO2_PHYS        0xA9300000
+#define MSM_GPIO2_SIZE        SZ_4K
+
+#define MSM_HSUSB_BASE        0xE0009000
+#define MSM_HSUSB_PHYS        0xA0800000
+#define MSM_HSUSB_SIZE        SZ_4K
+
+#define MSM_CLK_CTL_BASE      0xE000A000
+#define MSM_CLK_CTL_PHYS      0xA8600000
+#define MSM_CLK_CTL_SIZE      SZ_4K
+
+#define MSM_PMDH_BASE         0xE000B000
+#define MSM_PMDH_PHYS         0xAA600000
+#define MSM_PMDH_SIZE         SZ_4K
+
+#define MSM_EMDH_BASE         0xE000C000
+#define MSM_EMDH_PHYS         0xAA700000
+#define MSM_EMDH_SIZE         SZ_4K
+
+#define MSM_MDP_BASE          0xE0010000
+#define MSM_MDP_PHYS          0xAA200000
+#define MSM_MDP_SIZE          0x000F0000
+
+#define MSM_SHARED_RAM_BASE   0xE0100000
+#define MSM_SHARED_RAM_PHYS   0x01F00000
+#define MSM_SHARED_RAM_SIZE   SZ_1M
+
+#endif
diff --git a/include/asm-arm/arch-msm/system.h b/include/asm-arm/arch-msm/system.h
new file mode 100644
index 000000000000..7c5544bdd0c7
--- /dev/null
+++ b/include/asm-arm/arch-msm/system.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-msm/system.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/hardware.h>
+
+void arch_idle(void);
+
+static inline void arch_reset(char mode)
+{
+        for (;;) ;  /* depends on IPC w/ other core */
+}
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
new file mode 100644
index 000000000000..154b23fb3599
--- /dev/null
+++ b/include/asm-arm/arch-msm/timex.h
@@ -0,0 +1,20 @@
+/* linux/include/asm-arm/arch-msm/timex.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_TIMEX_H
+
+#define CLOCK_TICK_RATE         1000000
+
+#endif
diff --git a/include/asm-arm/arch-msm/uncompress.h b/include/asm-arm/arch-msm/uncompress.h
new file mode 100644
index 000000000000..e91ed786ffec
--- /dev/null
+++ b/include/asm-arm/arch-msm/uncompress.h
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-msm/uncompress.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
+
+#include "hardware.h"
+
+static void putc(int c)
+{
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+}
+
+static inline void arch_decomp_wdog(void)
+{
+}
+
+#endif
diff --git a/include/asm-arm/arch-msm/vmalloc.h b/include/asm-arm/arch-msm/vmalloc.h
new file mode 100644
index 000000000000..60f8d910e825
--- /dev/null
+++ b/include/asm-arm/arch-msm/vmalloc.h
@@ -0,0 +1,22 @@
+/* linux/include/asm-arm/arch-msm/vmalloc.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_VMALLOC_H
+#define __ASM_ARCH_MSM_VMALLOC_H
+
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+
+#endif
+
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index b3cf33441f6e..56d2c98e143c 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -37,7 +37,7 @@
 #define OMAP1510P1_EMIFF_PRI_VALUE              0x00
 
 #define NR_FPGA_IRQS            24
-#define NR_IRQS                 IH_BOARD_BASE + NR_FPGA_IRQS
+#define NR_IRQS                 (IH_BOARD_BASE + NR_FPGA_IRQS)
 
 #ifndef __ASSEMBLY__
 void fpga_write(unsigned char val, int reg);
diff --git a/include/asm-arm/arch-omap/eac.h b/include/asm-arm/arch-omap/eac.h
index 6662cb02bafc..ccee3b0700b3 100644
--- a/include/asm-arm/arch-omap/eac.h
+++ b/include/asm-arm/arch-omap/eac.h
@@ -31,7 +31,6 @@
 #include <asm/arch/hardware.h>
 #include <asm/irq.h>
 
-#include <sound/driver.h>
 #include <sound/core.h>
 
 /* master codec clock source */
diff --git a/include/asm-arm/arch-omap/omap-alsa.h b/include/asm-arm/arch-omap/omap-alsa.h
index fcaf44c14714..faa0ed23d4ba 100644
--- a/include/asm-arm/arch-omap/omap-alsa.h
+++ b/include/asm-arm/arch-omap/omap-alsa.h
@@ -40,7 +40,6 @@
 #ifndef __OMAP_ALSA_H
 #define __OMAP_ALSA_H
 
-#include <sound/driver.h>
 #include <asm/arch/dma.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h
deleted file mode 100644
index b9aa2b3a3909..000000000000
--- a/include/asm-arm/arch-omap/tps65010.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* linux/include/asm-arm/arch-omap/tps65010.h
- *
- * Functions to access TPS65010 power management device.
- *
- * Copyright (C) 2004 Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_TPS65010_H
-#define __ASM_ARCH_TPS65010_H
-
-/*
- * ----------------------------------------------------------------------------
- * Registers, all 8 bits
- * ----------------------------------------------------------------------------
- */
-
-#define TPS_CHGSTATUS           0x01
-#       define  TPS_CHG_USB             (1 << 7)
-#       define  TPS_CHG_AC              (1 << 6)
-#       define  TPS_CHG_THERM           (1 << 5)
-#       define  TPS_CHG_TERM            (1 << 4)
-#       define  TPS_CHG_TAPER_TMO       (1 << 3)
-#       define  TPS_CHG_CHG_TMO         (1 << 2)
-#       define  TPS_CHG_PRECHG_TMO      (1 << 1)
-#       define  TPS_CHG_TEMP_ERR        (1 << 0)
-#define TPS_REGSTATUS           0x02
-#       define  TPS_REG_ONOFF           (1 << 7)
-#       define  TPS_REG_COVER           (1 << 6)
-#       define  TPS_REG_UVLO            (1 << 5)
-#       define  TPS_REG_NO_CHG          (1 << 4)        /* tps65013 */
-#       define  TPS_REG_PG_LD02         (1 << 3)
-#       define  TPS_REG_PG_LD01         (1 << 2)
-#       define  TPS_REG_PG_MAIN         (1 << 1)
-#       define  TPS_REG_PG_CORE         (1 << 0)
-#define TPS_MASK1               0x03
-#define TPS_MASK2               0x04
-#define TPS_ACKINT1             0x05
-#define TPS_ACKINT2             0x06
-#define TPS_CHGCONFIG           0x07
-#       define  TPS_CHARGE_POR          (1 << 7)        /* 65010/65012 */
-#       define  TPS65013_AUA            (1 << 7)        /* 65011/65013 */
-#       define  TPS_CHARGE_RESET        (1 << 6)
-#       define  TPS_CHARGE_FAST         (1 << 5)
-#       define  TPS_CHARGE_CURRENT      (3 << 3)
-#       define  TPS_VBUS_500MA          (1 << 2)
-#       define  TPS_VBUS_CHARGING       (1 << 1)
-#       define  TPS_CHARGE_ENABLE       (1 << 0)
-#define TPS_LED1_ON             0x08
-#define TPS_LED1_PER            0x09
-#define TPS_LED2_ON             0x0a
-#define TPS_LED2_PER            0x0b
-#define TPS_VDCDC1              0x0c
-#       define  TPS_ENABLE_LP           (1 << 3)
-#define TPS_VDCDC2              0x0d
-#define TPS_VREGS1              0x0e
-#       define  TPS_LDO2_ENABLE (1 << 7)
-#       define  TPS_LDO2_OFF    (1 << 6)
-#       define  TPS_VLDO2_3_0V  (3 << 4)
-#       define  TPS_VLDO2_2_75V (2 << 4)
-#       define  TPS_VLDO2_2_5V  (1 << 4)
-#       define  TPS_VLDO2_1_8V  (0 << 4)
-#       define  TPS_LDO1_ENABLE (1 << 3)
-#       define  TPS_LDO1_OFF    (1 << 2)
-#       define  TPS_VLDO1_3_0V  (3 << 0)
-#       define  TPS_VLDO1_2_75V (2 << 0)
-#       define  TPS_VLDO1_2_5V  (1 << 0)
-#       define  TPS_VLDO1_ADJ   (0 << 0)
-#define TPS_MASK3               0x0f
-#define TPS_DEFGPIO             0x10
-
-/*
- * ----------------------------------------------------------------------------
- * Macros used by exported functions
- * ----------------------------------------------------------------------------
- */
-
-#define LED1  1
-#define LED2  2
-#define OFF   0
-#define ON    1
-#define BLINK 2
-#define GPIO1 1
-#define GPIO2 2
-#define GPIO3 3
-#define GPIO4 4
-#define LOW   0
-#define HIGH  1
-
-/*
- * ----------------------------------------------------------------------------
- * Exported functions
- * ----------------------------------------------------------------------------
- */
-
-/* Draw from VBUS:
- *   0 mA -- DON'T DRAW (might supply power instead)
- * 100 mA -- usb unit load (slowest charge rate)
- * 500 mA -- usb high power (fast battery charge)
- */
-extern int tps65010_set_vbus_draw(unsigned mA);
-
-/* tps65010_set_gpio_out_value parameter:
- * gpio:  GPIO1, GPIO2, GPIO3 or GPIO4
- * value: LOW or HIGH
- */
-extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
-
-/* tps65010_set_led parameter:
- * led:  LED1 or LED2
- * mode: ON, OFF or BLINK
- */
-extern int tps65010_set_led(unsigned led, unsigned mode);
-
-/* tps65010_set_vib parameter:
- * value: ON or OFF
- */
-extern int tps65010_set_vib(unsigned value);
-
-/* tps65010_set_low_pwr parameter:
- * mode: ON or OFF
- */
-extern int tps65010_set_low_pwr(unsigned mode);
-
-/* tps65010_config_vregs1 parameter:
- * value to be written to VREGS1 register
- * Note: The complete register is written, set all bits you need
- */
-extern int tps65010_config_vregs1(unsigned value);
-
-/* tps65013_set_low_pwr parameter:
- * mode: ON or OFF
- */
-extern int tps65013_set_low_pwr(unsigned mode);
-
-#endif /*  __ASM_ARCH_TPS65010_H */
-
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
new file mode 100644
index 000000000000..e2a80641f214
--- /dev/null
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -0,0 +1,17 @@
+/*
+ * linux/include/asm-arm/arch-orion/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+        .macro  addruart,rx
+        mov   \rx, #0xf1000000
+        orr   \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-orion/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
new file mode 100644
index 000000000000..b76075a7e44b
--- /dev/null
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-orion/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Orion platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/orion.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =MAIN_IRQ_CAUSE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #0]           @ main cause
+        ldr     \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
+        mov     \irqnr, #0                      @ default irqnr
+        @ find cause bits that are unmasked
+        ands    \irqstat, \irqstat, \tmp        @ clear Z flag if any
+        clzne   \irqnr, \irqstat                @ calc irqnr
+        rsbne   \irqnr, \irqnr, #31
+        .endm
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion/gpio.h
new file mode 100644
index 000000000000..d66284f9a14c
--- /dev/null
+++ b/include/asm-arm/arch-orion/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * include/asm-arm/arch-orion/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+extern int gpio_request(unsigned pin, const char *label);
+extern void gpio_free(unsigned pin);
+extern int gpio_direction_input(unsigned pin);
+extern int gpio_direction_output(unsigned pin, int value);
+extern int gpio_get_value(unsigned pin);
+extern void gpio_set_value(unsigned pin, int value);
+extern void orion_gpio_set_blink(unsigned pin, int blink);
+extern void gpio_display(void);         /* debug */
+
+static inline int gpio_to_irq(int pin)
+{
+        return pin + IRQ_ORION_GPIO_START;
+}
+
+static inline int irq_to_gpio(int irq)
+{
+        return irq - IRQ_ORION_GPIO_START;
+}
+
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
new file mode 100644
index 000000000000..8a12d213fbdc
--- /dev/null
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -0,0 +1,24 @@
+/*
+ * include/asm-arm/arch-orion/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+#include "orion.h"
+
+#define PCI_MEMORY_VADDR        ORION_PCI_SYS_MEM_BASE
+#define PCI_IO_VADDR            ORION_PCI_SYS_IO_BASE
+
+#define pcibios_assign_all_busses()  1
+
+#define PCIBIOS_MIN_IO  0x1000
+#define PCIBIOS_MIN_MEM 0x01000000
+#define PCIMEM_BASE     PCI_MEMORY_VADDR /* mem base for VGA */
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h
new file mode 100644
index 000000000000..e0b8c39b9167
--- /dev/null
+++ b/include/asm-arm/arch-orion/io.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-arm/arch-orion/io.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include "orion.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define IO_SPACE_REMAP          ORION_PCI_SYS_IO_BASE
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h
new file mode 100644
index 000000000000..eea65ca6076a
--- /dev/null
+++ b/include/asm-arm/arch-orion/irqs.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-arm/arch-orion/irqs.h
+ *
+ * IRQ definitions for Orion SoC
+ *
+ *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ *  This file is licensed under the terms of the GNU General Public
+ *  License version 2. This program is licensed "as is" without any
+ *  warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H__
+#define __ASM_ARCH_IRQS_H__
+
+#include "orion.h"      /* need GPIO_MAX */
+
+/*
+ * Orion Main Interrupt Controller
+ */
+#define IRQ_ORION_BRIDGE        0
+#define IRQ_ORION_DOORBELL_H2C  1
+#define IRQ_ORION_DOORBELL_C2H  2
+#define IRQ_ORION_UART0         3
+#define IRQ_ORION_UART1         4
+#define IRQ_ORION_I2C           5
+#define IRQ_ORION_GPIO_0_7      6
+#define IRQ_ORION_GPIO_8_15     7
+#define IRQ_ORION_GPIO_16_23    8
+#define IRQ_ORION_GPIO_24_31    9
+#define IRQ_ORION_PCIE0_ERR     10
+#define IRQ_ORION_PCIE0_INT     11
+#define IRQ_ORION_USB1_CTRL     12
+#define IRQ_ORION_DEV_BUS_ERR   14
+#define IRQ_ORION_PCI_ERR       15
+#define IRQ_ORION_USB_BR_ERR    16
+#define IRQ_ORION_USB0_CTRL     17
+#define IRQ_ORION_ETH_RX        18
+#define IRQ_ORION_ETH_TX        19
+#define IRQ_ORION_ETH_MISC      20
+#define IRQ_ORION_ETH_SUM       21
+#define IRQ_ORION_ETH_ERR       22
+#define IRQ_ORION_IDMA_ERR      23
+#define IRQ_ORION_IDMA_0        24
+#define IRQ_ORION_IDMA_1        25
+#define IRQ_ORION_IDMA_2        26
+#define IRQ_ORION_IDMA_3        27
+#define IRQ_ORION_CESA          28
+#define IRQ_ORION_SATA          29
+#define IRQ_ORION_XOR0          30
+#define IRQ_ORION_XOR1          31
+
+/*
+ * Orion General Purpose Pins
+ */
+#define IRQ_ORION_GPIO_START    32
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
+
+#endif /* __ASM_ARCH_IRQS_H__ */
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion/memory.h
new file mode 100644
index 000000000000..d954dba87ced
--- /dev/null
+++ b/include/asm-arm/arch-orion/memory.h
@@ -0,0 +1,15 @@
+/*
+ * include/asm-arm/arch-orion/memory.h
+ *
+ * Marvell Orion memory definitions
+ */
+
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
new file mode 100644
index 000000000000..f787f752e58c
--- /dev/null
+++ b/include/asm-arm/arch-orion/orion.h
@@ -0,0 +1,143 @@
+/*
+ * include/asm-arm/arch-orion/orion.h
+ *
+ * Generic definitions of Orion SoC flavors:
+ *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_ORION_H__
+#define __ASM_ARCH_ORION_H__
+
+/*******************************************************************************
+ * Orion Address Map
+ * Use the same mapping (1:1 virtual:physical) of internal registers and
+ * PCI system (PCI+PCIE) for all machines.
+ * Each machine defines the rest of its mapping (e.g. device bus flashes)
+ ******************************************************************************/
+#define ORION_REGS_BASE         0xf1000000
+#define ORION_REGS_SIZE         SZ_1M
+
+#define ORION_PCI_SYS_MEM_BASE  0xe0000000
+#define ORION_PCIE_MEM_BASE     ORION_PCI_SYS_MEM_BASE
+#define ORION_PCIE_MEM_SIZE     SZ_128M
+#define ORION_PCI_MEM_BASE      (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
+#define ORION_PCI_MEM_SIZE      SZ_128M
+
+#define ORION_PCI_SYS_IO_BASE   0xf2000000
+#define ORION_PCIE_IO_BASE      ORION_PCI_SYS_IO_BASE
+#define ORION_PCIE_IO_SIZE      SZ_1M
+#define ORION_PCIE_IO_REMAP     (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
+#define ORION_PCI_IO_BASE       (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
+#define ORION_PCI_IO_SIZE       SZ_1M
+#define ORION_PCI_IO_REMAP      (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
+/* Relevant only for Orion-NAS */
+#define ORION_PCIE_WA_BASE      0xf0000000
+#define ORION_PCIE_WA_SIZE      SZ_16M
+
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+
+/*******************************************************************************
+ * Orion Registers Map
+ ******************************************************************************/
+#define ORION_DDR_REG_BASE      (ORION_REGS_BASE | 0x00000)
+#define ORION_DEV_BUS_REG_BASE  (ORION_REGS_BASE | 0x10000)
+#define ORION_BRIDGE_REG_BASE   (ORION_REGS_BASE | 0x20000)
+#define ORION_PCI_REG_BASE      (ORION_REGS_BASE | 0x30000)
+#define ORION_PCIE_REG_BASE     (ORION_REGS_BASE | 0x40000)
+#define ORION_USB0_REG_BASE     (ORION_REGS_BASE | 0x50000)
+#define ORION_ETH_REG_BASE      (ORION_REGS_BASE | 0x70000)
+#define ORION_SATA_REG_BASE     (ORION_REGS_BASE | 0x80000)
+#define ORION_USB1_REG_BASE     (ORION_REGS_BASE | 0xa0000)
+
+#define ORION_DDR_REG(x)        (ORION_DDR_REG_BASE | (x))
+#define ORION_DEV_BUS_REG(x)    (ORION_DEV_BUS_REG_BASE | (x))
+#define ORION_BRIDGE_REG(x)     (ORION_BRIDGE_REG_BASE | (x))
+#define ORION_PCI_REG(x)        (ORION_PCI_REG_BASE | (x))
+#define ORION_PCIE_REG(x)       (ORION_PCIE_REG_BASE | (x))
+#define ORION_USB0_REG(x)       (ORION_USB0_REG_BASE | (x))
+#define ORION_USB1_REG(x)       (ORION_USB1_REG_BASE | (x))
+#define ORION_ETH_REG(x)        (ORION_ETH_REG_BASE | (x))
+#define ORION_SATA_REG(x)       (ORION_SATA_REG_BASE | (x))
+
+/*******************************************************************************
+ * Device Bus Registers
+ ******************************************************************************/
+#define MPP_0_7_CTRL            ORION_DEV_BUS_REG(0x000)
+#define MPP_8_15_CTRL           ORION_DEV_BUS_REG(0x004)
+#define MPP_16_19_CTRL          ORION_DEV_BUS_REG(0x050)
+#define MPP_DEV_CTRL            ORION_DEV_BUS_REG(0x008)
+#define MPP_RESET_SAMPLE        ORION_DEV_BUS_REG(0x010)
+#define GPIO_OUT                ORION_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF            ORION_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN           ORION_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL             ORION_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN            ORION_DEV_BUS_REG(0x110)
+#define GPIO_EDGE_CAUSE         ORION_DEV_BUS_REG(0x114)
+#define GPIO_EDGE_MASK          ORION_DEV_BUS_REG(0x118)
+#define GPIO_LEVEL_MASK         ORION_DEV_BUS_REG(0x11c)
+#define DEV_BANK_0_PARAM        ORION_DEV_BUS_REG(0x45c)
+#define DEV_BANK_1_PARAM        ORION_DEV_BUS_REG(0x460)
+#define DEV_BANK_2_PARAM        ORION_DEV_BUS_REG(0x464)
+#define DEV_BANK_BOOT_PARAM     ORION_DEV_BUS_REG(0x46c)
+#define DEV_BUS_CTRL            ORION_DEV_BUS_REG(0x4c0)
+#define DEV_BUS_INT_CAUSE       ORION_DEV_BUS_REG(0x4d0)
+#define DEV_BUS_INT_MASK        ORION_DEV_BUS_REG(0x4d4)
+#define I2C_BASE                ORION_DEV_BUS_REG(0x1000)
+#define UART0_BASE              ORION_DEV_BUS_REG(0x2000)
+#define UART1_BASE              ORION_DEV_BUS_REG(0x2100)
+#define GPIO_MAX                32
+
+/***************************************************************************
+ * Orion CPU Bridge Registers
+ **************************************************************************/
+#define CPU_CONF                ORION_BRIDGE_REG(0x100)
+#define CPU_CTRL                ORION_BRIDGE_REG(0x104)
+#define CPU_RESET_MASK          ORION_BRIDGE_REG(0x108)
+#define CPU_SOFT_RESET          ORION_BRIDGE_REG(0x10c)
+#define POWER_MNG_CTRL_REG      ORION_BRIDGE_REG(0x11C)
+#define BRIDGE_CAUSE            ORION_BRIDGE_REG(0x110)
+#define BRIDGE_MASK             ORION_BRIDGE_REG(0x114)
+#define MAIN_IRQ_CAUSE          ORION_BRIDGE_REG(0x200)
+#define MAIN_IRQ_MASK           ORION_BRIDGE_REG(0x204)
+#define TIMER_CTRL              ORION_BRIDGE_REG(0x300)
+#define TIMER_VAL(x)            ORION_BRIDGE_REG(0x314 + ((x) * 8))
+#define TIMER_VAL_RELOAD(x)     ORION_BRIDGE_REG(0x310 + ((x) * 8))
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Helpers to access Orion registers
+ ******************************************************************************/
+#include <asm/types.h>
+#include <asm/io.h>
+
+#define orion_read(r)           __raw_readl(r)
+#define orion_write(r, val)     __raw_writel(val, r)
+
+/*
+ * These are not preempt safe. Locks, if needed, must be taken care by caller.
+ */
+#define orion_setbits(r, mask)  orion_write((r), orion_read(r) | (mask))
+#define orion_clrbits(r, mask)  orion_write((r), orion_read(r) & ~(mask))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_ORION_H__ */
diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/arch-orion/platform.h
new file mode 100644
index 000000000000..143c38e2fa0b
--- /dev/null
+++ b/include/asm-arm/arch-orion/platform.h
@@ -0,0 +1,25 @@
+/*
+ * asm-arm/arch-orion/platform.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H__
+#define __ASM_ARCH_PLATFORM_H__
+
+/*
+ * Device bus NAND private data
+ */
+struct orion_nand_data {
+        struct mtd_partition *parts;
+        u32 nr_parts;
+        u8 ale;         /* address line number connected to ALE */
+        u8 cle;         /* address line number connected to CLE */
+        u8 width;       /* buswidth */
+};
+
+#endif
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion/system.h
new file mode 100644
index 000000000000..17704c68f90e
--- /dev/null
+++ b/include/asm-arm/arch-orion/system.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-orion/system.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/orion.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable and issue soft reset
+         */
+        orion_setbits(CPU_RESET_MASK, (1 << 2));
+        orion_setbits(CPU_SOFT_RESET, 1);
+}
+
+#endif
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h
new file mode 100644
index 000000000000..26c2c91eecf0
--- /dev/null
+++ b/include/asm-arm/arch-orion/timex.h
@@ -0,0 +1,12 @@
+/*
+ * include/asm-arm/arch-orion/timex.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define ORION_TCLK              166666667
+#define CLOCK_TICK_RATE         ORION_TCLK
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
new file mode 100644
index 000000000000..a1a222fb438c
--- /dev/null
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-arm/arch-orion/uncompress.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/orion.h>
+
+#define MV_UART_LSR     ((volatile unsigned char *)(UART0_BASE + 0x14))
+#define MV_UART_THR     ((volatile unsigned char *)(UART0_BASE + 0x0))
+
+#define LSR_THRE        0x20
+
+static void putc(const char c)
+{
+        int j = 0x1000;
+        while (--j && !(*MV_UART_LSR & LSR_THRE))
+                barrier();
+        *MV_UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+static void orion_early_putstr(const char *ptr)
+{
+        char c;
+        while ((c = *ptr++) != '\0') {
+                if (c == '\n')
+                        putc('\r');
+                putc(c);
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h
new file mode 100644
index 000000000000..23e2a102fe0c
--- /dev/null
+++ b/include/asm-arm/arch-orion/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-orion/vmalloc.h
+ */
+
+#define VMALLOC_END       0xf0000000
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
index 17eccd720136..52bbe3bc25e1 100644
--- a/include/asm-arm/arch-pxa/audio.h
+++ b/include/asm-arm/arch-pxa/audio.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_ARCH_AUDIO_H__
 #define __ASM_ARCH_AUDIO_H__
 
-#include <sound/driver.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 
diff --git a/include/asm-arm/arch-pxa/colibri.h b/include/asm-arm/arch-pxa/colibri.h
new file mode 100644
index 000000000000..2ae373fb5675
--- /dev/null
+++ b/include/asm-arm/arch-pxa/colibri.h
@@ -0,0 +1,19 @@
+#ifndef _COLIBRI_H_
+#define _COLIBRI_H_
+
+/* physical memory regions */
+#define COLIBRI_FLASH_PHYS      (PXA_CS0_PHYS)  /* Flash region */
+#define COLIBRI_ETH_PHYS        (PXA_CS2_PHYS)  /* Ethernet DM9000 region */
+#define COLIBRI_SDRAM_BASE      0xa0000000      /* SDRAM region */
+
+/* virtual memory regions */
+#define COLIBRI_DISK_VIRT       0xF0000000      /* Disk On Chip region */
+
+/* size of flash */
+#define COLIBRI_FLASH_SIZE      0x02000000      /* Flash size 32 MB */
+
+/* Ethernet Controller Davicom DM9000 */
+#define GPIO_DM9000             114
+#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
+
+#endif /* _COLIBRI_H_ */
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
index e554caa0d18b..bf856503baf6 100644
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -104,7 +104,6 @@
  */
 extern struct platform_device corgiscoop_device;
 extern struct platform_device corgissp_device;
-extern struct platform_device corgifb_device;
 
 #endif /* __ASM_ARCH_CORGI_H  */
 
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index ab2d963e742a..e25558faa5a4 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -121,38 +121,32 @@
 
 #define cpu_is_pxa21x()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa21x(id);                    \
+                __cpu_is_pxa21x(read_cpuid_id());       \
         })
 
 #define cpu_is_pxa25x()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa25x(id);                    \
+                __cpu_is_pxa25x(read_cpuid_id());       \
         })
 
 #define cpu_is_pxa27x()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa27x(id);                    \
+                __cpu_is_pxa27x(read_cpuid_id());       \
         })
 
 #define cpu_is_pxa300()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa300(id);                    \
+                __cpu_is_pxa300(read_cpuid_id());       \
          })
 
 #define cpu_is_pxa310()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa310(id);                    \
+                __cpu_is_pxa310(read_cpuid_id());       \
          })
 
 #define cpu_is_pxa320()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa320(id);                    \
+                __cpu_is_pxa320(read_cpuid_id());       \
          })
 
 /*
@@ -174,14 +168,12 @@
 
 #define cpu_is_pxa2xx()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa2xx(id);                    \
+                __cpu_is_pxa2xx(read_cpuid_id());       \
          })
 
 #define cpu_is_pxa3xx()                                 \
         ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa3xx(id);                    \
+                __cpu_is_pxa3xx(read_cpuid_id());       \
          })
 
 /*
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
index e404b233d8a8..80596b013443 100644
--- a/include/asm-arm/arch-pxa/i2c.h
+++ b/include/asm-arm/arch-pxa/i2c.h
@@ -65,7 +65,13 @@ struct i2c_pxa_platform_data {
         unsigned int            slave_addr;
         struct i2c_slave_client *slave;
         unsigned int            class;
+        int                     use_pio;
 };
 
 extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
+
+#ifdef CONFIG_PXA27x
+extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
+#endif
+
 #endif
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index 6238dbf7a236..c562b972a4a6 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -13,7 +13,7 @@
 
 #define PXA_IRQ(x)      (x)
 
-#ifdef CONFIG_PXA27x
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
 #define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
 #define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
@@ -52,11 +52,27 @@
 #define IRQ_RTC1Hz      PXA_IRQ(30)     /* RTC HZ Clock Tick */
 #define IRQ_RTCAlrm     PXA_IRQ(31)     /* RTC Alarm */
 
-#ifdef CONFIG_PXA27x
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
 #define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
 #endif
 
+#ifdef CONFIG_PXA3xx
+#define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request */
+#define IRQ_CIR         PXA_IRQ(34)     /* Consumer IR */
+#define IRQ_TSI         PXA_IRQ(36)     /* Touch Screen Interface (PXA320) */
+#define IRQ_USIM2       PXA_IRQ(38)     /* USIM2 Controller */
+#define IRQ_GRPHICS     PXA_IRQ(39)     /* Graphics Controller */
+#define IRQ_MMC2        PXA_IRQ(41)     /* MMC2 Controller */
+#define IRQ_1WIRE       PXA_IRQ(44)     /* 1-Wire Controller */
+#define IRQ_NAND        PXA_IRQ(45)     /* NAND Controller */
+#define IRQ_USB2        PXA_IRQ(46)     /* USB 2.0 Device Controller */
+#define IRQ_WAKEUP0     PXA_IRQ(49)     /* EXT_WAKEUP0 */
+#define IRQ_WAKEUP1     PXA_IRQ(50)     /* EXT_WAKEUP1 */
+#define IRQ_DMEMC       PXA_IRQ(51)     /* Dynamic Memory Controller */
+#define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
+#endif
+
 #define PXA_GPIO_IRQ_BASE       (64)
 #define PXA_GPIO_IRQ_NUM        (128)
 
@@ -164,7 +180,8 @@
 #define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
 #elif defined(CONFIG_ARCH_LUBBOCK) || \
       defined(CONFIG_MACH_LOGICPD_PXA270) || \
-      defined(CONFIG_MACH_MAINSTONE)
+      defined(CONFIG_MACH_MAINSTONE) || \
+      defined(CONFIG_MACH_PCM027)
 #define NR_IRQS                 (IRQ_BOARD_END)
 #else
 #define NR_IRQS                 (IRQ_BOARD_START)
@@ -211,6 +228,13 @@
 #define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
 #define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
 
+/* phyCORE-PXA270 (PCM027) Interrupts */
+#define PCM027_IRQ(x)          (IRQ_BOARD_START + (x))
+#define PCM027_BTDET_IRQ       PCM027_IRQ(0)
+#define PCM027_FF_RI_IRQ       PCM027_IRQ(1)
+#define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
+#define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
+
 /* ITE8152 irqs */
 /* add IT8152 IRQs beyond BOARD_END */
 #ifdef CONFIG_PCI_HOST_ITE8152
diff --git a/include/asm-arm/arch-pxa/littleton.h b/include/asm-arm/arch-pxa/littleton.h
new file mode 100644
index 000000000000..79d209b826f4
--- /dev/null
+++ b/include/asm-arm/arch-pxa/littleton.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_ZYLONITE_H
+#define __ASM_ARCH_ZYLONITE_H
+
+#define LITTLETON_ETH_PHYS      0x30000000
+
+#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
new file mode 100644
index 000000000000..337f51f06b3a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/magician.h
@@ -0,0 +1,111 @@
+/*
+ * GPIO and IRQ definitions for HTC Magician PDA phones
+ *
+ * Copyright (c) 2007 Philipp Zabel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MAGICIAN_H_
+#define _MAGICIAN_H_
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * PXA GPIOs
+ */
+
+#define GPIO0_MAGICIAN_KEY_POWER                0
+#define GPIO9_MAGICIAN_UNKNOWN                  9
+#define GPIO10_MAGICIAN_GSM_IRQ                 10
+#define GPIO11_MAGICIAN_GSM_OUT1                11
+#define GPIO13_MAGICIAN_CPLD_IRQ                13
+#define GPIO18_MAGICIAN_UNKNOWN                 18
+#define GPIO22_MAGICIAN_VIBRA_EN                22
+#define GPIO26_MAGICIAN_GSM_POWER               26
+#define GPIO27_MAGICIAN_USBC_PUEN               27
+#define GPIO30_MAGICIAN_nCHARGE_EN              30
+#define GPIO37_MAGICIAN_KEY_HANGUP              37
+#define GPIO38_MAGICIAN_KEY_CONTACTS            38
+#define GPIO40_MAGICIAN_GSM_OUT2                40
+#define GPIO48_MAGICIAN_UNKNOWN                 48
+#define GPIO56_MAGICIAN_UNKNOWN                 56
+#define GPIO57_MAGICIAN_CAM_RESET               57
+#define GPIO83_MAGICIAN_nIR_EN                  83
+#define GPIO86_MAGICIAN_GSM_RESET               86
+#define GPIO87_MAGICIAN_GSM_SELECT              87
+#define GPIO90_MAGICIAN_KEY_CALENDAR            90
+#define GPIO91_MAGICIAN_KEY_CAMERA              91
+#define GPIO93_MAGICIAN_KEY_UP                  93
+#define GPIO94_MAGICIAN_KEY_DOWN                94
+#define GPIO95_MAGICIAN_KEY_LEFT                95
+#define GPIO96_MAGICIAN_KEY_RIGHT               96
+#define GPIO97_MAGICIAN_KEY_ENTER               97
+#define GPIO98_MAGICIAN_KEY_RECORD              98
+#define GPIO99_MAGICIAN_HEADPHONE_IN            99
+#define GPIO100_MAGICIAN_KEY_VOL_UP             100
+#define GPIO101_MAGICIAN_KEY_VOL_DOWN           101
+#define GPIO102_MAGICIAN_KEY_PHONE              102
+#define GPIO103_MAGICIAN_LED_KP                 103
+#define GPIO104_MAGICIAN_LCD_POWER_1            104
+#define GPIO105_MAGICIAN_LCD_POWER_2            105
+#define GPIO106_MAGICIAN_LCD_POWER_3            106
+#define GPIO107_MAGICIAN_DS1WM_IRQ              107
+#define GPIO108_MAGICIAN_GSM_READY              108
+#define GPIO114_MAGICIAN_UNKNOWN                114
+#define GPIO115_MAGICIAN_nPEN_IRQ               115
+#define GPIO116_MAGICIAN_nCAM_EN                116
+#define GPIO119_MAGICIAN_UNKNOWN                119
+#define GPIO120_MAGICIAN_UNKNOWN                120
+
+/*
+ * PXA GPIO alternate function mode & direction
+ */
+
+#define GPIO0_MAGICIAN_KEY_POWER_MD             (0 | GPIO_IN)
+#define GPIO9_MAGICIAN_UNKNOWN_MD               (9 | GPIO_IN)
+#define GPIO10_MAGICIAN_GSM_IRQ_MD              (10 | GPIO_IN)
+#define GPIO11_MAGICIAN_GSM_OUT1_MD             (11 | GPIO_OUT)
+#define GPIO13_MAGICIAN_CPLD_IRQ_MD             (13 | GPIO_IN)
+#define GPIO18_MAGICIAN_UNKNOWN_MD              (18 | GPIO_OUT)
+#define GPIO22_MAGICIAN_VIBRA_EN_MD             (22 | GPIO_OUT)
+#define GPIO26_MAGICIAN_GSM_POWER_MD            (26 | GPIO_OUT)
+#define GPIO27_MAGICIAN_USBC_PUEN_MD            (27 | GPIO_OUT)
+#define GPIO30_MAGICIAN_nCHARGE_EN_MD           (30 | GPIO_OUT)
+#define GPIO37_MAGICIAN_KEY_HANGUP_MD           (37 | GPIO_OUT)
+#define GPIO38_MAGICIAN_KEY_CONTACTS_MD         (38 | GPIO_OUT)
+#define GPIO40_MAGICIAN_GSM_OUT2_MD             (40 | GPIO_OUT)
+#define GPIO48_MAGICIAN_UNKNOWN_MD              (48 | GPIO_OUT)
+#define GPIO56_MAGICIAN_UNKNOWN_MD              (56 | GPIO_OUT)
+#define GPIO57_MAGICIAN_CAM_RESET_MD            (57 | GPIO_OUT)
+#define GPIO83_MAGICIAN_nIR_EN_MD               (83 | GPIO_OUT)
+#define GPIO86_MAGICIAN_GSM_RESET_MD            (86 | GPIO_OUT)
+#define GPIO87_MAGICIAN_GSM_SELECT_MD           (87 | GPIO_OUT)
+#define GPIO90_MAGICIAN_KEY_CALENDAR_MD         (90 | GPIO_OUT)
+#define GPIO91_MAGICIAN_KEY_CAMERA_MD           (91 | GPIO_OUT)
+#define GPIO93_MAGICIAN_KEY_UP_MD               (93 | GPIO_IN)
+#define GPIO94_MAGICIAN_KEY_DOWN_MD             (94 | GPIO_IN)
+#define GPIO95_MAGICIAN_KEY_LEFT_MD             (95 | GPIO_IN)
+#define GPIO96_MAGICIAN_KEY_RIGHT_MD            (96 | GPIO_IN)
+#define GPIO97_MAGICIAN_KEY_ENTER_MD            (97 | GPIO_IN)
+#define GPIO98_MAGICIAN_KEY_RECORD_MD           (98 | GPIO_IN)
+#define GPIO99_MAGICIAN_HEADPHONE_IN_MD         (99 | GPIO_IN)
+#define GPIO100_MAGICIAN_KEY_VOL_UP_MD          (100 | GPIO_IN)
+#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD        (101 | GPIO_IN)
+#define GPIO102_MAGICIAN_KEY_PHONE_MD           (102 | GPIO_IN)
+#define GPIO103_MAGICIAN_LED_KP_MD              (103 | GPIO_OUT)
+#define GPIO104_MAGICIAN_LCD_POWER_1_MD         (104 | GPIO_OUT)
+#define GPIO105_MAGICIAN_LCD_POWER_2_MD         (105 | GPIO_OUT)
+#define GPIO106_MAGICIAN_LCD_POWER_3_MD         (106 | GPIO_OUT)
+#define GPIO107_MAGICIAN_DS1WM_IRQ_MD           (107 | GPIO_IN)
+#define GPIO108_MAGICIAN_GSM_READY_MD           (108 | GPIO_IN)
+#define GPIO114_MAGICIAN_UNKNOWN_MD             (114 | GPIO_OUT)
+#define GPIO115_MAGICIAN_nPEN_IRQ_MD            (115 | GPIO_IN)
+#define GPIO116_MAGICIAN_nCAM_EN_MD             (116 | GPIO_OUT)
+#define GPIO119_MAGICIAN_UNKNOWN_MD             (119 | GPIO_OUT)
+#define GPIO120_MAGICIAN_UNKNOWN_MD             (120 | GPIO_OUT)
+
+#endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
index 7513c7a3402d..bb410313556f 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa300.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa300.h
@@ -4,7 +4,7 @@
  * PXA300/PXA310 specific MFP configuration definitions
  *
  * Copyright (C) 2007 Marvell International Ltd.
- * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
  *             initial version
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -16,6 +16,7 @@
 #define __ASM_ARCH_MFP_PXA300_H
 
 #include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa3xx.h>
 
 /* GPIO */
 #define GPIO46_GPIO             MFP_CFG(GPIO46, AF1)
@@ -179,7 +180,7 @@
 #define GPIO62_LCD_CS_N         MFP_CFG_DRV(GPIO62, AF2, DS01X)
 #define GPIO72_LCD_FCLK         MFP_CFG_DRV(GPIO72, AF1, DS01X)
 #define GPIO73_LCD_LCLK         MFP_CFG_DRV(GPIO73, AF1, DS01X)
-#define GPIO74_LCD_PCLK         MFP_CFG_DRV(GPIO74, AF1, DS01X)
+#define GPIO74_LCD_PCLK         MFP_CFG_DRV(GPIO74, AF1, DS02X)
 #define GPIO75_LCD_BIAS         MFP_CFG_DRV(GPIO75, AF1, DS01X)
 #define GPIO76_LCD_VSYNC        MFP_CFG_DRV(GPIO76, AF2, DS01X)
 
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
index ae8ba34194cf..576aa46d90fc 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa320.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa320.h
@@ -4,7 +4,7 @@
  * PXA320 specific MFP configuration definitions
  *
  * Copyright (C) 2007 Marvell International Ltd.
- * 2007-08-21: eric miao <eric.y.miao@gmail.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
  *             initial version
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -16,9 +16,10 @@
 #define __ASM_ARCH_MFP_PXA320_H
 
 #include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa3xx.h>
 
 /* GPIO */
-#define GPIO46_GPIO             MFP_CFG(GPIO6, AF0)
+#define GPIO46_GPIO             MFP_CFG(GPIO46, AF0)
 #define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
 #define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
 #define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
new file mode 100644
index 000000000000..1f6b35c015d0
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
@@ -0,0 +1,252 @@
+#ifndef __ASM_ARCH_MFP_PXA3XX_H
+#define __ASM_ARCH_MFP_PXA3XX_H
+
+#define MFPR_BASE       (0x40e10000)
+#define MFPR_SIZE       (PAGE_SIZE)
+
+/* MFPR register bit definitions */
+#define MFPR_PULL_SEL           (0x1 << 15)
+#define MFPR_PULLUP_EN          (0x1 << 14)
+#define MFPR_PULLDOWN_EN        (0x1 << 13)
+#define MFPR_SLEEP_SEL          (0x1 << 9)
+#define MFPR_SLEEP_OE_N         (0x1 << 7)
+#define MFPR_EDGE_CLEAR         (0x1 << 6)
+#define MFPR_EDGE_FALL_EN       (0x1 << 5)
+#define MFPR_EDGE_RISE_EN       (0x1 << 4)
+
+#define MFPR_SLEEP_DATA(x)      ((x) << 8)
+#define MFPR_DRIVE(x)           (((x) & 0x7) << 10)
+#define MFPR_AF_SEL(x)          (((x) & 0x7) << 0)
+
+#define MFPR_EDGE_NONE          (0)
+#define MFPR_EDGE_RISE          (MFPR_EDGE_RISE_EN)
+#define MFPR_EDGE_FALL          (MFPR_EDGE_FALL_EN)
+#define MFPR_EDGE_BOTH          (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
+
+/*
+ * Table that determines the low power modes outputs, with actual settings
+ * used in parentheses for don't-care values. Except for the float output,
+ * the configured driven and pulled levels match, so if there is a need for
+ * non-LPM pulled output, the same configuration could probably be used.
+ *
+ * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
+ *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
+ *
+ * Input            0          X(0)        X(0)        X(0)       0
+ * Drive 0          0          0           0           X(1)       0
+ * Drive 1          0          1           X(1)        0          0
+ * Pull hi (1)      1          X(1)        1           0          0
+ * Pull lo (0)      1          X(0)        0           1          0
+ * Z (float)        1          X(0)        0           0          0
+ */
+#define MFPR_LPM_INPUT          (0)
+#define MFPR_LPM_DRIVE_LOW      (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
+#define MFPR_LPM_DRIVE_HIGH     (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
+#define MFPR_LPM_PULL_LOW       (MFPR_LPM_DRIVE_LOW  | MFPR_SLEEP_OE_N)
+#define MFPR_LPM_PULL_HIGH      (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
+#define MFPR_LPM_FLOAT          (MFPR_SLEEP_OE_N)
+#define MFPR_LPM_MASK           (0xe080)
+
+/*
+ * The pullup and pulldown state of the MFP pin at run mode is by default
+ * determined by the selected alternate function. In case that some buggy
+ * devices need to override this default behavior,  the definitions below
+ * indicates the setting of corresponding MFPR bits
+ *
+ * Definition       pull_sel  pullup_en  pulldown_en
+ * MFPR_PULL_NONE       0         0        0
+ * MFPR_PULL_LOW        1         0        1
+ * MFPR_PULL_HIGH       1         1        0
+ * MFPR_PULL_BOTH       1         1        1
+ */
+#define MFPR_PULL_NONE          (0)
+#define MFPR_PULL_LOW           (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
+#define MFPR_PULL_BOTH          (MFPR_PULL_LOW | MFPR_PULLUP_EN)
+#define MFPR_PULL_HIGH          (MFPR_PULL_SEL | MFPR_PULLUP_EN)
+
+/* PXA3xx common MFP configurations - processor specific ones defined
+ * in mfp-pxa300.h and mfp-pxa320.h
+ */
+#define GPIO0_GPIO              MFP_CFG(GPIO0, AF0)
+#define GPIO1_GPIO              MFP_CFG(GPIO1, AF0)
+#define GPIO2_GPIO              MFP_CFG(GPIO2, AF0)
+#define GPIO3_GPIO              MFP_CFG(GPIO3, AF0)
+#define GPIO4_GPIO              MFP_CFG(GPIO4, AF0)
+#define GPIO5_GPIO              MFP_CFG(GPIO5, AF0)
+#define GPIO6_GPIO              MFP_CFG(GPIO6, AF0)
+#define GPIO7_GPIO              MFP_CFG(GPIO7, AF0)
+#define GPIO8_GPIO              MFP_CFG(GPIO8, AF0)
+#define GPIO9_GPIO              MFP_CFG(GPIO9, AF0)
+#define GPIO10_GPIO             MFP_CFG(GPIO10, AF0)
+#define GPIO11_GPIO             MFP_CFG(GPIO11, AF0)
+#define GPIO12_GPIO             MFP_CFG(GPIO12, AF0)
+#define GPIO13_GPIO             MFP_CFG(GPIO13, AF0)
+#define GPIO14_GPIO             MFP_CFG(GPIO14, AF0)
+#define GPIO15_GPIO             MFP_CFG(GPIO15, AF0)
+#define GPIO16_GPIO             MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO             MFP_CFG(GPIO17, AF0)
+#define GPIO18_GPIO             MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO             MFP_CFG(GPIO19, AF0)
+#define GPIO20_GPIO             MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO             MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO             MFP_CFG(GPIO22, AF0)
+#define GPIO23_GPIO             MFP_CFG(GPIO23, AF0)
+#define GPIO24_GPIO             MFP_CFG(GPIO24, AF0)
+#define GPIO25_GPIO             MFP_CFG(GPIO25, AF0)
+#define GPIO26_GPIO             MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO             MFP_CFG(GPIO27, AF0)
+#define GPIO28_GPIO             MFP_CFG(GPIO28, AF0)
+#define GPIO29_GPIO             MFP_CFG(GPIO29, AF0)
+#define GPIO30_GPIO             MFP_CFG(GPIO30, AF0)
+#define GPIO31_GPIO             MFP_CFG(GPIO31, AF0)
+#define GPIO32_GPIO             MFP_CFG(GPIO32, AF0)
+#define GPIO33_GPIO             MFP_CFG(GPIO33, AF0)
+#define GPIO34_GPIO             MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO             MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO             MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO             MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO             MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO             MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO             MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO             MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO             MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO             MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO             MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO             MFP_CFG(GPIO45, AF0)
+
+#define GPIO47_GPIO             MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO             MFP_CFG(GPIO48, AF0)
+
+#define GPIO53_GPIO             MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO             MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO             MFP_CFG(GPIO55, AF0)
+
+#define GPIO57_GPIO             MFP_CFG(GPIO57, AF0)
+
+#define GPIO63_GPIO             MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO             MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO             MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO             MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO             MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO             MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO             MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO             MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO             MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO             MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO             MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO             MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO             MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO             MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO             MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO             MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO             MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO             MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO             MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO             MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO             MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO             MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO             MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO             MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO             MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO             MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO             MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO             MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO             MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO             MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO             MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO             MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO             MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO             MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO             MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO             MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO             MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO            MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO            MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO            MFP_CFG(GPIO102, AF0)
+#define GPIO103_GPIO            MFP_CFG(GPIO103, AF0)
+#define GPIO104_GPIO            MFP_CFG(GPIO104, AF0)
+#define GPIO105_GPIO            MFP_CFG(GPIO105, AF0)
+#define GPIO106_GPIO            MFP_CFG(GPIO106, AF0)
+#define GPIO107_GPIO            MFP_CFG(GPIO107, AF0)
+#define GPIO108_GPIO            MFP_CFG(GPIO108, AF0)
+#define GPIO109_GPIO            MFP_CFG(GPIO109, AF0)
+#define GPIO110_GPIO            MFP_CFG(GPIO110, AF0)
+#define GPIO111_GPIO            MFP_CFG(GPIO111, AF0)
+#define GPIO112_GPIO            MFP_CFG(GPIO112, AF0)
+#define GPIO113_GPIO            MFP_CFG(GPIO113, AF0)
+#define GPIO114_GPIO            MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO            MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO            MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO            MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO            MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO            MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO            MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO            MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO            MFP_CFG(GPIO122, AF0)
+#define GPIO123_GPIO            MFP_CFG(GPIO123, AF0)
+#define GPIO124_GPIO            MFP_CFG(GPIO124, AF0)
+#define GPIO125_GPIO            MFP_CFG(GPIO125, AF0)
+#define GPIO126_GPIO            MFP_CFG(GPIO126, AF0)
+#define GPIO127_GPIO            MFP_CFG(GPIO127, AF0)
+
+#define GPIO0_2_GPIO            MFP_CFG(GPIO0_2, AF0)
+#define GPIO1_2_GPIO            MFP_CFG(GPIO1_2, AF0)
+#define GPIO2_2_GPIO            MFP_CFG(GPIO2_2, AF0)
+#define GPIO3_2_GPIO            MFP_CFG(GPIO3_2, AF0)
+#define GPIO4_2_GPIO            MFP_CFG(GPIO4_2, AF0)
+#define GPIO5_2_GPIO            MFP_CFG(GPIO5_2, AF0)
+#define GPIO6_2_GPIO            MFP_CFG(GPIO6_2, AF0)
+
+/*
+ * each MFP pin will have a MFPR register, since the offset of the
+ * register varies between processors, the processor specific code
+ * should initialize the pin offsets by pxa3xx_mfp_init_addr()
+ *
+ * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
+ * structure, which represents a range of MFP pins from "start" to
+ * "end", with the offset begining at "offset", to define a single
+ * pin, let "end" = -1
+ *
+ * use
+ *
+ * MFP_ADDR_X() to define a range of pins
+ * MFP_ADDR()   to define a single pin
+ * MFP_ADDR_END to signal the end of pin offset definitions
+ */
+struct pxa3xx_mfp_addr_map {
+        unsigned int    start;
+        unsigned int    end;
+        unsigned long   offset;
+};
+
+#define MFP_ADDR_X(start, end, offset) \
+        { MFP_PIN_##start, MFP_PIN_##end, offset }
+
+#define MFP_ADDR(pin, offset) \
+        { MFP_PIN_##pin, -1, offset }
+
+#define MFP_ADDR_END    { MFP_PIN_INVALID, 0 }
+
+/*
+ * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
+ * to the MFPR register
+ */
+unsigned long pxa3xx_mfp_read(int mfp);
+void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
+
+/*
+ * pxa3xx_mfp_config - configure the MFPR registers
+ *
+ * used by board specific initialization code
+ */
+void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
+
+/*
+ * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
+ * index and MFPR register offset
+ *
+ * used by processor specific code
+ */
+void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
+void __init pxa3xx_init_mfp(void);
+#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
index 60291742ffdd..02f6157396d3 100644
--- a/include/asm-arm/arch-pxa/mfp.h
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2007 Marvell International Ltd.
  *
- * 2007-8-21: eric miao <eric.y.miao@gmail.com>
+ * 2007-8-21: eric miao <eric.miao@marvell.com>
  *            initial version
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -16,9 +16,6 @@
 #ifndef __ASM_ARCH_MFP_H
 #define __ASM_ARCH_MFP_H
 
-#define MFPR_BASE       (0x40e10000)
-#define MFPR_SIZE       (PAGE_SIZE)
-
 #define mfp_to_gpio(m)  ((m) % 128)
 
 /* list of all the configurable MFP pins */
@@ -217,114 +214,21 @@ enum {
 };
 
 /*
- * Table that determines the low power modes outputs, with actual settings
- * used in parentheses for don't-care values. Except for the float output,
- * the configured driven and pulled levels match, so if there is a need for
- * non-LPM pulled output, the same configuration could probably be used.
- *
- * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
- *                 (bit 7)    (bit 8)    (bit 14d)   (bit 13d)
- *
- * Drive 0          0          0           0           X (1)      0
- * Drive 1          0          1           X (1)       0          0
- * Pull hi (1)      1          X(1)        1           0          0
- * Pull lo (0)      1          X(0)        0           1          0
- * Z (float)        1          X(0)        0           0          0
- */
-#define MFP_LPM_DRIVE_LOW       0x8
-#define MFP_LPM_DRIVE_HIGH      0x6
-#define MFP_LPM_PULL_HIGH       0x7
-#define MFP_LPM_PULL_LOW        0x9
-#define MFP_LPM_FLOAT           0x1
-#define MFP_LPM_PULL_NEITHER    0x0
-
-/*
- * The pullup and pulldown state of the MFP pin is by default determined by
- * selected alternate function. In case some buggy devices need to override
- * this default behavior,  pxa3xx_mfp_set_pull() can be invoked with one of
- * the following definition as the parameter.
- *
- * Definition       pull_sel  pullup_en  pulldown_en
- * MFP_PULL_HIGH        1         1        0
- * MFP_PULL_LOW         1         0        1
- * MFP_PULL_BOTH        1         1        1
- * MFP_PULL_NONE        1         0        0
- * MFP_PULL_DEFAULT     0         X        X
- *
- * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
- * bits,  which will cause potential conflicts with the low power mode
- * setting, device drivers should take care of this
- */
-#define MFP_PULL_BOTH           (0x7u)
-#define MFP_PULL_HIGH           (0x6u)
-#define MFP_PULL_LOW            (0x5u)
-#define MFP_PULL_NONE           (0x4u)
-#define MFP_PULL_DEFAULT        (0x0u)
-
-#define MFP_AF0                 (0)
-#define MFP_AF1                 (1)
-#define MFP_AF2                 (2)
-#define MFP_AF3                 (3)
-#define MFP_AF4                 (4)
-#define MFP_AF5                 (5)
-#define MFP_AF6                 (6)
-#define MFP_AF7                 (7)
-
-#define MFP_DS01X               (0)
-#define MFP_DS02X               (1)
-#define MFP_DS03X               (2)
-#define MFP_DS04X               (3)
-#define MFP_DS06X               (4)
-#define MFP_DS08X               (5)
-#define MFP_DS10X               (6)
-#define MFP_DS12X               (7)
-
-#define MFP_EDGE_BOTH           0x3
-#define MFP_EDGE_RISE           0x2
-#define MFP_EDGE_FALL           0x1
-#define MFP_EDGE_NONE           0x0
-
-#define MFPR_AF_MASK            0x0007
-#define MFPR_DRV_MASK           0x1c00
-#define MFPR_RDH_MASK           0x0200
-#define MFPR_LPM_MASK           0xe180
-#define MFPR_PULL_MASK          0xe000
-#define MFPR_EDGE_MASK          0x0070
-
-#define MFPR_ALT_OFFSET         0
-#define MFPR_ERE_OFFSET         4
-#define MFPR_EFE_OFFSET         5
-#define MFPR_EC_OFFSET          6
-#define MFPR_SON_OFFSET         7
-#define MFPR_SD_OFFSET          8
-#define MFPR_SS_OFFSET          9
-#define MFPR_DRV_OFFSET         10
-#define MFPR_PD_OFFSET          13
-#define MFPR_PU_OFFSET          14
-#define MFPR_PS_OFFSET          15
-
-#define MFPR(af, drv, rdh, lpm, edge) \
-        (((af) & 0x7) | (((drv) & 0x7) << 10) |\
-         (((rdh) & 0x1) << 9) |\
-         (((lpm) & 0x3) << 7) |\
-         (((lpm) & 0x4) << 12)|\
-         (((lpm) & 0x8) << 10)|\
-         ((!(edge)) << 6) |\
-         (((edge) & 0x1) << 5) |\
-         (((edge) & 0x2) << 3))
-
-/*
  * a possible MFP configuration is represented by a 32-bit integer
- * bit  0..15 - MFPR value (16-bit)
- * bit 16..31 - mfp pin index (used to obtain the MFPR offset)
+ *
+ * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
+ * bit 10..12 - Alternate Function Selection
+ * bit 13..15 - Drive Strength
+ * bit 16..18 - Low Power Mode State
+ * bit 19..20 - Low Power Mode Edge Detection
+ * bit 21..22 - Run Mode Pull State
  *
  * to facilitate the definition, the following macros are provided
  *
- * MFPR_DEFAULT - default MFPR value, with
+ * MFP_CFG_DEFAULT - default MFP configuration value, with
  *                alternate function = 0,
- *                drive strength = fast 1mA (MFP_DS01X)
+ *                drive strength = fast 3mA (MFP_DS03X)
  *                low power mode = default
- *                release dalay hold = false (RDH bit)
  *                edge detection = none
  *
  * MFP_CFG      - default MFPR value with alternate function
@@ -334,243 +238,74 @@ enum {
  *                low power mode
  * MFP_CFG_X    - default MFPR value with alternate function,
  *                pin drive strength and low power mode
- *
- * use
- *
- * MFP_CFG_PIN  - to get the MFP pin index
- * MFP_CFG_VAL  - to get the corresponding MFPR value
  */
 
-typedef uint32_t mfp_cfg_t;
-
-#define MFP_CFG_PIN(mfp_cfg)    (((mfp_cfg) >> 16) & 0xffff)
-#define MFP_CFG_VAL(mfp_cfg)    ((mfp_cfg) & 0xffff)
-
-#define MFPR_DEFAULT    (0x0000)
+typedef unsigned long mfp_cfg_t;
+
+#define MFP_PIN(x)              ((x) & 0x3ff)
+
+#define MFP_AF0                 (0x0 << 10)
+#define MFP_AF1                 (0x1 << 10)
+#define MFP_AF2                 (0x2 << 10)
+#define MFP_AF3                 (0x3 << 10)
+#define MFP_AF4                 (0x4 << 10)
+#define MFP_AF5                 (0x5 << 10)
+#define MFP_AF6                 (0x6 << 10)
+#define MFP_AF7                 (0x7 << 10)
+#define MFP_AF_MASK             (0x7 << 10)
+#define MFP_AF(x)               (((x) >> 10) & 0x7)
+
+#define MFP_DS01X               (0x0 << 13)
+#define MFP_DS02X               (0x1 << 13)
+#define MFP_DS03X               (0x2 << 13)
+#define MFP_DS04X               (0x3 << 13)
+#define MFP_DS06X               (0x4 << 13)
+#define MFP_DS08X               (0x5 << 13)
+#define MFP_DS10X               (0x6 << 13)
+#define MFP_DS13X               (0x7 << 13)
+#define MFP_DS_MASK             (0x7 << 13)
+#define MFP_DS(x)               (((x) >> 13) & 0x7)
+
+#define MFP_LPM_INPUT           (0x0 << 16)
+#define MFP_LPM_DRIVE_LOW       (0x1 << 16)
+#define MFP_LPM_DRIVE_HIGH      (0x2 << 16)
+#define MFP_LPM_PULL_LOW        (0x3 << 16)
+#define MFP_LPM_PULL_HIGH       (0x4 << 16)
+#define MFP_LPM_FLOAT           (0x5 << 16)
+#define MFP_LPM_STATE_MASK      (0x7 << 16)
+#define MFP_LPM_STATE(x)        (((x) >> 16) & 0x7)
+
+#define MFP_LPM_EDGE_NONE       (0x0 << 19)
+#define MFP_LPM_EDGE_RISE       (0x1 << 19)
+#define MFP_LPM_EDGE_FALL       (0x2 << 19)
+#define MFP_LPM_EDGE_BOTH       (0x3 << 19)
+#define MFP_LPM_EDGE_MASK       (0x3 << 19)
+#define MFP_LPM_EDGE(x)         (((x) >> 19) & 0x3)
+
+#define MFP_PULL_NONE           (0x0 << 21)
+#define MFP_PULL_LOW            (0x1 << 21)
+#define MFP_PULL_HIGH           (0x2 << 21)
+#define MFP_PULL_BOTH           (0x3 << 21)
+#define MFP_PULL_MASK           (0x3 << 21)
+#define MFP_PULL(x)             (((x) >> 21) & 0x3)
+
+#define MFP_CFG_DEFAULT         (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
+                                 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
 
 #define MFP_CFG(pin, af)                \
-        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
+        ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
 
 #define MFP_CFG_DRV(pin, af, drv)       \
-        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
-         ((MFP_##drv) << 10) | (MFP_##af))
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
 
 #define MFP_CFG_LPM(pin, af, lpm)       \
-        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\
-         (((MFP_LPM_##lpm) & 0x3) << 7)  |\
-         (((MFP_LPM_##lpm) & 0x4) << 12) |\
-         (((MFP_LPM_##lpm) & 0x8) << 10))
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
 
 #define MFP_CFG_X(pin, af, drv, lpm)    \
-        ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
-         ((MFP_##drv) << 10) | (MFP_##af) |\
-         (((MFP_LPM_##lpm) & 0x3) << 7)  |\
-         (((MFP_LPM_##lpm) & 0x4) << 12) |\
-         (((MFP_LPM_##lpm) & 0x8) << 10))
-
-/* common MFP configurations - processor specific ones defined
- * in mfp-pxa3xx.h
- */
-#define GPIO0_GPIO              MFP_CFG(GPIO0, AF0)
-#define GPIO1_GPIO              MFP_CFG(GPIO1, AF0)
-#define GPIO2_GPIO              MFP_CFG(GPIO2, AF0)
-#define GPIO3_GPIO              MFP_CFG(GPIO3, AF0)
-#define GPIO4_GPIO              MFP_CFG(GPIO4, AF0)
-#define GPIO5_GPIO              MFP_CFG(GPIO5, AF0)
-#define GPIO6_GPIO              MFP_CFG(GPIO6, AF0)
-#define GPIO7_GPIO              MFP_CFG(GPIO7, AF0)
-#define GPIO8_GPIO              MFP_CFG(GPIO8, AF0)
-#define GPIO9_GPIO              MFP_CFG(GPIO9, AF0)
-#define GPIO10_GPIO             MFP_CFG(GPIO10, AF0)
-#define GPIO11_GPIO             MFP_CFG(GPIO11, AF0)
-#define GPIO12_GPIO             MFP_CFG(GPIO12, AF0)
-#define GPIO13_GPIO             MFP_CFG(GPIO13, AF0)
-#define GPIO14_GPIO             MFP_CFG(GPIO14, AF0)
-#define GPIO15_GPIO             MFP_CFG(GPIO15, AF0)
-#define GPIO16_GPIO             MFP_CFG(GPIO16, AF0)
-#define GPIO17_GPIO             MFP_CFG(GPIO17, AF0)
-#define GPIO18_GPIO             MFP_CFG(GPIO18, AF0)
-#define GPIO19_GPIO             MFP_CFG(GPIO19, AF0)
-#define GPIO20_GPIO             MFP_CFG(GPIO20, AF0)
-#define GPIO21_GPIO             MFP_CFG(GPIO21, AF0)
-#define GPIO22_GPIO             MFP_CFG(GPIO22, AF0)
-#define GPIO23_GPIO             MFP_CFG(GPIO23, AF0)
-#define GPIO24_GPIO             MFP_CFG(GPIO24, AF0)
-#define GPIO25_GPIO             MFP_CFG(GPIO25, AF0)
-#define GPIO26_GPIO             MFP_CFG(GPIO26, AF0)
-#define GPIO27_GPIO             MFP_CFG(GPIO27, AF0)
-#define GPIO28_GPIO             MFP_CFG(GPIO28, AF0)
-#define GPIO29_GPIO             MFP_CFG(GPIO29, AF0)
-#define GPIO30_GPIO             MFP_CFG(GPIO30, AF0)
-#define GPIO31_GPIO             MFP_CFG(GPIO31, AF0)
-#define GPIO32_GPIO             MFP_CFG(GPIO32, AF0)
-#define GPIO33_GPIO             MFP_CFG(GPIO33, AF0)
-#define GPIO34_GPIO             MFP_CFG(GPIO34, AF0)
-#define GPIO35_GPIO             MFP_CFG(GPIO35, AF0)
-#define GPIO36_GPIO             MFP_CFG(GPIO36, AF0)
-#define GPIO37_GPIO             MFP_CFG(GPIO37, AF0)
-#define GPIO38_GPIO             MFP_CFG(GPIO38, AF0)
-#define GPIO39_GPIO             MFP_CFG(GPIO39, AF0)
-#define GPIO40_GPIO             MFP_CFG(GPIO40, AF0)
-#define GPIO41_GPIO             MFP_CFG(GPIO41, AF0)
-#define GPIO42_GPIO             MFP_CFG(GPIO42, AF0)
-#define GPIO43_GPIO             MFP_CFG(GPIO43, AF0)
-#define GPIO44_GPIO             MFP_CFG(GPIO44, AF0)
-#define GPIO45_GPIO             MFP_CFG(GPIO45, AF0)
-
-#define GPIO47_GPIO             MFP_CFG(GPIO47, AF0)
-#define GPIO48_GPIO             MFP_CFG(GPIO48, AF0)
-
-#define GPIO53_GPIO             MFP_CFG(GPIO53, AF0)
-#define GPIO54_GPIO             MFP_CFG(GPIO54, AF0)
-#define GPIO55_GPIO             MFP_CFG(GPIO55, AF0)
-
-#define GPIO57_GPIO             MFP_CFG(GPIO57, AF0)
-
-#define GPIO63_GPIO             MFP_CFG(GPIO63, AF0)
-#define GPIO64_GPIO             MFP_CFG(GPIO64, AF0)
-#define GPIO65_GPIO             MFP_CFG(GPIO65, AF0)
-#define GPIO66_GPIO             MFP_CFG(GPIO66, AF0)
-#define GPIO67_GPIO             MFP_CFG(GPIO67, AF0)
-#define GPIO68_GPIO             MFP_CFG(GPIO68, AF0)
-#define GPIO69_GPIO             MFP_CFG(GPIO69, AF0)
-#define GPIO70_GPIO             MFP_CFG(GPIO70, AF0)
-#define GPIO71_GPIO             MFP_CFG(GPIO71, AF0)
-#define GPIO72_GPIO             MFP_CFG(GPIO72, AF0)
-#define GPIO73_GPIO             MFP_CFG(GPIO73, AF0)
-#define GPIO74_GPIO             MFP_CFG(GPIO74, AF0)
-#define GPIO75_GPIO             MFP_CFG(GPIO75, AF0)
-#define GPIO76_GPIO             MFP_CFG(GPIO76, AF0)
-#define GPIO77_GPIO             MFP_CFG(GPIO77, AF0)
-#define GPIO78_GPIO             MFP_CFG(GPIO78, AF0)
-#define GPIO79_GPIO             MFP_CFG(GPIO79, AF0)
-#define GPIO80_GPIO             MFP_CFG(GPIO80, AF0)
-#define GPIO81_GPIO             MFP_CFG(GPIO81, AF0)
-#define GPIO82_GPIO             MFP_CFG(GPIO82, AF0)
-#define GPIO83_GPIO             MFP_CFG(GPIO83, AF0)
-#define GPIO84_GPIO             MFP_CFG(GPIO84, AF0)
-#define GPIO85_GPIO             MFP_CFG(GPIO85, AF0)
-#define GPIO86_GPIO             MFP_CFG(GPIO86, AF0)
-#define GPIO87_GPIO             MFP_CFG(GPIO87, AF0)
-#define GPIO88_GPIO             MFP_CFG(GPIO88, AF0)
-#define GPIO89_GPIO             MFP_CFG(GPIO89, AF0)
-#define GPIO90_GPIO             MFP_CFG(GPIO90, AF0)
-#define GPIO91_GPIO             MFP_CFG(GPIO91, AF0)
-#define GPIO92_GPIO             MFP_CFG(GPIO92, AF0)
-#define GPIO93_GPIO             MFP_CFG(GPIO93, AF0)
-#define GPIO94_GPIO             MFP_CFG(GPIO94, AF0)
-#define GPIO95_GPIO             MFP_CFG(GPIO95, AF0)
-#define GPIO96_GPIO             MFP_CFG(GPIO96, AF0)
-#define GPIO97_GPIO             MFP_CFG(GPIO97, AF0)
-#define GPIO98_GPIO             MFP_CFG(GPIO98, AF0)
-#define GPIO99_GPIO             MFP_CFG(GPIO99, AF0)
-#define GPIO100_GPIO            MFP_CFG(GPIO100, AF0)
-#define GPIO101_GPIO            MFP_CFG(GPIO101, AF0)
-#define GPIO102_GPIO            MFP_CFG(GPIO102, AF0)
-#define GPIO103_GPIO            MFP_CFG(GPIO103, AF0)
-#define GPIO104_GPIO            MFP_CFG(GPIO104, AF0)
-#define GPIO105_GPIO            MFP_CFG(GPIO105, AF0)
-#define GPIO106_GPIO            MFP_CFG(GPIO106, AF0)
-#define GPIO107_GPIO            MFP_CFG(GPIO107, AF0)
-#define GPIO108_GPIO            MFP_CFG(GPIO108, AF0)
-#define GPIO109_GPIO            MFP_CFG(GPIO109, AF0)
-#define GPIO110_GPIO            MFP_CFG(GPIO110, AF0)
-#define GPIO111_GPIO            MFP_CFG(GPIO111, AF0)
-#define GPIO112_GPIO            MFP_CFG(GPIO112, AF0)
-#define GPIO113_GPIO            MFP_CFG(GPIO113, AF0)
-#define GPIO114_GPIO            MFP_CFG(GPIO114, AF0)
-#define GPIO115_GPIO            MFP_CFG(GPIO115, AF0)
-#define GPIO116_GPIO            MFP_CFG(GPIO116, AF0)
-#define GPIO117_GPIO            MFP_CFG(GPIO117, AF0)
-#define GPIO118_GPIO            MFP_CFG(GPIO118, AF0)
-#define GPIO119_GPIO            MFP_CFG(GPIO119, AF0)
-#define GPIO120_GPIO            MFP_CFG(GPIO120, AF0)
-#define GPIO121_GPIO            MFP_CFG(GPIO121, AF0)
-#define GPIO122_GPIO            MFP_CFG(GPIO122, AF0)
-#define GPIO123_GPIO            MFP_CFG(GPIO123, AF0)
-#define GPIO124_GPIO            MFP_CFG(GPIO124, AF0)
-#define GPIO125_GPIO            MFP_CFG(GPIO125, AF0)
-#define GPIO126_GPIO            MFP_CFG(GPIO126, AF0)
-#define GPIO127_GPIO            MFP_CFG(GPIO127, AF0)
-
-#define GPIO0_2_GPIO            MFP_CFG(GPIO0_2, AF0)
-#define GPIO1_2_GPIO            MFP_CFG(GPIO1_2, AF0)
-#define GPIO2_2_GPIO            MFP_CFG(GPIO2_2, AF0)
-#define GPIO3_2_GPIO            MFP_CFG(GPIO3_2, AF0)
-#define GPIO4_2_GPIO            MFP_CFG(GPIO4_2, AF0)
-#define GPIO5_2_GPIO            MFP_CFG(GPIO5_2, AF0)
-#define GPIO6_2_GPIO            MFP_CFG(GPIO6_2, AF0)
-
-/*
- * each MFP pin will have a MFPR register, since the offset of the
- * register varies between processors, the processor specific code
- * should initialize the pin offsets by pxa3xx_mfp_init_addr()
- *
- * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
- * structure, which represents a range of MFP pins from "start" to
- * "end", with the offset begining at "offset", to define a single
- * pin, let "end" = -1
- *
- * use
- *
- * MFP_ADDR_X() to define a range of pins
- * MFP_ADDR()   to define a single pin
- * MFP_ADDR_END to signal the end of pin offset definitions
- */
-struct pxa3xx_mfp_addr_map {
-        unsigned int    start;
-        unsigned int    end;
-        unsigned long   offset;
-};
-
-#define MFP_ADDR_X(start, end, offset) \
-        { MFP_PIN_##start, MFP_PIN_##end, offset }
-
-#define MFP_ADDR(pin, offset) \
-        { MFP_PIN_##pin, -1, offset }
-
-#define MFP_ADDR_END    { MFP_PIN_INVALID, 0 }
-
-struct pxa3xx_mfp_pin {
-        unsigned long   mfpr_off;       /* MFPRxx register offset */
-        unsigned long   mfpr_val;       /* MFPRxx register value */
-};
-
-/*
- * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
- * to the MFPR register
- */
-unsigned long pxa3xx_mfp_read(int mfp);
-void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
-
-/*
- * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
- * pxa3xx_mfp_set_rdh  - set MFP release delay hold on/off
- * pxa3xx_mfp_set_lpm  - set MFP low power mode state
- * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
- *
- * use these functions to override/change the default configuration
- * done by pxa3xx_mfp_set_config(s)
- */
-void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
-void pxa3xx_mfp_set_rdh(int mfp, int rdh);
-void pxa3xx_mfp_set_lpm(int mfp, int lpm);
-void pxa3xx_mfp_set_edge(int mfp, int edge);
-
-/*
- * pxa3xx_mfp_config - configure the MFPR registers
- *
- * used by board specific initialization code
- */
-void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
-
-/*
- * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
- * index and MFPR register offset
- *
- * used by processor specific code
- */
-void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
-void __init pxa3xx_init_mfp(void);
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
 
 #endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index ef4f570381d1..6d1304c9270f 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -17,5 +17,7 @@ struct pxamci_platform_data {
 };
 
 extern void pxa_set_mci_info(struct pxamci_platform_data *info);
+extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
+extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
 
 #endif
diff --git a/include/asm-arm/arch-pxa/pcm027.h b/include/asm-arm/arch-pxa/pcm027.h
new file mode 100644
index 000000000000..7beae1472c3e
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm027.h
@@ -0,0 +1,75 @@
+/*
+ * linux/include/asm-arm/arch-pxa/pcm027.h
+ *
+ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
+ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Definitions of CPU card resources only
+ */
+
+/* I2C RTC */
+#define PCM027_RTC_IRQ_GPIO     0
+#define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
+#define PCM027_RTC_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
+#define ADR_PCM027_RTC          0x51    /* I2C address */
+
+/* I2C EEPROM */
+#define ADR_PCM027_EEPROM       0x54    /* I2C address */
+
+/* Ethernet chip (SMSC91C111) */
+#define PCM027_ETH_IRQ_GPIO     52
+#define PCM027_ETH_IRQ          IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
+#define PCM027_ETH_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
+#define PCM027_ETH_PHYS         PXA_CS5_PHYS
+#define PCM027_ETH_SIZE         (1*1024*1024)
+
+/* CAN controller SJA1000 (unsupported yet) */
+#define PCM027_CAN_IRQ_GPIO     114
+#define PCM027_CAN_IRQ          IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
+#define PCM027_CAN_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
+#define PCM027_CAN_PHYS         0x22000000
+#define PCM027_CAN_SIZE         0x100
+
+/* SPI GPIO expander (unsupported yet) */
+#define PCM027_EGPIO_IRQ_GPIO   27
+#define PCM027_EGPIO_IRQ        IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
+#define PCM027_EGPIO_IRQ_EDGE   IRQ_TYPE_EDGE_FALLING
+#define PCM027_EGPIO_CS         24
+/*
+ * TODO: Switch this pin from dedicated usage to GPIO if
+ * more than the MAX7301 device is connected to this SPI bus
+ */
+#define PCM027_EGPIO_CS_MODE    GPIO24_SFRM_MD
+
+/* Flash memory */
+#define PCM027_FLASH_PHYS       0x00000000
+#define PCM027_FLASH_SIZE       0x02000000
+
+/* onboard LEDs connected to GPIO */
+#define PCM027_LED_CPU          90
+#define PCM027_LED_HEARD_BEAT   91
+
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own basebaord init function and call it from
+ * inside pcm027_init(). This example here is for the developmen board.
+ * Refer pcm990-baseboard.c
+ */
+extern void pcm990_baseboard_init(void);
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
new file mode 100644
index 000000000000..b699d0d7bdb2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm990_baseboard.h
@@ -0,0 +1,275 @@
+/*
+ * include/asm-arm/arch-pxa/pcm990_baseboard.h
+ *
+ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
+ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <asm/arch/pcm027.h>
+
+/*
+ * definitions relevant only when the PCM-990
+ * development base board is in use
+ */
+
+/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
+#define PCM990_CTRL_INT_IRQ_GPIO        9
+#define PCM990_CTRL_INT_IRQ             IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
+#define PCM990_CTRL_INT_IRQ_EDGE        IRQT_RISING
+#define PCM990_CTRL_PHYS                PXA_CS1_PHYS    /* 16-Bit */
+#define PCM990_CTRL_BASE                0xea000000
+#define PCM990_CTRL_SIZE                (1*1024*1024)
+
+#define PCM990_CTRL_PWR_IRQ_GPIO        14
+#define PCM990_CTRL_PWR_IRQ             IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
+#define PCM990_CTRL_PWR_IRQ_EDGE        IRQT_RISING
+
+/* visible CPLD (U7) registers */
+#define PCM990_CTRL_REG0        0x0000  /* RESET REGISTER */
+#define PCM990_CTRL_SYSRES      0x0001  /* System RESET REGISTER */
+#define PCM990_CTRL_RESOUT      0x0002  /* RESETOUT Enable REGISTER */
+#define PCM990_CTRL_RESGPIO     0x0004  /* RESETGPIO Enable REGISTER */
+
+#define PCM990_CTRL_REG1        0x0002  /* Power REGISTER */
+#define PCM990_CTRL_5VOFF       0x0001  /* Disable  5V Regulators */
+#define PCM990_CTRL_CANPWR      0x0004  /* Enable CANPWR ADUM */
+#define PCM990_CTRL_PM_5V       0x0008  /* Read 5V OK */
+
+#define PCM990_CTRL_REG2        0x0004  /* LED REGISTER */
+#define PCM990_CTRL_LEDPWR      0x0001  /* POWER LED enable */
+#define PCM990_CTRL_LEDBAS      0x0002  /* BASIS LED enable */
+#define PCM990_CTRL_LEDUSR      0x0004  /* USER LED enable */
+
+#define PCM990_CTRL_REG3        0x0006  /* LCD CTRL REGISTER 3 */
+#define PCM990_CTRL_LCDPWR      0x0001  /* RW LCD Power on */
+#define PCM990_CTRL_LCDON       0x0002  /* RW LCD Latch on */
+#define PCM990_CTRL_LCDPOS1     0x0004  /* RW POS 1 */
+#define PCM990_CTRL_LCDPOS2     0x0008  /* RW POS 2 */
+
+#define PCM990_CTRL_REG4        0x0008  /* MMC1 CTRL REGISTER 4 */
+#define PCM990_CTRL_MMC1PWR     0x0001 /* RW MMC1 Power on */
+
+#define PCM990_CTRL_REG5        0x000A  /* MMC2 CTRL REGISTER 5 */
+#define PCM990_CTRL_MMC2PWR     0x0001  /* RW MMC2 Power on */
+#define PCM990_CTRL_MMC2LED     0x0002  /* RW MMC2 LED */
+#define PCM990_CTRL_MMC2DE      0x0004  /* R MMC2 Card detect */
+#define PCM990_CTRL_MMC2WP      0x0008  /* R MMC2 Card write protect */
+
+#define PCM990_CTRL_REG6        0x000C  /* Interrupt Clear REGISTER */
+#define PCM990_CTRL_INTC0       0x0001  /* Clear Reg BT Detect */
+#define PCM990_CTRL_INTC1       0x0002  /* Clear Reg FR RI */
+#define PCM990_CTRL_INTC2       0x0004  /* Clear Reg MMC1 Detect */
+#define PCM990_CTRL_INTC3       0x0008  /* Clear Reg PM_5V off */
+
+#define PCM990_CTRL_REG7        0x000E  /* Interrupt Enable REGISTER */
+#define PCM990_CTRL_ENAINT0     0x0001  /* Enable Int BT Detect */
+#define PCM990_CTRL_ENAINT1     0x0002  /* Enable Int FR RI */
+#define PCM990_CTRL_ENAINT2     0x0004  /* Enable Int MMC1 Detect */
+#define PCM990_CTRL_ENAINT3     0x0008  /* Enable Int PM_5V off */
+
+#define PCM990_CTRL_REG8        0x0014  /* Uart REGISTER */
+#define PCM990_CTRL_FFSD        0x0001  /* BT Uart Enable */
+#define PCM990_CTRL_BTSD        0x0002  /* FF Uart Enable */
+#define PCM990_CTRL_FFRI        0x0004  /* FF Uart RI detect */
+#define PCM990_CTRL_BTRX        0x0008  /* BT Uart Rx detect */
+
+#define PCM990_CTRL_REG9        0x0010  /* AC97 Flash REGISTER */
+#define PCM990_CTRL_FLWP        0x0001  /* pC Flash Write Protect */
+#define PCM990_CTRL_FLDIS       0x0002  /* pC Flash Disable */
+#define PCM990_CTRL_AC97ENA     0x0004  /* Enable AC97 Expansion */
+
+#define PCM990_CTRL_REG10       0x0012  /* GPS-REGISTER */
+#define PCM990_CTRL_GPSPWR      0x0004  /* GPS-Modul Power on */
+#define PCM990_CTRL_GPSENA      0x0008  /* GPS-Modul Enable */
+
+#define PCM990_CTRL_REG11       0x0014  /* Accu REGISTER */
+#define PCM990_CTRL_ACENA       0x0001  /* Charge Enable */
+#define PCM990_CTRL_ACSEL       0x0002  /* Charge Akku -> DC Enable */
+#define PCM990_CTRL_ACPRES      0x0004  /* DC Present */
+#define PCM990_CTRL_ACALARM     0x0008  /* Error Akku */
+
+#define PCM990_CTRL_P2V(x)      ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
+#define PCM990_CTRL_V2P(x)      ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
+
+#ifndef __ASSEMBLY__
+#  define __PCM990_CTRL_REG(x) \
+                (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
+#else
+#  define __PCM990_CTRL_REG(x)  PCM990_CTRL_P2V(x)
+#endif
+
+#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
+#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
+#define PCM990_CTRL0    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
+#define PCM990_CTRL1    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
+#define PCM990_CTRL2    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
+#define PCM990_CTRL3    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
+#define PCM990_CTRL4    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
+#define PCM990_CTRL5    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
+#define PCM990_CTRL6    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
+#define PCM990_CTRL7    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
+#define PCM990_CTRL8    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
+#define PCM990_CTRL9    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
+#define PCM990_CTRL10   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
+#define PCM990_CTRL11   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
+
+
+/*
+ * IDE
+ */
+#define PCM990_IDE_IRQ_GPIO     13
+#define PCM990_IDE_IRQ          IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
+#define PCM990_IDE_IRQ_EDGE     IRQT_RISING
+#define PCM990_IDE_PLD_PHYS     0x20000000      /* 16 bit wide */
+#define PCM990_IDE_PLD_BASE     0xee000000
+#define PCM990_IDE_PLD_SIZE     (1*1024*1024)
+
+/* visible CPLD (U6) registers */
+#define PCM990_IDE_PLD_REG0     0x1000  /* OFFSET IDE REGISTER 0 */
+#define PCM990_IDE_PM5V         0x0004  /* R System VCC_5V */
+#define PCM990_IDE_STBY         0x0008  /* R System StandBy */
+
+#define PCM990_IDE_PLD_REG1     0x1002  /* OFFSET IDE REGISTER 1 */
+#define PCM990_IDE_IDEMODE      0x0001  /* R TrueIDE Mode */
+#define PCM990_IDE_DMAENA       0x0004  /* RW DMA Enable */
+#define PCM990_IDE_DMA1_0       0x0008  /* RW 1=DREQ1 0=DREQ0 */
+
+#define PCM990_IDE_PLD_REG2     0x1004  /* OFFSET IDE REGISTER 2 */
+#define PCM990_IDE_RESENA       0x0001  /* RW IDE Reset Bit enable */
+#define PCM990_IDE_RES          0x0002  /* RW IDE Reset Bit */
+#define PCM990_IDE_RDY          0x0008  /* RDY */
+
+#define PCM990_IDE_PLD_REG3     0x1006  /* OFFSET IDE REGISTER 3 */
+#define PCM990_IDE_IDEOE        0x0001  /* RW Latch on Databus */
+#define PCM990_IDE_IDEON        0x0002  /* RW Latch on Control Address */
+#define PCM990_IDE_IDEIN        0x0004  /* RW Latch on Interrupt usw. */
+
+#define PCM990_IDE_PLD_REG4     0x1008  /* OFFSET IDE REGISTER 4 */
+#define PCM990_IDE_PWRENA       0x0001  /* RW IDE Power enable */
+#define PCM990_IDE_5V           0x0002  /* R IDE Power 5V */
+#define PCM990_IDE_PWG          0x0008  /* R IDE Power is on */
+
+#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
+#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
+
+#ifndef __ASSEMBLY__
+# define  __PCM990_IDE_PLD_REG(x) \
+        (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
+#else
+# define  __PCM990_IDE_PLD_REG(x)       PCM990_IDE_PLD_P2V(x)
+#endif
+
+#define PCM990_IDE0 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
+#define PCM990_IDE1 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
+#define PCM990_IDE2 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
+#define PCM990_IDE3 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
+#define PCM990_IDE4 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
+
+/*
+ * Compact Flash
+ */
+#define PCM990_CF_IRQ_GPIO      11
+#define PCM990_CF_IRQ           IRQ_GPIO(PCM990_CF_IRQ_GPIO)
+#define PCM990_CF_IRQ_EDGE      IRQT_RISING
+
+#define PCM990_CF_CD_GPIO       12
+#define PCM990_CF_CD            IRQ_GPIO(PCM990_CF_CD_GPIO)
+#define PCM990_CF_CD_EDGE       IRQT_RISING
+
+#define PCM990_CF_PLD_PHYS      0x30000000      /* 16 bit wide */
+#define PCM990_CF_PLD_BASE      0xef000000
+#define PCM990_CF_PLD_SIZE      (1*1024*1024)
+#define PCM990_CF_PLD_P2V(x)    ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
+#define PCM990_CF_PLD_V2P(x)    ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
+
+/* visible CPLD (U6) registers */
+#define PCM990_CF_PLD_REG0      0x1000  /* OFFSET CF REGISTER 0 */
+#define PCM990_CF_REG0_LED      0x0001  /* RW LED on */
+#define PCM990_CF_REG0_BLK      0x0002  /* RW LED flash when access */
+#define PCM990_CF_REG0_PM5V     0x0004  /* R System VCC_5V enable */
+#define PCM990_CF_REG0_STBY     0x0008  /* R System StandBy */
+
+#define PCM990_CF_PLD_REG1      0x1002  /* OFFSET CF REGISTER 1 */
+#define PCM990_CF_REG1_IDEMODE  0x0001  /* RW CF card run as TrueIDE */
+#define PCM990_CF_REG1_CF0      0x0002  /* RW CF card at ADDR 0x28000000 */
+
+#define PCM990_CF_PLD_REG2      0x1004  /* OFFSET CF REGISTER 2 */
+#define PCM990_CF_REG2_RES      0x0002  /* RW CF RESET BIT */
+#define PCM990_CF_REG2_RDYENA   0x0004  /* RW Enable CF_RDY */
+#define PCM990_CF_REG2_RDY      0x0008  /* R CF_RDY auf PWAIT */
+
+#define PCM990_CF_PLD_REG3      0x1006  /* OFFSET CF REGISTER 3 */
+#define PCM990_CF_REG3_CFOE     0x0001  /* RW Latch on Databus */
+#define PCM990_CF_REG3_CFON     0x0002  /* RW Latch on Control Address */
+#define PCM990_CF_REG3_CFIN     0x0004  /* RW Latch on Interrupt usw. */
+#define PCM990_CF_REG3_CFCD     0x0008  /* RW Latch on CD1/2 VS1/2 usw */
+
+#define PCM990_CF_PLD_REG4      0x1008  /* OFFSET CF REGISTER 4 */
+#define PCM990_CF_REG4_PWRENA   0x0001  /* RW CF Power on (CD1/2 = "00") */
+#define PCM990_CF_REG4_5_3V     0x0002  /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
+#define PCM990_CF_REG4_3B       0x0004  /* RW 3.0V Backup from VCC (5_3V=0) */
+#define PCM990_CF_REG4_PWG      0x0008  /* R CF-Power is on */
+
+#define PCM990_CF_PLD_REG5      0x100A  /* OFFSET CF REGISTER 5 */
+#define PCM990_CF_REG5_BVD1     0x0001  /* R CF /BVD1 */
+#define PCM990_CF_REG5_BVD2     0x0002  /* R CF /BVD2 */
+#define PCM990_CF_REG5_VS1      0x0004  /* R CF /VS1 */
+#define PCM990_CF_REG5_VS2      0x0008  /* R CF /VS2 */
+
+#define PCM990_CF_PLD_REG6      0x100C  /* OFFSET CF REGISTER 6 */
+#define PCM990_CF_REG6_CD1      0x0001  /* R CF Card_Detect1 */
+#define PCM990_CF_REG6_CD2      0x0002  /* R CF Card_Detect2 */
+
+#ifndef __ASSEMBLY__
+#  define  __PCM990_CF_PLD_REG(x) \
+        (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
+#else
+#  define  __PCM990_CF_PLD_REG(x)       PCM990_CF_PLD_P2V(x)
+#endif
+
+#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
+#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
+#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
+#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
+#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
+#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
+#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
+
+/*
+ * Wolfson AC97 Touch
+ */
+#define PCM990_AC97_IRQ_GPIO    10
+#define PCM990_AC97_IRQ         IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
+#define PCM990_AC97_IRQ_EDGE    IRQT_RISING
+
+/*
+ * MMC phyCORE
+ */
+#define PCM990_MMC0_IRQ_GPIO    9
+#define PCM990_MMC0_IRQ         IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
+#define PCM990_MMC0_IRQ_EDGE    IRQT_FALLING
+
+/*
+ * USB phyCore
+ */
+#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
+#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index bb68b598c436..442494d71f12 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -110,7 +110,10 @@
 #define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
 #define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
 
-#define DRCMR(n)        __REG2(0x40000100, (n)<<2)
+#define DRCMR(n)        (*(((n) < 64) ? \
+                        &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
+                        &__REG2(0x40001100, ((n) & 0x3f) << 2)))
+
 #define DRCMR0          __REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
 #define DRCMR1          __REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
 #define DRCMR2          __REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
@@ -1594,176 +1597,10 @@
 #define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
 #define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
 
-
 /*
- * SSP Serial Port Registers
- * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
- * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
+ * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
  */
 
- /* Common PXA2xx bits first */
-#define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
-#define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
-#define SSCR0_FRF       (0x00000030)    /* FRame Format (mask) */
-#define SSCR0_Motorola  (0x0 << 4)      /* Motorola's Serial Peripheral Interface (SPI) */
-#define SSCR0_TI        (0x1 << 4)      /* Texas Instruments' Synchronous Serial Protocol (SSP) */
-#define SSCR0_National  (0x2 << 4)      /* National Microwire */
-#define SSCR0_ECS       (1 << 6)        /* External clock select */
-#define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
-#if defined(CONFIG_PXA25x)
-#define SSCR0_SCR       (0x0000ff00)    /* Serial Clock Rate (mask) */
-#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
-#elif defined(CONFIG_PXA27x)
-#define SSCR0_SCR       (0x000fff00)    /* Serial Clock Rate (mask) */
-#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
-#define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
-#define SSCR0_NCS       (1 << 21)       /* Network clock select */
-#define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
-#define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
-#define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
-#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
-#define SSCR0_ADC       (1 << 30)       /* Audio clock select */
-#define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
-#endif
-
-#define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
-#define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
-#define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
-#define SSCR1_SPO       (1 << 3)        /* Motorola SPI SSPSCLK polarity setting */
-#define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
-#define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
-#define SSCR1_TFT       (0x000003c0)    /* Transmit FIFO Threshold (mask) */
-#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
-#define SSCR1_RFT       (0x00003c00)    /* Receive FIFO Threshold (mask) */
-#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
-
-#define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
-#define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
-#define SSSR_BSY        (1 << 4)        /* SSP Busy */
-#define SSSR_TFS        (1 << 5)        /* Transmit FIFO Service Request */
-#define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
-#define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
-
-#define SSCR0_TIM               (1 << 23)       /* Transmit FIFO Under Run Interrupt Mask */
-#define SSCR0_RIM               (1 << 22)       /* Receive FIFO Over Run interrupt Mask */
-#define SSCR0_NCS               (1 << 21)       /* Network Clock Select */
-#define SSCR0_EDSS              (1 << 20)       /* Extended Data Size Select */
-
-/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
-#define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
-#define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
-#define SSCR1_TTELP             (1 << 31)       /* TXD Tristate Enable Last Phase */
-#define SSCR1_TTE               (1 << 30)       /* TXD Tristate Enable */
-#define SSCR1_EBCEI             (1 << 29)       /* Enable Bit Count Error interrupt */
-#define SSCR1_SCFR              (1 << 28)       /* Slave Clock free Running */
-#define SSCR1_ECRA              (1 << 27)       /* Enable Clock Request A */
-#define SSCR1_ECRB              (1 << 26)       /* Enable Clock request B */
-#define SSCR1_SCLKDIR   (1 << 25)       /* Serial Bit Rate Clock Direction */
-#define SSCR1_SFRMDIR   (1 << 24)       /* Frame Direction */
-#define SSCR1_RWOT              (1 << 23)       /* Receive Without Transmit */
-#define SSCR1_TRAIL             (1 << 22)       /* Trailing Byte */
-#define SSCR1_TSRE              (1 << 21)       /* Transmit Service Request Enable */
-#define SSCR1_RSRE              (1 << 20)       /* Receive Service Request Enable */
-#define SSCR1_TINTE             (1 << 19)       /* Receiver Time-out Interrupt enable */
-#define SSCR1_PINTE             (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
-#define SSCR1_STRF              (1 << 15)       /* Select FIFO or EFWR */
-#define SSCR1_EFWR              (1 << 14)       /* Enable FIFO Write/Read */
-
-#define SSSR_BCE                (1 << 23)       /* Bit Count Error */
-#define SSSR_CSS                (1 << 22)       /* Clock Synchronisation Status */
-#define SSSR_TUR                (1 << 21)       /* Transmit FIFO Under Run */
-#define SSSR_EOC                (1 << 20)       /* End Of Chain */
-#define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
-#define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
-
-#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
-#define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
-#define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
-#define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
-#define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
-#define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
-#define SSPSP_ETDS                      (1 << 3)        /* End of Transfer data State */
-#define SSPSP_SFRMP                     (1 << 2)        /* Serial Frame Polarity */
-#define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
-
-#define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
-#define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
-#define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
-
-#define SSCR0_P1        __REG(0x41000000)  /* SSP Port 1 Control Register 0 */
-#define SSCR1_P1        __REG(0x41000004)  /* SSP Port 1 Control Register 1 */
-#define SSSR_P1         __REG(0x41000008)  /* SSP Port 1 Status Register */
-#define SSITR_P1        __REG(0x4100000C)  /* SSP Port 1 Interrupt Test Register */
-#define SSDR_P1         __REG(0x41000010)  /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
-
-/* Support existing PXA25x drivers */
-#define SSCR0           SSCR0_P1  /* SSP Control Register 0 */
-#define SSCR1           SSCR1_P1  /* SSP Control Register 1 */
-#define SSSR            SSSR_P1   /* SSP Status Register */
-#define SSITR           SSITR_P1  /* SSP Interrupt Test Register */
-#define SSDR            SSDR_P1   /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
-
-/* PXA27x ports */
-#if defined (CONFIG_PXA27x)
-#define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
-#define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
-#define SSTSA_P1        __REG(0x41000030)  /* SSP Port 1 Tx Timeslot Active */
-#define SSRSA_P1        __REG(0x41000034)  /* SSP Port 1 Rx Timeslot Active */
-#define SSTSS_P1        __REG(0x41000038)  /* SSP Port 1 Timeslot Status */
-#define SSACD_P1        __REG(0x4100003C)  /* SSP Port 1 Audio Clock Divider */
-#define SSCR0_P2        __REG(0x41700000)  /* SSP Port 2 Control Register 0 */
-#define SSCR1_P2        __REG(0x41700004)  /* SSP Port 2 Control Register 1 */
-#define SSSR_P2         __REG(0x41700008)  /* SSP Port 2 Status Register */
-#define SSITR_P2        __REG(0x4170000C)  /* SSP Port 2 Interrupt Test Register */
-#define SSDR_P2         __REG(0x41700010)  /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
-#define SSTO_P2         __REG(0x41700028)  /* SSP Port 2 Time Out Register */
-#define SSPSP_P2        __REG(0x4170002C)  /* SSP Port 2 Programmable Serial Protocol */
-#define SSTSA_P2        __REG(0x41700030)  /* SSP Port 2 Tx Timeslot Active */
-#define SSRSA_P2        __REG(0x41700034)  /* SSP Port 2 Rx Timeslot Active */
-#define SSTSS_P2        __REG(0x41700038)  /* SSP Port 2 Timeslot Status */
-#define SSACD_P2        __REG(0x4170003C)  /* SSP Port 2 Audio Clock Divider */
-#define SSCR0_P3        __REG(0x41900000)  /* SSP Port 3 Control Register 0 */
-#define SSCR1_P3        __REG(0x41900004)  /* SSP Port 3 Control Register 1 */
-#define SSSR_P3         __REG(0x41900008)  /* SSP Port 3 Status Register */
-#define SSITR_P3        __REG(0x4190000C)  /* SSP Port 3 Interrupt Test Register */
-#define SSDR_P3         __REG(0x41900010)  /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
-#define SSTO_P3         __REG(0x41900028)  /* SSP Port 3 Time Out Register */
-#define SSPSP_P3        __REG(0x4190002C)  /* SSP Port 3 Programmable Serial Protocol */
-#define SSTSA_P3        __REG(0x41900030)  /* SSP Port 3 Tx Timeslot Active */
-#define SSRSA_P3        __REG(0x41900034)  /* SSP Port 3 Rx Timeslot Active */
-#define SSTSS_P3        __REG(0x41900038)  /* SSP Port 3 Timeslot Status */
-#define SSACD_P3        __REG(0x4190003C)  /* SSP Port 3 Audio Clock Divider */
-#else /* PXA255 (only port 2) and PXA26x ports*/
-#define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
-#define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
-#define SSCR0_P2        __REG(0x41400000)  /* SSP Port 2 Control Register 0 */
-#define SSCR1_P2        __REG(0x41400004)  /* SSP Port 2 Control Register 1 */
-#define SSSR_P2         __REG(0x41400008)  /* SSP Port 2 Status Register */
-#define SSITR_P2        __REG(0x4140000C)  /* SSP Port 2 Interrupt Test Register */
-#define SSDR_P2         __REG(0x41400010)  /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
-#define SSTO_P2         __REG(0x41400028)  /* SSP Port 2 Time Out Register */
-#define SSPSP_P2        __REG(0x4140002C)  /* SSP Port 2 Programmable Serial Protocol */
-#define SSCR0_P3        __REG(0x41500000)  /* SSP Port 3 Control Register 0 */
-#define SSCR1_P3        __REG(0x41500004)  /* SSP Port 3 Control Register 1 */
-#define SSSR_P3         __REG(0x41500008)  /* SSP Port 3 Status Register */
-#define SSITR_P3        __REG(0x4150000C)  /* SSP Port 3 Interrupt Test Register */
-#define SSDR_P3         __REG(0x41500010)  /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
-#define SSTO_P3         __REG(0x41500028)  /* SSP Port 3 Time Out Register */
-#define SSPSP_P3        __REG(0x4150002C)  /* SSP Port 3 Programmable Serial Protocol */
-#endif
-
-#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
-#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
-#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
-#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
-#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
-#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
-#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
-#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
-#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
-#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
-#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
-
 /*
  * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
  */
@@ -1781,6 +1618,7 @@
 #define CCCR_M_MASK     0x0060          /* Memory Frequency to Run Mode Frequency Multiplier */
 #define CCCR_L_MASK     0x001f          /* Crystal Frequency to Memory Frequency Multiplier */
 
+#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
 #define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
 #define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
 #define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
@@ -2010,71 +1848,8 @@
 
 #define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
 
-/*
- * Memory controller
- */
-
-#define MDCNFG          __REG(0x48000000)  /* SDRAM Configuration Register 0 */
-#define MDREFR          __REG(0x48000004)  /* SDRAM Refresh Control Register */
-#define MSC0            __REG(0x48000008)  /* Static Memory Control Register 0 */
-#define MSC1            __REG(0x4800000C)  /* Static Memory Control Register 1 */
-#define MSC2            __REG(0x48000010)  /* Static Memory Control Register 2 */
-#define MECR            __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR           __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG          __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
-#define SXMRS           __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0          __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1          __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0          __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1          __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0           __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1           __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS           __REG(0x48000040)  /* MRS value to be written to SDRAM */
-#define BOOT_DEF        __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s)        __REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
-#define MCATT(s)        __REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
-#define MCIO(s)         __REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
-#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
-
-#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
-#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
-#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
-
-
 #ifdef CONFIG_PXA27x
 
-#define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
-
-#define ARB_DMA_SLV_PARK        (1<<31)    /* Be parked with DMA slave when idle */
-#define ARB_CI_PARK             (1<<30)    /* Be parked with Camera Interface when idle */
-#define ARB_EX_MEM_PARK         (1<<29)    /* Be parked with external MEMC when idle */
-#define ARB_INT_MEM_PARK        (1<<28)    /* Be parked with internal MEMC when idle */
-#define ARB_USB_PARK            (1<<27)    /* Be parked with USB when idle */
-#define ARB_LCD_PARK            (1<<26)    /* Be parked with LCD when idle */
-#define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
-#define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
-#define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
-
 /*
  * Keypad
  */
@@ -2131,74 +1906,6 @@
 #define KPAS_SO         (0x1 << 31)
 #define KPASMKPx_SO     (0x1 << 31)
 
-/*
- * UHC: USB Host Controller (OHCI-like) register definitions
- */
-#define UHC_BASE_PHYS   (0x4C000000)
-#define UHCREV          __REG(0x4C000000) /* UHC HCI Spec Revision */
-#define UHCHCON         __REG(0x4C000004) /* UHC Host Control Register */
-#define UHCCOMS         __REG(0x4C000008) /* UHC Command Status Register */
-#define UHCINTS         __REG(0x4C00000C) /* UHC Interrupt Status Register */
-#define UHCINTE         __REG(0x4C000010) /* UHC Interrupt Enable */
-#define UHCINTD         __REG(0x4C000014) /* UHC Interrupt Disable */
-#define UHCHCCA         __REG(0x4C000018) /* UHC Host Controller Comm. Area */
-#define UHCPCED         __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
-#define UHCCHED         __REG(0x4C000020) /* UHC Control Head Endpt Descr */
-#define UHCCCED         __REG(0x4C000024) /* UHC Control Current Endpt Descr */
-#define UHCBHED         __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
-#define UHCBCED         __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
-#define UHCDHEAD        __REG(0x4C000030) /* UHC Done Head */
-#define UHCFMI          __REG(0x4C000034) /* UHC Frame Interval */
-#define UHCFMR          __REG(0x4C000038) /* UHC Frame Remaining */
-#define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
-#define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
-#define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
-
-#define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
-#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
-
-#define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
-#define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
-#define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
-#define UHCRHPS2        __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
-#define UHCRHPS3        __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
-
-#define UHCSTAT         __REG(0x4C000060) /* UHC Status Register */
-#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
-#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
-#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
-#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
-#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
-#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
-#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
-#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
-#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
-
-#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
-#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
-#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
-#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
-#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
-#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
-#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
-#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
-#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
-#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
-#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
-#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
-
-#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
-#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
-#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
-#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
-#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
-#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
-                                           Interrupt Enable*/
-#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
-#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
-
-#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */
-
 /* Camera Interface */
 #define CICR0           __REG(0x50000000)
 #define CICR1           __REG(0x50000004)
@@ -2346,6 +2053,77 @@
 
 #endif
 
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+/*
+ * UHC: USB Host Controller (OHCI-like) register definitions
+ */
+#define UHC_BASE_PHYS   (0x4C000000)
+#define UHCREV          __REG(0x4C000000) /* UHC HCI Spec Revision */
+#define UHCHCON         __REG(0x4C000004) /* UHC Host Control Register */
+#define UHCCOMS         __REG(0x4C000008) /* UHC Command Status Register */
+#define UHCINTS         __REG(0x4C00000C) /* UHC Interrupt Status Register */
+#define UHCINTE         __REG(0x4C000010) /* UHC Interrupt Enable */
+#define UHCINTD         __REG(0x4C000014) /* UHC Interrupt Disable */
+#define UHCHCCA         __REG(0x4C000018) /* UHC Host Controller Comm. Area */
+#define UHCPCED         __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
+#define UHCCHED         __REG(0x4C000020) /* UHC Control Head Endpt Descr */
+#define UHCCCED         __REG(0x4C000024) /* UHC Control Current Endpt Descr */
+#define UHCBHED         __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
+#define UHCBCED         __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
+#define UHCDHEAD        __REG(0x4C000030) /* UHC Done Head */
+#define UHCFMI          __REG(0x4C000034) /* UHC Frame Interval */
+#define UHCFMR          __REG(0x4C000038) /* UHC Frame Remaining */
+#define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
+#define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
+#define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
+
+#define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
+
+#define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
+#define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
+#define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
+#define UHCRHPS2        __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
+#define UHCRHPS3        __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
+
+#define UHCSTAT         __REG(0x4C000060) /* UHC Status Register */
+#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
+#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
+#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
+#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
+#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
+#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
+#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
+#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
+#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
+
+#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
+#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
+#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
+#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
+#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
+#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
+#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
+#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
+#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
+#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
+#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
+#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
+
+#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
+#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
+#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
+#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
+#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
+#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
+                                           Interrupt Enable*/
+#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
+#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
+
+#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */
+
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+
 /* PWRMODE register M field values */
 
 #define PWRMODE_IDLE            0x1
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
new file mode 100644
index 000000000000..9553b54fa5bc
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -0,0 +1,84 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
+ *
+ *  Taken from pxa-regs.h by Russell King
+ *
+ *  Author:     Nicolas Pitre
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PXA2XX_REGS_H
+#define __PXA2XX_REGS_H
+
+/*
+ * Memory controller
+ */
+
+#define MDCNFG          __REG(0x48000000)  /* SDRAM Configuration Register 0 */
+#define MDREFR          __REG(0x48000004)  /* SDRAM Refresh Control Register */
+#define MSC0            __REG(0x48000008)  /* Static Memory Control Register 0 */
+#define MSC1            __REG(0x4800000C)  /* Static Memory Control Register 1 */
+#define MSC2            __REG(0x48000010)  /* Static Memory Control Register 2 */
+#define MECR            __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR           __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG          __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
+#define SXMRS           __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0          __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1          __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0          __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1          __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0           __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1           __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS           __REG(0x48000040)  /* MRS value to be written to SDRAM */
+#define BOOT_DEF        __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s)        __REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
+#define MCATT(s)        __REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
+#define MCIO(s)         __REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
+#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
+
+#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
+
+
+#ifdef CONFIG_PXA27x
+
+#define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK        (1<<31)    /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK             (1<<30)    /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK         (1<<29)    /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK        (1<<28)    /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK            (1<<27)    /* Be parked with USB when idle */
+#define ARB_LCD_PARK            (1<<26)    /* Be parked with LCD when idle */
+#define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
+#define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
+#define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index acc7ec7a84a1..3459fb26ce97 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -22,32 +22,8 @@
 #define PXA2XX_CS_ASSERT (0x01)
 #define PXA2XX_CS_DEASSERT (0x02)
 
-#if defined(CONFIG_PXA25x)
-#define CLOCK_SPEED_HZ 3686400
-#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
-#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#elif defined(CONFIG_PXA27x)
-#define CLOCK_SPEED_HZ 13000000
-#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#endif
-
-#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
-#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
-#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
-
-enum pxa_ssp_type {
-        SSP_UNDEFINED = 0,
-        PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
-        PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
-        PXA27x_SSP,
-};
-
 /* device.platform_data for SSP controller devices */
 struct pxa2xx_spi_master {
-        enum pxa_ssp_type ssp_type;
         u32 clock_enable;
         u16 num_chipselect;
         u8 enable_dma;
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 3900a0ca0bc0..66d54119757c 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -14,6 +14,92 @@
 #define __ASM_ARCH_PXA3XX_REGS_H
 
 /*
+ * Slave Power Managment Unit
+ */
+#define ASCR            __REG(0x40f40000)       /* Application Subsystem Power Status/Configuration */
+#define ARSR            __REG(0x40f40004)       /* Application Subsystem Reset Status */
+#define AD3ER           __REG(0x40f40008)       /* Application Subsystem Wake-Up from D3 Enable */
+#define AD3SR           __REG(0x40f4000c)       /* Application Subsystem Wake-Up from D3 Status */
+#define AD2D0ER         __REG(0x40f40010)       /* Application Subsystem Wake-Up from D2 to D0 Enable */
+#define AD2D0SR         __REG(0x40f40014)       /* Application Subsystem Wake-Up from D2 to D0 Status */
+#define AD2D1ER         __REG(0x40f40018)       /* Application Subsystem Wake-Up from D2 to D1 Enable */
+#define AD2D1SR         __REG(0x40f4001c)       /* Application Subsystem Wake-Up from D2 to D1 Status */
+#define AD1D0ER         __REG(0x40f40020)       /* Application Subsystem Wake-Up from D1 to D0 Enable */
+#define AD1D0SR         __REG(0x40f40024)       /* Application Subsystem Wake-Up from D1 to D0 Status */
+#define AGENP           __REG(0x40f4002c)       /* Application Subsystem General Purpose */
+#define AD3R            __REG(0x40f40030)       /* Application Subsystem D3 Configuration */
+#define AD2R            __REG(0x40f40034)       /* Application Subsystem D2 Configuration */
+#define AD1R            __REG(0x40f40038)       /* Application Subsystem D1 Configuration */
+
+/*
+ * Application Subsystem Configuration bits.
+ */
+#define ASCR_RDH                (1 << 31)
+#define ASCR_D1S                (1 << 2)
+#define ASCR_D2S                (1 << 1)
+#define ASCR_D3S                (1 << 0)
+
+/*
+ * Application Reset Status bits.
+ */
+#define ARSR_GPR                (1 << 3)
+#define ARSR_LPMR               (1 << 2)
+#define ARSR_WDT                (1 << 1)
+#define ARSR_HWR                (1 << 0)
+
+/*
+ * Application Subsystem Wake-Up bits.
+ */
+#define ADXER_WRTC              (1 << 31)       /* RTC */
+#define ADXER_WOST              (1 << 30)       /* OS Timer */
+#define ADXER_WTSI              (1 << 29)       /* Touchscreen */
+#define ADXER_WUSBH             (1 << 28)       /* USB host */
+#define ADXER_WUSB2             (1 << 26)       /* USB client 2.0 */
+#define ADXER_WMSL0             (1 << 24)       /* MSL port 0*/
+#define ADXER_WDMUX3            (1 << 23)       /* USB EDMUX3 */
+#define ADXER_WDMUX2            (1 << 22)       /* USB EDMUX2 */
+#define ADXER_WKP               (1 << 21)       /* Keypad */
+#define ADXER_WUSIM1            (1 << 20)       /* USIM Port 1 */
+#define ADXER_WUSIM0            (1 << 19)       /* USIM Port 0 */
+#define ADXER_WOTG              (1 << 16)       /* USBOTG input */
+#define ADXER_MFP_WFLASH        (1 << 15)       /* MFP: Data flash busy */
+#define ADXER_MFP_GEN12         (1 << 14)       /* MFP: MMC3/GPIO/OST inputs */
+#define ADXER_MFP_WMMC2         (1 << 13)       /* MFP: MMC2 */
+#define ADXER_MFP_WMMC1         (1 << 12)       /* MFP: MMC1 */
+#define ADXER_MFP_WI2C          (1 << 11)       /* MFP: I2C */
+#define ADXER_MFP_WSSP4         (1 << 10)       /* MFP: SSP4 */
+#define ADXER_MFP_WSSP3         (1 << 9)        /* MFP: SSP3 */
+#define ADXER_MFP_WMAXTRIX      (1 << 8)        /* MFP: matrix keypad */
+#define ADXER_MFP_WUART3        (1 << 7)        /* MFP: UART3 */
+#define ADXER_MFP_WUART2        (1 << 6)        /* MFP: UART2 */
+#define ADXER_MFP_WUART1        (1 << 5)        /* MFP: UART1 */
+#define ADXER_MFP_WSSP2         (1 << 4)        /* MFP: SSP2 */
+#define ADXER_MFP_WSSP1         (1 << 3)        /* MFP: SSP1 */
+#define ADXER_MFP_WAC97         (1 << 2)        /* MFP: AC97 */
+#define ADXER_WEXTWAKE1         (1 << 1)        /* External Wake 1 */
+#define ADXER_WEXTWAKE0         (1 << 0)        /* External Wake 0 */
+
+/*
+ * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
+ */
+#define ADXR_L2                 (1 << 8)
+#define ADXR_R5                 (1 << 5)
+#define ADXR_R4                 (1 << 4)
+#define ADXR_R3                 (1 << 3)
+#define ADXR_R2                 (1 << 2)
+#define ADXR_R1                 (1 << 1)
+#define ADXR_R0                 (1 << 0)
+
+/*
+ * Values for PWRMODE CP15 register
+ */
+#define PXA3xx_PM_S3D4C4        0x07    /* aka deep sleep */
+#define PXA3xx_PM_S2D3C4        0x06    /* aka sleep */
+#define PXA3xx_PM_S0D2C2        0x03    /* aka standby */
+#define PXA3xx_PM_S0D1C2        0x02    /* aka LCD refresh */
+#define PXA3xx_PM_S0D0C1        0x01
+
+/*
  * Application Subsystem Clock
  */
 #define ACCR            __REG(0x41340000)       /* Application Subsystem Clock Configuration Register */
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
new file mode 100644
index 000000000000..991cb688db75
--- /dev/null
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -0,0 +1,112 @@
+#ifndef __ASM_ARCH_REGS_SSP_H
+#define __ASM_ARCH_REGS_SSP_H
+
+/*
+ * SSP Serial Port Registers
+ * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
+ * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
+ */
+
+#define SSCR0           (0x00)  /* SSP Control Register 0 */
+#define SSCR1           (0x04)  /* SSP Control Register 1 */
+#define SSSR            (0x08)  /* SSP Status Register */
+#define SSITR           (0x0C)  /* SSP Interrupt Test Register */
+#define SSDR            (0x10)  /* SSP Data Write/Data Read Register */
+
+#define SSTO            (0x28)  /* SSP Time Out Register */
+#define SSPSP           (0x2C)  /* SSP Programmable Serial Protocol */
+#define SSTSA           (0x30)  /* SSP Tx Timeslot Active */
+#define SSRSA           (0x34)  /* SSP Rx Timeslot Active */
+#define SSTSS           (0x38)  /* SSP Timeslot Status */
+#define SSACD           (0x3C)  /* SSP Audio Clock Divider */
+
+/* Common PXA2xx bits first */
+#define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
+#define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
+#define SSCR0_FRF       (0x00000030)    /* FRame Format (mask) */
+#define SSCR0_Motorola  (0x0 << 4)      /* Motorola's Serial Peripheral Interface (SPI) */
+#define SSCR0_TI        (0x1 << 4)      /* Texas Instruments' Synchronous Serial Protocol (SSP) */
+#define SSCR0_National  (0x2 << 4)      /* National Microwire */
+#define SSCR0_ECS       (1 << 6)        /* External clock select */
+#define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
+#if defined(CONFIG_PXA25x)
+#define SSCR0_SCR       (0x0000ff00)    /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+#elif defined(CONFIG_PXA27x)
+#define SSCR0_SCR       (0x000fff00)    /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
+#define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
+#define SSCR0_NCS       (1 << 21)       /* Network clock select */
+#define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
+#define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
+#define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
+#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
+#define SSCR0_ADC       (1 << 30)       /* Audio clock select */
+#define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
+#endif
+
+#define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
+#define SSCR1_SPO       (1 << 3)        /* Motorola SPI SSPSCLK polarity setting */
+#define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
+#define SSCR1_TFT       (0x000003c0)    /* Transmit FIFO Threshold (mask) */
+#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
+#define SSCR1_RFT       (0x00003c00)    /* Receive FIFO Threshold (mask) */
+#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
+
+#define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
+#define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
+#define SSSR_BSY        (1 << 4)        /* SSP Busy */
+#define SSSR_TFS        (1 << 5)        /* Transmit FIFO Service Request */
+#define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
+#define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
+
+#define SSCR0_TIM               (1 << 23)       /* Transmit FIFO Under Run Interrupt Mask */
+#define SSCR0_RIM               (1 << 22)       /* Receive FIFO Over Run interrupt Mask */
+#define SSCR0_NCS               (1 << 21)       /* Network Clock Select */
+#define SSCR0_EDSS              (1 << 20)       /* Extended Data Size Select */
+
+/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
+#define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
+#define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
+#define SSCR1_TTELP             (1 << 31)       /* TXD Tristate Enable Last Phase */
+#define SSCR1_TTE               (1 << 30)       /* TXD Tristate Enable */
+#define SSCR1_EBCEI             (1 << 29)       /* Enable Bit Count Error interrupt */
+#define SSCR1_SCFR              (1 << 28)       /* Slave Clock free Running */
+#define SSCR1_ECRA              (1 << 27)       /* Enable Clock Request A */
+#define SSCR1_ECRB              (1 << 26)       /* Enable Clock request B */
+#define SSCR1_SCLKDIR           (1 << 25)       /* Serial Bit Rate Clock Direction */
+#define SSCR1_SFRMDIR           (1 << 24)       /* Frame Direction */
+#define SSCR1_RWOT              (1 << 23)       /* Receive Without Transmit */
+#define SSCR1_TRAIL             (1 << 22)       /* Trailing Byte */
+#define SSCR1_TSRE              (1 << 21)       /* Transmit Service Request Enable */
+#define SSCR1_RSRE              (1 << 20)       /* Receive Service Request Enable */
+#define SSCR1_TINTE             (1 << 19)       /* Receiver Time-out Interrupt enable */
+#define SSCR1_PINTE             (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
+#define SSCR1_STRF              (1 << 15)       /* Select FIFO or EFWR */
+#define SSCR1_EFWR              (1 << 14)       /* Enable FIFO Write/Read */
+
+#define SSSR_BCE                (1 << 23)       /* Bit Count Error */
+#define SSSR_CSS                (1 << 22)       /* Clock Synchronisation Status */
+#define SSSR_TUR                (1 << 21)       /* Transmit FIFO Under Run */
+#define SSSR_EOC                (1 << 20)       /* End Of Chain */
+#define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
+#define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
+
+#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
+#define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
+#define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
+#define SSPSP_ETDS              (1 << 3)        /* End of Transfer data State */
+#define SSPSP_SFRMP             (1 << 2)        /* Serial Frame Polarity */
+#define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
+
+#define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
+#define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
+#define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
+
+#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h
index 2b0fe773213a..3b1d4a72d4d1 100644
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ b/include/asm-arm/arch-pxa/sharpsl.h
@@ -16,7 +16,7 @@ int corgi_ssp_max1111_get(unsigned long data);
  */
 
 struct corgits_machinfo {
-        unsigned long (*get_hsync_len)(void);
+        unsigned long (*get_hsync_invperiod)(void);
         void (*put_hsync)(void);
         void (*wait_hsync)(void);
 };
diff --git a/include/asm-arm/arch-pxa/spitz.h b/include/asm-arm/arch-pxa/spitz.h
index 4953dd324d4d..bd14365f7ed5 100644
--- a/include/asm-arm/arch-pxa/spitz.h
+++ b/include/asm-arm/arch-pxa/spitz.h
@@ -156,5 +156,3 @@ extern struct platform_device spitzscoop_device;
 extern struct platform_device spitzscoop2_device;
 extern struct platform_device spitzssp_device;
 extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
-
-extern void spitz_lcd_power(int on, struct fb_var_screeninfo *var);
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
index ea200551a75f..a012882c9ee6 100644
--- a/include/asm-arm/arch-pxa/ssp.h
+++ b/include/asm-arm/arch-pxa/ssp.h
@@ -13,10 +13,37 @@
  *       PXA255     SSP, NSSP
  *       PXA26x     SSP, NSSP, ASSP
  *       PXA27x     SSP1, SSP2, SSP3
+ *       PXA3xx     SSP1, SSP2, SSP3, SSP4
  */
 
-#ifndef SSP_H
-#define SSP_H
+#ifndef __ASM_ARCH_SSP_H
+#define __ASM_ARCH_SSP_H
+
+#include <linux/list.h>
+
+enum pxa_ssp_type {
+        SSP_UNDEFINED = 0,
+        PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
+        PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
+        PXA27x_SSP,
+};
+
+struct ssp_device {
+        struct platform_device *pdev;
+        struct list_head        node;
+
+        struct clk      *clk;
+        void __iomem    *mmio_base;
+        unsigned long   phys_base;
+
+        const char      *label;
+        int             port_id;
+        int             type;
+        int             use_count;
+        int             irq;
+        int             drcmr_rx;
+        int             drcmr_tx;
+};
 
 /*
  * SSP initialisation flags
@@ -31,6 +58,7 @@ struct ssp_state {
 };
 
 struct ssp_dev {
+        struct ssp_device *ssp;
         u32 port;
         u32 mode;
         u32 flags;
@@ -50,4 +78,6 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
 int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
 void ssp_exit(struct ssp_dev *dev);
 
-#endif
+struct ssp_device *ssp_request(int port, const char *label);
+void ssp_free(struct ssp_device *);
+#endif /* __ASM_ARCH_SSP_H */
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 178aa2e073ac..dadf4c20b622 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -9,19 +9,21 @@
  * published by the Free Software Foundation.
  */
 
-#define FFUART          ((volatile unsigned long *)0x40100000)
-#define BTUART          ((volatile unsigned long *)0x40200000)
-#define STUART          ((volatile unsigned long *)0x40700000)
-#define HWUART          ((volatile unsigned long *)0x41600000)
+#include <linux/serial_reg.h>
+#include <asm/arch/pxa-regs.h>
+
+#define __REG(x)        ((volatile unsigned long *)x)
 
 #define UART            FFUART
 
 
 static inline void putc(char c)
 {
-        while (!(UART[5] & 0x20))
+        if (!(UART[UART_IER] & IER_UUE))
+                return;
+        while (!(UART[UART_LSR] & LSR_TDRQ))
                 barrier();
-        UART[0] = c;
+        UART[UART_TX] = c;
 }
 
 /*
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index f58b59162b82..5f717d64ea7d 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -3,9 +3,18 @@
 
 #define ZYLONITE_ETH_PHYS       0x14000000
 
+#define EXT_GPIO(x)             (128 + (x))
+
 /* the following variables are processor specific and initialized
  * by the corresponding zylonite_pxa3xx_init()
  */
+struct platform_mmc_slot {
+        int gpio_cd;
+        int gpio_wp;
+};
+
+extern struct platform_mmc_slot zylonite_mmc_slot[];
+
 extern int gpio_backlight;
 extern int gpio_eth_irq;
 
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 9c8cd9abb82b..89076c322726 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -92,11 +92,9 @@
 #if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
 #define fifo_full  fifo_full_s3c2410
 #define fifo_level fifo_level_s3c2410
-#warning 2410only
 #elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
 #define fifo_full  fifo_full_s3c24xx
 #define fifo_level fifo_level_s3c24xx
-#warning generic
 #endif
 
 /* include the reset of the code which will do the work */
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index c6e8d8f64938..4f291d9b7d93 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -214,6 +214,7 @@ struct s3c2410_dma_chan {
         unsigned long            dev_addr;
         unsigned long            load_timeout;
         unsigned int             flags;         /* channel flags */
+        unsigned int             hw_cfg;        /* last hw config */
 
         struct s3c24xx_dma_map  *map;           /* channel hw maps */
 
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 6dadf58ff984..29592c3ebf22 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -50,6 +50,17 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
 
 extern int s3c2410_gpio_getirq(unsigned int pin);
 
+/* s3c2410_gpio_irq2pin
+ *
+ * turn the given irq number into the corresponding GPIO number
+ *
+ * returns:
+ *      < 0 = no pin
+ *      >=0 = gpio pin number
+*/
+
+extern int s3c2410_gpio_irq2pin(unsigned int irq);
+
 #ifdef CONFIG_CPU_S3C2400
 
 extern int s3c2400_gpio_getirq(unsigned int pin);
@@ -87,6 +98,18 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 
 extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
 
+/* s3c2410_gpio_getpull
+ *
+ * Read the state of the pull-up on a given pin
+ *
+ * return:
+ *      < 0 => error code
+ *        0 => enabled
+ *        1 => disabled
+*/
+
+extern int s3c2410_gpio_getpull(unsigned int pin);
+
 extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
 
 extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
@@ -99,6 +122,11 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
 
 #endif /* CONFIG_CPU_S3C2440 */
 
+#ifdef CONFIG_CPU_S3C2412
+
+extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
+
+#endif /* CONFIG_CPU_S3C2412 */
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index 996f65488d2d..d858b3eb5547 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -160,4 +160,7 @@
 #define NR_IRQS (IRQ_S3C2440_AC97+1)
 #endif
 
+/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
+#define FIQ_START               IRQ_EINT0
+
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e39656b7a086..dba9df9d8713 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -138,6 +138,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 #define S3C2412_CLKDIVN_PDIVN           (1<<2)
 #define S3C2412_CLKDIVN_HDIVN_MASK      (3<<0)
 #define S3C2421_CLKDIVN_ARMDIVN         (1<<3)
+#define S3C2412_CLKDIVN_DVSEN           (1<<4)
+#define S3C2412_CLKDIVN_HALFHCLK        (1<<5)
 #define S3C2412_CLKDIVN_USB48DIV        (1<<6)
 #define S3C2412_CLKDIVN_UARTDIV_MASK    (15<<8)
 #define S3C2412_CLKDIVN_UARTDIV_SHIFT   (8)
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index c0748511edbc..1235df70f34e 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -19,7 +19,7 @@
 #define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
 #endif
 
-#if defined(CONFIG_CPU_S3C2440)
+#if defined(CONFIG_CPU_S3C244X)
 
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
 #define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index b693158b2d3c..0ad75d716ded 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -1133,12 +1133,16 @@
 #define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
 #define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
 #define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
-#define S3C2412_GPESLPCON       S3C2410_GPIOREG(0x4C)
 #define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
 #define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
 #define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
 
 /* definitions for each pin bit */
+#define S3C2412_GPIO_SLPCON_LOW  ( 0x00 )
+#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
+#define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
+#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
+
 #define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
 #define S3C2412_SLPCON_HIGH(x)  ( 0x01 << ((x) * 2))
 #define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index e4d82341f7ba..312ff93b63c6 100644
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -98,16 +98,19 @@
 #define S3C2410_BANKCON_Tacp3           (0x1 << 2)
 #define S3C2410_BANKCON_Tacp4           (0x2 << 2)
 #define S3C2410_BANKCON_Tacp6           (0x3 << 2)
+#define S3C2410_BANKCON_Tacp_SHIFT      (2)
 
 #define S3C2410_BANKCON_Tcah0           (0x0 << 4)
 #define S3C2410_BANKCON_Tcah1           (0x1 << 4)
 #define S3C2410_BANKCON_Tcah2           (0x2 << 4)
 #define S3C2410_BANKCON_Tcah4           (0x3 << 4)
+#define S3C2410_BANKCON_Tcah_SHIFT      (4)
 
 #define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
 #define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
 #define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
 #define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
+#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
 
 #define S3C2410_BANKCON_Tacc1           (0x0 << 8)
 #define S3C2410_BANKCON_Tacc2           (0x1 << 8)
@@ -117,16 +120,19 @@
 #define S3C2410_BANKCON_Tacc8           (0x5 << 8)
 #define S3C2410_BANKCON_Tacc10          (0x6 << 8)
 #define S3C2410_BANKCON_Tacc14          (0x7 << 8)
+#define S3C2410_BANKCON_Tacc_SHIFT      (8)
 
 #define S3C2410_BANKCON_Tcos0           (0x0 << 11)
 #define S3C2410_BANKCON_Tcos1           (0x1 << 11)
 #define S3C2410_BANKCON_Tcos2           (0x2 << 11)
 #define S3C2410_BANKCON_Tcos4           (0x3 << 11)
+#define S3C2410_BANKCON_Tcos_SHIFT      (11)
 
 #define S3C2410_BANKCON_Tacs0           (0x0 << 13)
 #define S3C2410_BANKCON_Tacs1           (0x1 << 13)
 #define S3C2410_BANKCON_Tacs2           (0x2 << 13)
 #define S3C2410_BANKCON_Tacs4           (0x3 << 13)
+#define S3C2410_BANKCON_Tacs_SHIFT      (13)
 
 #define S3C2410_BANKCON_SRAM            (0x0 << 15)
 #define S3C2400_BANKCON_EDODRAM         (0x2 << 15)
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h
index f79987be55e8..13d13b7cfe98 100644
--- a/include/asm-arm/arch-s3c2410/regs-power.h
+++ b/include/asm-arm/arch-s3c2410/regs-power.h
@@ -23,7 +23,8 @@
 #define S3C2412_INFORM2         S3C24XX_PWRREG(0x78)
 #define S3C2412_INFORM3         S3C24XX_PWRREG(0x7C)
 
-#define S3C2412_PWRCFG_BATF_IGNORE              (0<<0)
+#define S3C2412_PWRCFG_BATF_IRQ                 (1<<0)
+#define S3C2412_PWRCFG_BATF_IGNORE              (2<<0)
 #define S3C2412_PWRCFG_BATF_SLEEP               (3<<0)
 #define S3C2412_PWRCFG_BATF_MASK                (3<<0)
 
diff --git a/include/asm-arm/arch-s3c2410/spi-gpio.h b/include/asm-arm/arch-s3c2410/spi-gpio.h
index c1e4db7c9710..ba1dca88d480 100644
--- a/include/asm-arm/arch-s3c2410/spi-gpio.h
+++ b/include/asm-arm/arch-s3c2410/spi-gpio.h
@@ -21,6 +21,8 @@ struct s3c2410_spigpio_info {
         unsigned long            pin_mosi;
         unsigned long            pin_miso;
 
+        int                      bus_num;
+
         unsigned long            board_size;
         struct spi_board_info   *board_info;
 
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 63891786dfa0..14de4e596f87 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -20,6 +20,9 @@
 #include <asm/plat-s3c/regs-watchdog.h>
 #include <asm/arch/regs-clock.h>
 
+#include <linux/clk.h>
+#include <linux/err.h>
+
 void (*s3c24xx_idle)(void);
 void (*s3c24xx_reset_hook)(void);
 
@@ -59,6 +62,8 @@ static void arch_idle(void)
 static void
 arch_reset(char mode)
 {
+        struct clk *wdtclk;
+
         if (mode == 's') {
                 cpu_reset(0);
         }
@@ -70,19 +75,28 @@ arch_reset(char mode)
 
         __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
 
+        wdtclk = clk_get(NULL, "watchdog");
+        if (!IS_ERR(wdtclk)) {
+                clk_enable(wdtclk);
+        } else
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+
         /* put initial values into count and data */
-        __raw_writel(0x100, S3C2410_WTCNT);
-        __raw_writel(0x100, S3C2410_WTDAT);
+        __raw_writel(0x80, S3C2410_WTCNT);
+        __raw_writel(0x80, S3C2410_WTDAT);
 
         /* set the watchdog to go and reset... */
         __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
                      S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
 
         /* wait for reset to assert... */
-        mdelay(5000);
+        mdelay(500);
 
         printk(KERN_ERR "Watchdog reset failed to assert reset\n");
 
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+
         /* we'll take a jump through zero as a poor second */
         cpu_reset(0);
 }
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 47a6b086eee2..5c60bfc1a84d 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -310,6 +310,8 @@ static inline int constant_fls(int x)
                 _find_first_zero_bit_le(p,sz)
 #define ext2_find_next_zero_bit(p,sz,off)       \
                 _find_next_zero_bit_le(p,sz,off)
+#define ext2_find_next_bit(p, sz, off) \
+                _find_next_bit_le(p, sz, off)
 
 /*
  * Minix is defined to use little-endian byte ordering.
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 6c1c968b2987..759a97b56eed 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -94,6 +94,14 @@
 # endif
 #endif
 
+#if defined(CONFIG_CPU_FEROCEON)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE feroceon
+# endif
+#endif
+
 #if defined(CONFIG_CPU_V6)
 //# ifdef _CACHE
 #  define MULTI_CACHE 1
diff --git a/include/asm-arm/flat.h b/include/asm-arm/flat.h
index 16f5375e57b8..9918aa46d9e5 100644
--- a/include/asm-arm/flat.h
+++ b/include/asm-arm/flat.h
@@ -11,8 +11,9 @@
 #define flat_argvp_envp_on_stack()              1
 #define flat_old_ram_flag(flags)                (flags)
 #define flat_reloc_valid(reloc, size)           ((reloc) <= (size))
-#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp)
+#define flat_get_addr_from_rp(rp, relval, flags, persistent) get_unaligned(rp)
 #define flat_put_addr_at_rp(rp, val, relval)    put_unaligned(val,rp)
 #define flat_get_relocate_addr(rel)             (rel)
+#define flat_set_persistent(relval, p)          0
 
 #endif /* __ARM_FLAT_H__ */
diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h
index f31cda5a55ee..392eb5332323 100644
--- a/include/asm-arm/fpstate.h
+++ b/include/asm-arm/fpstate.h
@@ -17,14 +17,18 @@
 /*
  * VFP storage area has:
  *  - FPEXC, FPSCR, FPINST and FPINST2.
- *  - 16 double precision data registers
- *  - an implementation-dependant word of state for FLDMX/FSTMX
+ *  - 16 or 32 double precision data registers
+ *  - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6)
  * 
  *  FPEXC will always be non-zero once the VFP has been used in this process.
  */
 
 struct vfp_hard_struct {
+#ifdef CONFIG_VFPv3
+        __u64 fpregs[32];
+#else
         __u64 fpregs[16];
+#endif
 #if __LINUX_ARM_ARCH__ < 6
         __u32 fpmx_state;
 #endif
@@ -35,6 +39,7 @@ struct vfp_hard_struct {
          */
         __u32 fpinst;
         __u32 fpinst2;
+
 #ifdef CONFIG_SMP
         __u32 cpu;
 #endif
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index fb90b421f31c..ede377ec9147 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -231,7 +231,7 @@ extern int init_atu;
                                         IOP3XX_PCI_IO_WINDOW_SIZE - 1)
 #define IOP3XX_PCI_UPPER_IO_VA          (IOP3XX_PCI_LOWER_IO_VA +\
                                         IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\
+#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
                                         IOP3XX_PCI_LOWER_IO_PA) +\
                                         IOP3XX_PCI_LOWER_IO_VA)
 
diff --git a/include/asm-arm/kprobes.h b/include/asm-arm/kprobes.h
new file mode 100644
index 000000000000..4e7bd32288ae
--- /dev/null
+++ b/include/asm-arm/kprobes.h
@@ -0,0 +1,79 @@
+/*
+ * include/asm-arm/kprobes.h
+ *
+ * Copyright (C) 2006, 2007 Motorola Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _ARM_KPROBES_H
+#define _ARM_KPROBES_H
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/percpu.h>
+
+#define ARCH_SUPPORTS_KRETPROBES
+#define __ARCH_WANT_KPROBES_INSN_SLOT
+#define MAX_INSN_SIZE                   2
+#define MAX_STACK_SIZE                  64      /* 32 would probably be OK */
+
+/*
+ * This undefined instruction must be unique and
+ * reserved solely for kprobes' use.
+ */
+#define KPROBE_BREAKPOINT_INSTRUCTION   0xe7f001f8
+
+#define regs_return_value(regs)         ((regs)->ARM_r0)
+#define flush_insn_slot(p)              do { } while (0)
+#define kretprobe_blacklist_size        0
+
+typedef u32 kprobe_opcode_t;
+
+struct kprobe;
+typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *);
+
+/* Architecture specific copy of original instruction. */
+struct arch_specific_insn {
+        kprobe_opcode_t         *insn;
+        kprobe_insn_handler_t   *insn_handler;
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned int status;
+};
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned int kprobe_status;
+        struct prev_kprobe prev_kprobe;
+        struct pt_regs jprobe_saved_regs;
+        char jprobes_stack[MAX_STACK_SIZE];
+};
+
+void arch_remove_kprobe(struct kprobe *);
+
+int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr);
+int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
+int kprobe_exceptions_notify(struct notifier_block *self,
+                             unsigned long val, void *data);
+
+enum kprobe_insn {
+        INSN_REJECTED,
+        INSN_GOOD,
+        INSN_GOOD_NO_SLOT
+};
+
+enum kprobe_insn arm_kprobe_decode_insn(kprobe_opcode_t,
+                                        struct arch_specific_insn *);
+void __init arm_kprobe_decode_init(void);
+
+#endif /* _ARM_KPROBES_H */
diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h
index ff0a95715a07..f191e147ea90 100644
--- a/include/asm-arm/mach/udc_pxa2xx.h
+++ b/include/asm-arm/mach/udc_pxa2xx.h
@@ -19,7 +19,9 @@ struct pxa2xx_udc_mach_info {
          * with on-chip GPIOs not Lubbock's wierd hardware, can have a sane
          * VBUS IRQ and omit the methods above.  Store the GPIO number
          * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits.
+         * Note that sometimes the signals go through inverters...
          */
+        bool    gpio_vbus_inverted;
         u16     gpio_vbus;                      /* high == vbus present */
         u16     gpio_pullup;                    /* high == pullup activated */
 };
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index d2e8171d1d4e..5e0182485d8c 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -249,7 +249,7 @@ extern struct page *empty_zero_page;
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
 #define set_pte_at(mm,addr,ptep,pteval) do { \
-        set_pte_ext(ptep, pteval, (addr) >= PAGE_OFFSET ? 0 : PTE_EXT_NG); \
+        set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
  } while (0)
 
 /*
diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
index b824d371ae0b..d742205ac172 100644
--- a/include/asm-arm/plat-s3c/regs-nand.h
+++ b/include/asm-arm/plat-s3c/regs-nand.h
@@ -35,7 +35,7 @@
 #define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
 #define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
 #define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
-#define S3C2440_NFSECC   S3C24E10_NFREG(0x34)
+#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
 #define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
 #define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
 
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
index 2c59406435e5..c78efe316fc8 100644
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ b/include/asm-arm/plat-s3c24xx/dma.h
@@ -32,6 +32,7 @@ struct s3c24xx_dma_map {
         struct s3c24xx_dma_addr  hw_addr;
 
         unsigned long            channels[S3C2410_DMA_CHANNELS];
+        unsigned long            channels_rx[S3C2410_DMA_CHANNELS];
 };
 
 struct s3c24xx_dma_selection {
@@ -41,6 +42,10 @@ struct s3c24xx_dma_selection {
 
         void    (*select)(struct s3c2410_dma_chan *chan,
                           struct s3c24xx_dma_map *map);
+
+        void    (*direction)(struct s3c2410_dma_chan *chan,
+                             struct s3c24xx_dma_map *map,
+                             enum s3c2410_dmasrc dir);
 };
 
 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
index 8af6d9579b31..45746a995343 100644
--- a/include/asm-arm/plat-s3c24xx/irq.h
+++ b/include/asm-arm/plat-s3c24xx/irq.h
@@ -15,7 +15,9 @@
 
 #define EXTINT_OFF (IRQ_EINT4 - 4)
 
+/* these are exported for arch/arm/mach-* usage */
 extern struct irq_chip s3c_irq_level_chip;
+extern struct irq_chip s3c_irq_chip;
 
 static inline void
 s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h b/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
new file mode 100644
index 000000000000..25d4058bcfed
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
@@ -0,0 +1,72 @@
+/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
+ *
+ * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 IIS register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
+#define __ASM_ARCH_REGS_S3C2412_IIS_H
+
+#define S3C2412_IISCON                  (0x00)
+#define S3C2412_IISMOD                  (0x04)
+#define S3C2412_IISFIC                  (0x08)
+#define S3C2412_IISPSR                  (0x0C)
+#define S3C2412_IISTXD                  (0x10)
+#define S3C2412_IISRXD                  (0x14)
+
+#define S3C2412_IISCON_LRINDEX          (1 << 11)
+#define S3C2412_IISCON_TXFIFO_EMPTY     (1 << 10)
+#define S3C2412_IISCON_RXFIFO_EMPTY     (1 << 9)
+#define S3C2412_IISCON_TXFIFO_FULL      (1 << 8)
+#define S3C2412_IISCON_RXFIFO_FULL      (1 << 7)
+#define S3C2412_IISCON_TXDMA_PAUSE      (1 << 6)
+#define S3C2412_IISCON_RXDMA_PAUSE      (1 << 5)
+#define S3C2412_IISCON_TXCH_PAUSE       (1 << 4)
+#define S3C2412_IISCON_RXCH_PAUSE       (1 << 3)
+#define S3C2412_IISCON_TXDMA_ACTIVE     (1 << 2)
+#define S3C2412_IISCON_RXDMA_ACTIVE     (1 << 1)
+#define S3C2412_IISCON_IIS_ACTIVE       (1 << 0)
+
+#define S3C2412_IISMOD_MASTER_INTERNAL  (0 << 10)
+#define S3C2412_IISMOD_MASTER_EXTERNAL  (1 << 10)
+#define S3C2412_IISMOD_SLAVE            (2 << 10)
+#define S3C2412_IISMOD_MASTER_MASK      (3 << 10)
+#define S3C2412_IISMOD_MODE_TXONLY      (0 << 8)
+#define S3C2412_IISMOD_MODE_RXONLY      (1 << 8)
+#define S3C2412_IISMOD_MODE_TXRX        (2 << 8)
+#define S3C2412_IISMOD_MODE_MASK        (3 << 8)
+#define S3C2412_IISMOD_LR_LLOW          (0 << 7)
+#define S3C2412_IISMOD_LR_RLOW          (1 << 7)
+#define S3C2412_IISMOD_SDF_IIS          (0 << 5)
+#define S3C2412_IISMOD_SDF_MSB          (0 << 5)
+#define S3C2412_IISMOD_SDF_LSB          (0 << 5)
+#define S3C2412_IISMOD_SDF_MASK         (3 << 5)
+#define S3C2412_IISMOD_RCLK_256FS       (0 << 3)
+#define S3C2412_IISMOD_RCLK_512FS       (1 << 3)
+#define S3C2412_IISMOD_RCLK_384FS       (2 << 3)
+#define S3C2412_IISMOD_RCLK_768FS       (3 << 3)
+#define S3C2412_IISMOD_RCLK_MASK        (3 << 3)
+#define S3C2412_IISMOD_BCLK_32FS        (0 << 1)
+#define S3C2412_IISMOD_BCLK_48FS        (1 << 1)
+#define S3C2412_IISMOD_BCLK_16FS        (2 << 1)
+#define S3C2412_IISMOD_BCLK_24FS        (3 << 1)
+#define S3C2412_IISMOD_BCLK_MASK        (3 << 1)
+#define S3C2412_IISMOD_8BIT             (1 << 0)
+
+#define S3C2412_IISPSR_PSREN            (1 << 15)
+
+#define S3C2412_IISFIC_TXFLUSH          (1 << 15)
+#define S3C2412_IISFIC_RXFLUSH          (1 << 7)
+#define S3C2412_IISFIC_TXCOUNT(x)       (((x) >>  8) & 0xf)
+#define S3C2412_IISFIC_RXCOUNT(x)       (((x) >>  0) & 0xf)
+
+
+
+#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
+
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 4a499a138256..ea565b007d04 100644
--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
@@ -17,6 +17,21 @@
 
 #define S3C2410_SPCON   (0x00)
 
+#define S3C2412_SPCON_RXFIFO_RB2        (0<<14)
+#define S3C2412_SPCON_RXFIFO_RB4        (1<<14)
+#define S3C2412_SPCON_RXFIFO_RB12       (2<<14)
+#define S3C2412_SPCON_RXFIFO_RB14       (3<<14)
+#define S3C2412_SPCON_TXFIFO_RB2        (0<<12)
+#define S3C2412_SPCON_TXFIFO_RB4        (1<<12)
+#define S3C2412_SPCON_TXFIFO_RB12       (2<<12)
+#define S3C2412_SPCON_TXFIFO_RB14       (3<<12)
+#define S3C2412_SPCON_RXFIFO_RESET      (1<<11) /* RxFIFO reset */
+#define S3C2412_SPCON_TXFIFO_RESET      (1<<10) /* TxFIFO reset */
+#define S3C2412_SPCON_RXFIFO_EN         (1<<9)  /* RxFIFO Enable */
+#define S3C2412_SPCON_TXFIFO_EN         (1<<8)  /* TxFIFO Enable */
+
+#define S3C2412_SPCON_DIRC_RX     (1<<7)
+
 #define S3C2410_SPCON_SMOD_DMA    (2<<5)        /* DMA mode */
 #define S3C2410_SPCON_SMOD_INT    (1<<5)        /* interrupt mode */
 #define S3C2410_SPCON_SMOD_POLL   (0<<5)        /* polling mode */
@@ -34,10 +49,19 @@
 
 #define S3C2410_SPSTA    (0x04)
 
+#define S3C2412_SPSTA_RXFIFO_AE         (1<<11)
+#define S3C2412_SPSTA_TXFIFO_AE         (1<<10)
+#define S3C2412_SPSTA_RXFIFO_ERROR      (1<<9)
+#define S3C2412_SPSTA_TXFIFO_ERROR      (1<<8)
+#define S3C2412_SPSTA_RXFIFO_FIFO       (1<<7)
+#define S3C2412_SPSTA_RXFIFO_EMPTY      (1<<6)
+#define S3C2412_SPSTA_TXFIFO_NFULL      (1<<5)
+#define S3C2412_SPSTA_TXFIFO_EMPTY      (1<<4)
+
 #define S3C2410_SPSTA_DCOL        (1<<2)        /* Data Collision Error */
 #define S3C2410_SPSTA_MULD        (1<<1)        /* Multi Master Error */
 #define S3C2410_SPSTA_READY       (1<<0)        /* Data Tx/Rx ready */
-
+#define S3C2412_SPSTA_READY_ORG   (1<<3)
 
 #define S3C2410_SPPIN    (0x08)
 
@@ -46,9 +70,13 @@
 #define S3C2400_SPPIN_nCS         (1<<1)        /* SPI Card Select */
 #define S3C2410_SPPIN_KEEP        (1<<0)        /* Master Out keep */
 
-
 #define S3C2410_SPPRE    (0x0C)
 #define S3C2410_SPTDAT   (0x10)
 #define S3C2410_SPRDAT   (0x14)
 
+#define S3C2412_TXFIFO   (0x18)
+#define S3C2412_RXFIFO   (0x18)
+#define S3C2412_SPFIC    (0x24)
+
+
 #endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 5599d4e5e708..a4ce457199d3 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -185,6 +185,14 @@
 #   define CPU_NAME cpu_xsc3
 #  endif
 # endif
+# ifdef CONFIG_CPU_FEROCEON
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_feroceon
+#  endif
+# endif
 # ifdef CONFIG_CPU_V6
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
diff --git a/include/asm-arm/socket.h b/include/asm-arm/socket.h
index 65a1a64bf934..6817be9573a6 100644
--- a/include/asm-arm/socket.h
+++ b/include/asm-arm/socket.h
@@ -52,4 +52,6 @@
 #define SO_TIMESTAMPNS          35
 #define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
 
+#define SO_MARK                 36
+
 #endif /* _ASM_SOCKET_H */
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 94ea8c6dc1a4..28425c473e71 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -75,8 +75,21 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/linkage.h>
+#include <linux/stringify.h>
 #include <linux/irqflags.h>
 
+/*
+ * The CPU ID never changes at run time, so we might as well tell the
+ * compiler that it's constant.  Use this function to read the CPU ID
+ * rather than directly reading processor_id or read_cpuid() directly.
+ */
+static inline unsigned int read_cpuid_id(void) __attribute_const__;
+
+static inline unsigned int read_cpuid_id(void)
+{
+        return read_cpuid(CPUID_ID);
+}
+
 #define __exception     __attribute__((section(".exception.text")))
 
 struct thread_info;
diff --git a/include/asm-arm/traps.h b/include/asm-arm/traps.h
index d4f34dc83eb0..f1541afcf85c 100644
--- a/include/asm-arm/traps.h
+++ b/include/asm-arm/traps.h
@@ -15,4 +15,13 @@ struct undef_hook {
 void register_undef_hook(struct undef_hook *hook);
 void unregister_undef_hook(struct undef_hook *hook);
 
+static inline int in_exception_text(unsigned long ptr)
+{
+        extern char __exception_text_start[];
+        extern char __exception_text_end[];
+
+        return ptr >= (unsigned long)&__exception_text_start &&
+               ptr < (unsigned long)&__exception_text_end;
+}
+
 #endif
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index bd6be9d7f772..5f9a2cb3d452 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -7,7 +7,11 @@
 
 #define FPSID                   cr0
 #define FPSCR                   cr1
+#define MVFR1                   cr6
+#define MVFR0                   cr7
 #define FPEXC                   cr8
+#define FPINST                  cr9
+#define FPINST2                 cr10
 
 /* FPSID bits */
 #define FPSID_IMPLEMENTER_BIT   (24)
@@ -28,6 +32,19 @@
 /* FPEXC bits */
 #define FPEXC_EX                (1 << 31)
 #define FPEXC_EN                (1 << 30)
+#define FPEXC_DEX               (1 << 29)
+#define FPEXC_FP2V              (1 << 28)
+#define FPEXC_VV                (1 << 27)
+#define FPEXC_TFV               (1 << 26)
+#define FPEXC_LENGTH_BIT        (8)
+#define FPEXC_LENGTH_MASK       (7 << FPEXC_LENGTH_BIT)
+#define FPEXC_IDF               (1 << 7)
+#define FPEXC_IXF               (1 << 4)
+#define FPEXC_UFF               (1 << 3)
+#define FPEXC_OFF               (1 << 2)
+#define FPEXC_DZF               (1 << 1)
+#define FPEXC_IOF               (1 << 0)
+#define FPEXC_TRAP_MASK         (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
 
 /* FPSCR bits */
 #define FPSCR_DEFAULT_NAN       (1<<25)
@@ -55,20 +72,9 @@
 #define FPSCR_IXC               (1<<4)
 #define FPSCR_IDC               (1<<7)
 
-/*
- * VFP9-S specific.
- */
-#define FPINST                  cr9
-#define FPINST2                 cr10
-
-/* FPEXC bits */
-#define FPEXC_FPV2              (1<<28)
-#define FPEXC_LENGTH_BIT        (8)
-#define FPEXC_LENGTH_MASK       (7 << FPEXC_LENGTH_BIT)
-#define FPEXC_INV               (1 << 7)
-#define FPEXC_UFC               (1 << 3)
-#define FPEXC_OFC               (1 << 2)
-#define FPEXC_IOC               (1 << 0)
+/* MVFR0 bits */
+#define MVFR0_A_SIMD_BIT        (0)
+#define MVFR0_A_SIMD_MASK       (0xf << MVFR0_A_SIMD_BIT)
 
 /* Bit patterns for decoding the packaged operation descriptors */
 #define VFPOPDESC_LENGTH_BIT    (9)
diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h
index 27fe028b4e72..cccb3892e73c 100644
--- a/include/asm-arm/vfpmacros.h
+++ b/include/asm-arm/vfpmacros.h
@@ -15,19 +15,33 @@
         .endm
 
         @ read all the working registers back into the VFP
-        .macro  VFPFLDMIA, base
+        .macro  VFPFLDMIA, base, tmp
 #if __LINUX_ARM_ARCH__ < 6
         LDC     p11, cr0, [\base],#33*4             @ FLDMIAX \base!, {d0-d15}
 #else
         LDC     p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d0-d15}
 #endif
+#ifdef CONFIG_VFPv3
+        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
+        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
+        cmp     \tmp, #2                            @ 32 x 64bit registers?
+        ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#endif
         .endm
 
         @ write all the working registers out of the VFP
-        .macro  VFPFSTMIA, base
+        .macro  VFPFSTMIA, base, tmp
 #if __LINUX_ARM_ARCH__ < 6
         STC     p11, cr0, [\base],#33*4             @ FSTMIAX \base!, {d0-d15}
 #else
         STC     p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d0-d15}
 #endif
+#ifdef CONFIG_VFPv3
+        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
+        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
+        cmp     \tmp, #2                            @ 32 x 64bit registers?
+        stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#endif
         .endm