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-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h5
-rw-r--r--include/asm-arm/hardware/sa1111.h93
2 files changed, 36 insertions, 62 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e24f6b6c79ae..a87165436b8c 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -463,9 +463,6 @@
463 * Serial Audio Controller 463 * Serial Audio Controller
464 */ 464 */
465 465
466/* FIXME: This clash with SA1111 defines */
467#ifndef _ASM_ARCH_SA1111
468
469#define SACR0 __REG(0x40400000) /* Global Control Register */ 466#define SACR0 __REG(0x40400000) /* Global Control Register */
470#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ 467#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
471#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ 468#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
@@ -503,8 +500,6 @@
503#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ 500#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
504#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ 501#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
505 502
506#endif
507
508/* 503/*
509 * AC97 Controller registers 504 * AC97 Controller registers
510 */ 505 */
diff --git a/include/asm-arm/hardware/sa1111.h b/include/asm-arm/hardware/sa1111.h
index 6aa0a5b75b69..61b1d05c7df7 100644
--- a/include/asm-arm/hardware/sa1111.h
+++ b/include/asm-arm/hardware/sa1111.h
@@ -29,6 +29,9 @@
29#define _SA1111(x) ((x) + sa1111->resource.start) 29#define _SA1111(x) ((x) + sa1111->resource.start)
30#endif 30#endif
31 31
32#define sa1111_writel(val,addr) __raw_writel(val, addr)
33#define sa1111_readl(addr) __raw_readl(addr)
34
32/* 35/*
33 * 26 bits of the SA-1110 address bus are available to the SA-1111. 36 * 26 bits of the SA-1110 address bus are available to the SA-1111.
34 * Use these when feeding target addresses to the DMA engines. 37 * Use these when feeding target addresses to the DMA engines.
@@ -45,14 +48,6 @@
45#define SA1111_SAC_DMA_MIN_XFER (0x800) 48#define SA1111_SAC_DMA_MIN_XFER (0x800)
46 49
47/* 50/*
48 * SA1111 register definitions.
49 */
50#define __CCREG(x) __REGP(SA1111_VBASE + (x))
51
52#define sa1111_writel(val,addr) __raw_writel(val, addr)
53#define sa1111_readl(addr) __raw_readl(addr)
54
55/*
56 * System Bus Interface (SBI) 51 * System Bus Interface (SBI)
57 * 52 *
58 * Registers 53 * Registers
@@ -194,55 +189,37 @@
194 * SADR Serial Audio Data Register (16 x 32-bit) 189 * SADR Serial Audio Data Register (16 x 32-bit)
195 */ 190 */
196 191
197#define _SACR0 _SA1111( 0x0600 ) 192#define SA1111_SERAUDIO 0x0600
198#define _SACR1 _SA1111( 0x0604 ) 193
199#define _SACR2 _SA1111( 0x0608 ) 194/*
200#define _SASR0 _SA1111( 0x060c ) 195 * These are offsets from the above base.
201#define _SASR1 _SA1111( 0x0610 ) 196 */
202#define _SASCR _SA1111( 0x0618 ) 197#define SA1111_SACR0 0x00
203#define _L3_CAR _SA1111( 0x061c ) 198#define SA1111_SACR1 0x04
204#define _L3_CDR _SA1111( 0x0620 ) 199#define SA1111_SACR2 0x08
205#define _ACCAR _SA1111( 0x0624 ) 200#define SA1111_SASR0 0x0c
206#define _ACCDR _SA1111( 0x0628 ) 201#define SA1111_SASR1 0x10
207#define _ACSAR _SA1111( 0x062c ) 202#define SA1111_SASCR 0x18
208#define _ACSDR _SA1111( 0x0630 ) 203#define SA1111_L3_CAR 0x1c
209#define _SADTCS _SA1111( 0x0634 ) 204#define SA1111_L3_CDR 0x20
210#define _SADTSA _SA1111( 0x0638 ) 205#define SA1111_ACCAR 0x24
211#define _SADTCA _SA1111( 0x063c ) 206#define SA1111_ACCDR 0x28
212#define _SADTSB _SA1111( 0x0640 ) 207#define SA1111_ACSAR 0x2c
213#define _SADTCB _SA1111( 0x0644 ) 208#define SA1111_ACSDR 0x30
214#define _SADRCS _SA1111( 0x0648 ) 209#define SA1111_SADTCS 0x34
215#define _SADRSA _SA1111( 0x064c ) 210#define SA1111_SADTSA 0x38
216#define _SADRCA _SA1111( 0x0650 ) 211#define SA1111_SADTCA 0x3c
217#define _SADRSB _SA1111( 0x0654 ) 212#define SA1111_SADTSB 0x40
218#define _SADRCB _SA1111( 0x0658 ) 213#define SA1111_SADTCB 0x44
219#define _SAITR _SA1111( 0x065c ) 214#define SA1111_SADRCS 0x48
220#define _SADR _SA1111( 0x0680 ) 215#define SA1111_SADRSA 0x4c
221 216#define SA1111_SADRCA 0x50
222#define SACR0 __CCREG(0x0600) 217#define SA1111_SADRSB 0x54
223#define SACR1 __CCREG(0x0604) 218#define SA1111_SADRCB 0x58
224#define SACR2 __CCREG(0x0608) 219#define SA1111_SAITR 0x5c
225#define SASR0 __CCREG(0x060c) 220#define SA1111_SADR 0x80
226#define SASR1 __CCREG(0x0610) 221
227#define SASCR __CCREG(0x0618) 222#ifndef CONFIG_ARCH_PXA
228#define L3_CAR __CCREG(0x061c)
229#define L3_CDR __CCREG(0x0620)
230#define ACCAR __CCREG(0x0624)
231#define ACCDR __CCREG(0x0628)
232#define ACSAR __CCREG(0x062c)
233#define ACSDR __CCREG(0x0630)
234#define SADTCS __CCREG(0x0634)
235#define SADTSA __CCREG(0x0638)
236#define SADTCA __CCREG(0x063c)
237#define SADTSB __CCREG(0x0640)
238#define SADTCB __CCREG(0x0644)
239#define SADRCS __CCREG(0x0648)
240#define SADRSA __CCREG(0x064c)
241#define SADRCA __CCREG(0x0650)
242#define SADRSB __CCREG(0x0654)
243#define SADRCB __CCREG(0x0658)
244#define SAITR __CCREG(0x065c)
245#define SADR __CCREG(0x0680)
246 223
247#define SACR0_ENB (1<<0) 224#define SACR0_ENB (1<<0)
248#define SACR0_BCKD (1<<2) 225#define SACR0_BCKD (1<<2)
@@ -330,6 +307,8 @@
330#define SAITR_RDBDA (1<<10) 307#define SAITR_RDBDA (1<<10)
331#define SAITR_RDBDB (1<<11) 308#define SAITR_RDBDB (1<<11)
332 309
310#endif /* !CONFIG_ARCH_PXA */
311
333/* 312/*
334 * General-Purpose I/O Interface 313 * General-Purpose I/O Interface
335 * 314 *