90 files changed, 1460 insertions, 202 deletions
diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
index 0e9b7e18af05..002227924b9f 100644
--- a/include/asm-arm/arch-aaec2000/aaec2000.h
+++ b/include/asm-arm/arch-aaec2000/aaec2000.h
@@ -17,6 +17,16 @@
 #error You must include hardware.h not this file
 #endif /* __ASM_ARCH_HARDWARE_H */
+/* Chip selects */
+#define AAEC_CS0        0x00000000
+#define AAEC_CS1        0x10000000
+#define AAEC_CS2        0x20000000
+#define AAEC_CS3        0x30000000
+/* Flash */
+#define AAEC_FLASH_BASE AAEC_CS0
+#define AAEC_FLASH_SIZE SZ_64M
 /* Interrupt controller */
 #define IRQ_BASE        __REG(0x80000500)
 #define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
@@ -148,4 +158,50 @@
 #define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
 #define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
+/* GPIO Registers */
+#define AAEC_GPIO_PHYS  0x80000e00
+#define AAEC_GPIO_PADR          __REG(AAEC_GPIO_PHYS + 0x00)
+#define AAEC_GPIO_PBDR          __REG(AAEC_GPIO_PHYS + 0x04)
+#define AAEC_GPIO_PCDR          __REG(AAEC_GPIO_PHYS + 0x08)
+#define AAEC_GPIO_PDDR          __REG(AAEC_GPIO_PHYS + 0x0c)
+#define AAEC_GPIO_PADDR         __REG(AAEC_GPIO_PHYS + 0x10)
+#define AAEC_GPIO_PBDDR         __REG(AAEC_GPIO_PHYS + 0x14)
+#define AAEC_GPIO_PCDDR         __REG(AAEC_GPIO_PHYS + 0x18)
+#define AAEC_GPIO_PDDDR         __REG(AAEC_GPIO_PHYS + 0x1c)
+#define AAEC_GPIO_PEDR          __REG(AAEC_GPIO_PHYS + 0x20)
+#define AAEC_GPIO_PEDDR         __REG(AAEC_GPIO_PHYS + 0x24)
+#define AAEC_GPIO_KSCAN         __REG(AAEC_GPIO_PHYS + 0x28)
+#define AAEC_GPIO_PINMUX        __REG(AAEC_GPIO_PHYS + 0x2c)
+#define AAEC_GPIO_PFDR          __REG(AAEC_GPIO_PHYS + 0x30)
+#define AAEC_GPIO_PFDDR         __REG(AAEC_GPIO_PHYS + 0x34)
+#define AAEC_GPIO_PGDR          __REG(AAEC_GPIO_PHYS + 0x38)
+#define AAEC_GPIO_PGDDR         __REG(AAEC_GPIO_PHYS + 0x3c)
+#define AAEC_GPIO_PHDR          __REG(AAEC_GPIO_PHYS + 0x40)
+#define AAEC_GPIO_PHDDR         __REG(AAEC_GPIO_PHYS + 0x44)
+#define AAEC_GPIO_RAZ           __REG(AAEC_GPIO_PHYS + 0x48)
+#define AAEC_GPIO_INTTYPE1      __REG(AAEC_GPIO_PHYS + 0x4c)
+#define AAEC_GPIO_INTTYPE2      __REG(AAEC_GPIO_PHYS + 0x50)
+#define AAEC_GPIO_FEOI          __REG(AAEC_GPIO_PHYS + 0x54)
+#define AAEC_GPIO_INTEN         __REG(AAEC_GPIO_PHYS + 0x58)
+#define AAEC_GPIO_INTSTATUS     __REG(AAEC_GPIO_PHYS + 0x5c)
+#define AAEC_GPIO_RAWINTSTATUS  __REG(AAEC_GPIO_PHYS + 0x60)
+#define AAEC_GPIO_DB            __REG(AAEC_GPIO_PHYS + 0x64)
+#define AAEC_GPIO_PAPINDR       __REG(AAEC_GPIO_PHYS + 0x68)
+#define AAEC_GPIO_PBPINDR       __REG(AAEC_GPIO_PHYS + 0x6c)
+#define AAEC_GPIO_PCPINDR       __REG(AAEC_GPIO_PHYS + 0x70)
+#define AAEC_GPIO_PDPINDR       __REG(AAEC_GPIO_PHYS + 0x74)
+#define AAEC_GPIO_PEPINDR       __REG(AAEC_GPIO_PHYS + 0x78)
+#define AAEC_GPIO_PFPINDR       __REG(AAEC_GPIO_PHYS + 0x7c)
+#define AAEC_GPIO_PGPINDR       __REG(AAEC_GPIO_PHYS + 0x80)
+#define AAEC_GPIO_PHPINDR       __REG(AAEC_GPIO_PHYS + 0x84)
+#define AAEC_GPIO_PINMUX_PE0CON         (1 << 0)
+#define AAEC_GPIO_PINMUX_PD0CON         (1 << 1)
+#define AAEC_GPIO_PINMUX_CODECON        (1 << 2)
+#define AAEC_GPIO_PINMUX_UART3CON       (1 << 3)
+/* LCD Controller */
+#define AAEC_CLCD_PHYS  0x80003000
 #endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/include/asm-arm/arch-aaec2000/aaed2000.h b/include/asm-arm/arch-aaec2000/aaed2000.h
new file mode 100644
index 000000000000..bc76d2badb91
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/aaed2000.h
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/aaed2000.h
+ *
+ *  AAED-2000 specific bits definition
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_AAED2000_H
+#define __ASM_ARCH_AAED2000_H
+/* External GPIOs. */
+#define EXT_GPIO_PBASE  AAEC_CS3
+#define EXT_GPIO_VBASE  0xf8100000
+#define EXT_GPIO_LENGTH 0x00001000
+#define __ext_gpio_p2v(x)       ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
+#define __ext_gpio_v2p(x)       ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
+#define __EXT_GPIO_REG(x)       (*((volatile u32 *)__ext_gpio_p2v(x)))
+#define __EXT_GPIO_PREG(x)      (__ext_gpio_v2p((u32)&(x)))
+#define AAED_EXT_GPIO   __EXT_GPIO_REG(EXT_GPIO_PBASE)
+#define AAED_EGPIO_KBD_SCAN     0x00003fff /* Keyboard scan data */
+#define AAED_EGPIO_PWR_INT      0x00008fff /* Smart battery charger interrupt */
+#define AAED_EGPIO_SWITCHED     0x000f0000 /* DIP Switches */
+#define AAED_EGPIO_USB_VBUS     0x00400000 /* USB Vbus sense */
+#define AAED_EGPIO_LCD_PWR_EN   0x02000000 /* LCD and backlight PWR enable */
+#define AAED_EGPIO_nLED0        0x20000000 /* LED 0 */
+#define AAED_EGPIO_nLED1        0x20000000 /* LED 1 */
+#define AAED_EGPIO_nLED2        0x20000000 /* LED 2 */
+#endif /* __ARM_ARCH_AAED2000_H */
diff --git a/include/asm-arm/arch-aaec2000/hardware.h b/include/asm-arm/arch-aaec2000/hardware.h
index 4c37219e030e..153506fd06ed 100644
--- a/include/asm-arm/arch-aaec2000/hardware.h
+++ b/include/asm-arm/arch-aaec2000/hardware.h
@@ -11,7 +11,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
-#include <linux/config.h>
+#include <asm/sizes.h>
+#include <asm/arch/aaec2000.h>
 /* The kernel is loaded at physical address 0xf8000000.
 * We map the IO space a bit after
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
index c58a8d10425a..8d67907fd4f0 100644
--- a/include/asm-arm/arch-aaec2000/io.h
+++ b/include/asm-arm/arch-aaec2000/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 79c90813bc3e..d8209f8911d6 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -13,7 +13,7 @@
 #include <linux/config.h>
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
diff --git a/include/asm-arm/arch-cl7500/io.h b/include/asm-arm/arch-cl7500/io.h
index f0113bc75630..89a33287f4fe 100644
--- a/include/asm-arm/arch-cl7500/io.h
+++ b/include/asm-arm/arch-cl7500/io.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-cl7500/memory.h b/include/asm-arm/arch-cl7500/memory.h
index 9776bba8e585..34f40a6cec30 100644
--- a/include/asm-arm/arch-cl7500/memory.h
+++ b/include/asm-arm/arch-cl7500/memory.h
@@ -17,7 +17,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 /*
 * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
index 14d7e8da5453..62613b0e2d96 100644
--- a/include/asm-arm/arch-clps711x/io.h
+++ b/include/asm-arm/arch-clps711x/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 #define __io(a)                 ((void __iomem *)(a))
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index bd978947db42..61d8717406ce 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -25,7 +25,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-ebsa110/memory.h b/include/asm-arm/arch-ebsa110/memory.h
index 5a9493e12275..02f144520c10 100644
--- a/include/asm-arm/arch-ebsa110/memory.h
+++ b/include/asm-arm/arch-ebsa110/memory.h
@@ -19,7 +19,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * We keep this 1:1 so that we don't interfere
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
index 70576b17f922..776f9d377057 100644
--- a/include/asm-arm/arch-ebsa285/io.h
+++ b/include/asm-arm/arch-ebsa285/io.h
@@ -14,6 +14,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffff
 /*
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index d0466f9987d3..09e335cd687d 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -46,14 +46,14 @@ extern unsigned long __bus_to_virt(unsigned long);
 #if defined(CONFIG_ARCH_FOOTBRIDGE)
 /* Task size and page offset at 3GB */
-#define TASK_SIZE               (0xbf000000UL)
+#define TASK_SIZE               UL(0xbf000000)
-#define PAGE_OFFSET             (0xc0000000UL)
+#define PAGE_OFFSET             UL(0xc0000000)
 #elif defined(CONFIG_ARCH_CO285)
 /* Task size and page offset at 1.5GB */
-#define TASK_SIZE               (0x5f000000UL)
+#define TASK_SIZE               UL(0x5f000000)
-#define PAGE_OFFSET             (0x60000000UL)
+#define PAGE_OFFSET             UL(0x60000000)
 #else
@@ -64,7 +64,7 @@ extern unsigned long __bus_to_virt(unsigned long);
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET             (0x00000000UL)
+#define PHYS_OFFSET             UL(0x00000000)
 /*
 * This decides where the kernel will search for a free chunk of vm
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
index 1f0afa257621..9fe100c9d6be 100644
--- a/include/asm-arm/arch-epxa10db/io.h
+++ b/include/asm-arm/arch-epxa10db/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffff
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h
index 3f86bf7f67f0..999541b6a9f5 100644
--- a/include/asm-arm/arch-epxa10db/memory.h
+++ b/include/asm-arm/arch-epxa10db/memory.h
@@ -23,7 +23,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-h720x/io.h b/include/asm-arm/arch-h720x/io.h
index 68814828c9a7..d3ccfd8172b7 100644
--- a/include/asm-arm/arch-h720x/io.h
+++ b/include/asm-arm/arch-h720x/io.h
@@ -14,7 +14,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
diff --git a/include/asm-arm/arch-h720x/memory.h b/include/asm-arm/arch-h720x/memory.h
index 5633447af268..4a1bfd78a0fe 100644
--- a/include/asm-arm/arch-h720x/memory.h
+++ b/include/asm-arm/arch-h720x/memory.h
@@ -11,7 +11,7 @@
 * Page offset:
 *    ( 0xc0000000UL )
 */
-#define PHYS_OFFSET     (0x40000000UL)
+#define PHYS_OFFSET     UL(0x40000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h
index 28a4cca6a4cb..b191cdd05576 100644
--- a/include/asm-arm/arch-imx/io.h
+++ b/include/asm-arm/arch-imx/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 #define __io(a)         ((void __iomem *)(a))
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h
index 116a91fa14f1..d09ae32cd2f4 100644
--- a/include/asm-arm/arch-imx/memory.h
+++ b/include/asm-arm/arch-imx/memory.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_MMU_H
 #define __ASM_ARCH_MMU_H
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-integrator/hardware.h b/include/asm-arm/arch-integrator/hardware.h
index be2716eeaa02..6f0947bc500d 100644
--- a/include/asm-arm/arch-integrator/hardware.h
+++ b/include/asm-arm/arch-integrator/hardware.h
@@ -33,15 +33,6 @@
 #define IO_SIZE                 0x0B000000                 // How much?
 #define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
-/*
- * Similar to above, but for PCI addresses (memory, IO, Config and the
- * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
 #define PCIO_BASE               PCI_IO_VADDR
 #define PCIMEM_BASE             PCI_MEMORY_VADDR
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
index fbea8be67d26..31f2deab51b0 100644
--- a/include/asm-arm/arch-integrator/io.h
+++ b/include/asm-arm/arch-integrator/io.h
@@ -22,6 +22,14 @@
 #define IO_SPACE_LIMIT 0xffff
+/*
+ * WARNING: this has to mirror definitions in platform.h
+ */
+#define PCI_MEMORY_VADDR        0xe8000000
+#define PCI_CONFIG_VADDR        0xec000000
+#define PCI_V3_VADDR            0xed000000
+#define PCI_IO_VADDR            0xee000000
 #define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            ((a) + PCI_MEMORY_VADDR)
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h
index 2087ea7d28a9..1ab56d783e7c 100644
--- a/include/asm-arm/arch-integrator/memory.h
+++ b/include/asm-arm/arch-integrator/memory.h
@@ -23,8 +23,8 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
-#define BUS_OFFSET      (0x80000000UL)
+#define BUS_OFFSET      UL(0x80000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h
index 2761dfd8694d..f39046a6ab14 100644
--- a/include/asm-arm/arch-iop3xx/io.h
+++ b/include/asm-arm/arch-iop3xx/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 #define __io(p)                 ((void __iomem *)(p))
diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h
index 200621ff3690..f8df778a356f 100644
--- a/include/asm-arm/arch-iop3xx/iop321.h
+++ b/include/asm-arm/arch-iop3xx/iop321.h
@@ -40,7 +40,7 @@
 #define IOP321_PCI_UPPER_IO_BA      (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
 #define IOP321_PCI_IO_OFFSET        (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
-//#define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1)
+/* #define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1) */
 #define IOP321_PCI_MEM_WINDOW_SIZE  0x04000000 /* 64M outbound window */
 #define IOP321_PCI_LOWER_MEM_PA     0x80000000
 #define IOP321_PCI_LOWER_MEM_BA     (*IOP321_OMWTVR0)
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
index 45351f5cd904..bc62f4b13235 100644
--- a/include/asm-arm/arch-iop3xx/memory.h
+++ b/include/asm-arm/arch-iop3xx/memory.h
@@ -12,9 +12,9 @@
 * Physical DRAM offset.
 */
 #ifndef CONFIG_ARCH_IOP331
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 #else
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 #endif
 /*
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
index 31ae88674968..95128d9f5026 100644
--- a/include/asm-arm/arch-ixp2000/enp2611.h
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -21,8 +21,20 @@
 #ifndef __ENP2611_H
 #define __ENP2611_H
-#define ENP2611_GPIO_SCL        0x07
+#define ENP2611_CALEB_PHYS_BASE         0xc5000000
-#define ENP2611_GPIO_SDA        0x06
+#define ENP2611_CALEB_VIRT_BASE         0xfe000000
+#define ENP2611_CALEB_SIZE              0x00100000
+#define ENP2611_PM3386_0_PHYS_BASE      0xc6000000
+#define ENP2611_PM3386_0_VIRT_BASE      0xfe100000
+#define ENP2611_PM3386_0_SIZE           0x00100000
+#define ENP2611_PM3386_1_PHYS_BASE      0xc6400000
+#define ENP2611_PM3386_1_VIRT_BASE      0xfe200000
+#define ENP2611_PM3386_1_SIZE           0x00100000
+#define ENP2611_GPIO_SCL                7
+#define ENP2611_GPIO_SDA                6
 #endif
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 3241cd6f0778..7fbcdf9931ee 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT          0xffffffff
 #define __mem_pci(a)            (a)
diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h
index 0deb96c12adb..62f09c7ff420 100644
--- a/include/asm-arm/arch-ixp2000/irqs.h
+++ b/include/asm-arm/arch-ixp2000/irqs.h
@@ -67,12 +67,45 @@
 #define IRQ_IXP2000_PCIA                40
 #define IRQ_IXP2000_PCIB                41
-#define NR_IXP2000_IRQS                 42
+/* Int sources from IRQ_ERROR_STATUS */
+#define IRQ_IXP2000_DRAM0_MIN_ERR       42
+#define IRQ_IXP2000_DRAM0_MAJ_ERR       43
+#define IRQ_IXP2000_DRAM1_MIN_ERR       44
+#define IRQ_IXP2000_DRAM1_MAJ_ERR       45
+#define IRQ_IXP2000_DRAM2_MIN_ERR       46
+#define IRQ_IXP2000_DRAM2_MAJ_ERR       47
+/* 48-57 reserved */
+#define IRQ_IXP2000_SRAM0_ERR           58
+#define IRQ_IXP2000_SRAM1_ERR           59
+#define IRQ_IXP2000_SRAM2_ERR           60
+#define IRQ_IXP2000_SRAM3_ERR           61
+/* 62-65 reserved */
+#define IRQ_IXP2000_MEDIA_ERR           66
+#define IRQ_IXP2000_PCI_ERR                     67
+#define IRQ_IXP2000_SP_INT                      68
+#define NR_IXP2000_IRQS                         69
 #define IXP2000_BOARD_IRQ(x)            (NR_IXP2000_IRQS + (x))
 #define IXP2000_BOARD_IRQ_MASK(irq)     (1 << (irq - NR_IXP2000_IRQS))  
+#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
+#define IXP2000_VALID_ERR_IRQ_MASK (\
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT)        )
 /*
 * This allows for all the on-chip sources plus up to 32 CPLD based
 * IRQs. Should be more than enough.
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b768009c3a51..c6d51426e98f 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -22,7 +22,7 @@
 #define IXDP2X01_CPLD_REGION_SIZE       0x00100000
 #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
-#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
 #define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
 #define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 32aece069869..fc5ac6aec4f2 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -59,14 +59,15 @@
 #define IXP2000_CAP_SIZE                0x00100000
 /*
- * Addresses for specific on-chip peripherals
+ * Addresses for specific on-chip peripherals.
 */
 #define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
 #define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
 #define IXP2000_UART_PHYS_BASE          0xc0030000
 #define IXP2000_UART_VIRT_BASE          0xfef30000
 #define IXP2000_TIMER_VIRT_BASE         0xfef20000
-#define IXP2000_GPIO_VIRT_BASE          0Xfef10000
+#define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
+#define IXP2000_GPIO_VIRT_BASE          0xfef10000
 /*
 * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
@@ -252,7 +253,7 @@
 #define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
 #define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
-#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Centrolfunction bit */
+#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
 #define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
 /* These are from the IRQ register in the PCI ISR register */
@@ -392,4 +393,47 @@
 #define WDT_RESET_ENABLE                0x01000000
+/*
+ * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
+ * units, but the registers that differ between the two don't overlap,
+ * so we can have one register list for both.
+ */
+#define IXP2000_MSF_REG(x)                      ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
+#define IXP2000_MSF_RX_CONTROL                  IXP2000_MSF_REG(0x0000)
+#define IXP2000_MSF_TX_CONTROL                  IXP2000_MSF_REG(0x0004)
+#define IXP2000_MSF_INTERRUPT_STATUS            IXP2000_MSF_REG(0x0008)
+#define IXP2000_MSF_INTERRUPT_ENABLE            IXP2000_MSF_REG(0x000c)
+#define IXP2000_MSF_CSIX_TYPE_MAP               IXP2000_MSF_REG(0x0010)
+#define IXP2000_MSF_FC_EGRESS_STATUS            IXP2000_MSF_REG(0x0014)
+#define IXP2000_MSF_FC_INGRESS_STATUS           IXP2000_MSF_REG(0x0018)
+#define IXP2000_MSF_HWM_CONTROL                 IXP2000_MSF_REG(0x0024)
+#define IXP2000_MSF_FC_STATUS_OVERRIDE          IXP2000_MSF_REG(0x0028)
+#define IXP2000_MSF_CLOCK_CONTROL               IXP2000_MSF_REG(0x002c)
+#define IXP2000_MSF_RX_PORT_MAP                 IXP2000_MSF_REG(0x0040)
+#define IXP2000_MSF_RBUF_ELEMENT_DONE           IXP2000_MSF_REG(0x0044)
+#define IXP2000_MSF_RX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0        IXP2000_MSF_REG(0x0050)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1        IXP2000_MSF_REG(0x0054)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2        IXP2000_MSF_REG(0x0058)
+#define IXP2000_MSF_TX_SEQUENCE_0               IXP2000_MSF_REG(0x0060)
+#define IXP2000_MSF_TX_SEQUENCE_1               IXP2000_MSF_REG(0x0064)
+#define IXP2000_MSF_TX_SEQUENCE_2               IXP2000_MSF_REG(0x0068)
+#define IXP2000_MSF_TX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_TX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_RX_UP_CONTROL_0             IXP2000_MSF_REG(0x0080)
+#define IXP2000_MSF_RX_UP_CONTROL_1             IXP2000_MSF_REG(0x0084)
+#define IXP2000_MSF_RX_UP_CONTROL_2             IXP2000_MSF_REG(0x0088)
+#define IXP2000_MSF_RX_UP_CONTROL_3             IXP2000_MSF_REG(0x008c)
+#define IXP2000_MSF_TX_UP_CONTROL_0             IXP2000_MSF_REG(0x0090)
+#define IXP2000_MSF_TX_UP_CONTROL_1             IXP2000_MSF_REG(0x0094)
+#define IXP2000_MSF_TX_UP_CONTROL_2             IXP2000_MSF_REG(0x0098)
+#define IXP2000_MSF_TX_UP_CONTROL_3             IXP2000_MSF_REG(0x009c)
+#define IXP2000_MSF_TRAIN_DATA                  IXP2000_MSF_REG(0x00a0)
+#define IXP2000_MSF_TRAIN_CALENDAR              IXP2000_MSF_REG(0x00a4)
+#define IXP2000_MSF_TRAIN_FLOW_CONTROL          IXP2000_MSF_REG(0x00a8)
+#define IXP2000_MSF_TX_CALENDAR_0               IXP2000_MSF_REG(0x1000)
+#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS     IXP2000_MSF_REG(0x1400)
 #endif                          /* _IXP2000_H_ */
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h
index d0f415c6dae9..21e1de51e3f6 100644
--- a/include/asm-arm/arch-ixp2000/memory.h
+++ b/include/asm-arm/arch-ixp2000/memory.h
@@ -13,7 +13,7 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index abdcf51bd283..a66317ab2071 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -15,40 +15,40 @@
 #ifndef __ASSEMBLY__
+static inline unsigned long ixp2000_reg_read(volatile void *reg)
+{
+        return *((volatile unsigned long *)reg);
+}
+static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
 /*
- * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
+ * On the IXP2400, we can't use XCB=000 due to chip bugs.  We use
- * to on-chip I/O register to not complete fully. What this means is
+ * XCB=101 instead, but that makes all I/O accesses bufferable.  This
- * that if you have a write to on-chip I/O followed by a back-to-back
+ * is not a problem in general, but we do have to be slightly more
- * read or write, the first write will happen twice. OR...if it's
+ * careful because I/O writes are no longer automatically flushed out
- * not a back-to-back transaction, the read or write will generate
+ * of the write buffer.
- * incorrect data.
- *
- * The official work around for this is to set the on-chip I/O regions
- * as XCB=101 and then force a read-back from the register.
 *
+ * In cases where we want to make sure that a write has been flushed
+ * out of the write buffer before we proceed, for example when masking
+ * a device interrupt before re-enabling IRQs in CPSR, we can use this
+ * function, ixp2000_reg_wrb, which performs a write, a readback, and
+ * issues a dummy instruction dependent on the value of the readback
+ * (mov rX, rX) to make sure that the readback has completed before we
+ * continue.
 */
-#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
+static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
-#include <asm/system.h>         /* Pickup local_irq_ functions */
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
 {
        unsigned long dummy;
-        unsigned long flags;
-        local_irq_save(flags);
        *((volatile unsigned long *)reg) = val;
-        barrier();
        dummy = *((volatile unsigned long *)reg);
-        local_irq_restore(flags);
+        __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
-}
-#else
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
 }
-#endif  /* IXDP2400 || IXDP2401 */
-#define ixp2000_reg_read(reg)   (*((volatile unsigned long *)reg))
 /*
 * Boards may multiplex different devices on the 2nd channel of 
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
index 4f489cc0dfa5..ddbbb34b5f95 100644
--- a/include/asm-arm/arch-ixp2000/system.h
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -26,29 +26,24 @@ static inline void arch_reset(char mode)
         * RedBoot bank.
         */
        if (machine_is_ixdp2401()) {
-                *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
+                ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
-                                                | IXDP2X01_CPLD_FLASH_INTERN);
+                                        ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
-                *IXDP2X01_CPLD_RESET_REG = 0xffffffff;
+                                                | IXDP2X01_CPLD_FLASH_INTERN));
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
        }
        /*
         * On IXDP2801 we need to write this magic sequence to the CPLD
         * to cause a complete reset of the CPU and all external devices
-         * and moves the flash bank register back to 0.
+         * and move the flash bank register back to 0.
         */
        if (machine_is_ixdp2801()) {
                unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
                reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
-                *IXDP2X01_CPLD_RESET_REG = reset_reg;
+                ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
-                mb();
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
-                *IXDP2X01_CPLD_RESET_REG = 0x80000000;
        }
-        /*
+        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
-         * We do a reset all if we are PCI master. We could be a slave and we
-         * don't want to do anything funky on the PCI bus.
-         */
-        if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
-                *(IXP2000_RESET0) |= (RSTALL);
-        }
 }
diff --git a/include/asm-arm/arch-ixp2000/uengine.h b/include/asm-arm/arch-ixp2000/uengine.h
new file mode 100644
index 000000000000..b442d65c6593
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/uengine.h
@@ -0,0 +1,62 @@
+/*
+ * Generic library functions for the microengines found on the Intel
+ * IXP2000 series of network processors.
+ *
+ * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Dedicated to Marija Kulikova.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2.1 of the
+ * License, or (at your option) any later version.
+ */
+#ifndef __IXP2000_UENGINE_H
+#define __IXP2000_UENGINE_H
+extern u32 ixp2000_uengine_mask;
+struct ixp2000_uengine_code
+{
+        u32     cpu_model_bitmask;
+        u8      cpu_min_revision;
+        u8      cpu_max_revision;
+        u32     uengine_parameters;
+        struct ixp2000_reg_value {
+                int     reg;
+                u32     value;
+        } *initial_reg_values;
+        int     num_insns;
+        u8      *insns;
+};
+u32 ixp2000_uengine_csr_read(int uengine, int offset);
+void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
+void ixp2000_uengine_reset(u32 uengine_mask);
+void ixp2000_uengine_set_mode(int uengine, u32 mode);
+void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
+void ixp2000_uengine_init_context(int uengine, int context, int pc);
+void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
+void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
+int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
+#define IXP2000_UENGINE_8_CONTEXTS              0x00000000
+#define IXP2000_UENGINE_4_CONTEXTS              0x80000000
+#define IXP2000_UENGINE_PRN_UPDATE_EVERY        0x40000000
+#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS    0x00000000
+#define IXP2000_UENGINE_NN_FROM_SELF            0x00100000
+#define IXP2000_UENGINE_NN_FROM_PREVIOUS        0x00000000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3       0x000c0000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2       0x00080000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1       0x00040000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0       0x00000000
+#define IXP2000_UENGINE_LM_ADDR1_GLOBAL         0x00020000
+#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT    0x00000000
+#define IXP2000_UENGINE_LM_ADDR0_GLOBAL         0x00010000
+#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT    0x00000000
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index e350dcb544e8..688f7f90d93e 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -80,9 +80,9 @@ __ixp4xx_iounmap(void __iomem *addr)
 #define __arch_ioremap(a, s, f, x)      __ixp4xx_ioremap(a, s, f, x)
 #define __arch_iounmap(a)               __ixp4xx_iounmap(a)
-#define writeb(p, v)                    __ixp4xx_writeb(p, v)
+#define writeb(v, p)                    __ixp4xx_writeb(v, p)
-#define writew(p, v)                    __ixp4xx_writew(p, v)
+#define writew(v, p)                    __ixp4xx_writew(v, p)
-#define writel(p, v)                    __ixp4xx_writel(p, v)
+#define writel(v, p)                    __ixp4xx_writel(v, p)
 #define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
 #define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
@@ -97,8 +97,9 @@ __ixp4xx_iounmap(void __iomem *addr)
 #define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
 static inline void 
-__ixp4xx_writeb(u8 value, u32 addr)
+__ixp4xx_writeb(u8 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START) {
@@ -113,15 +114,16 @@ __ixp4xx_writeb(u8 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
+__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
 {
        while (count--)
                writeb(*vaddr++, bus_addr);
 }
 static inline void 
-__ixp4xx_writew(u16 value, u32 addr)
+__ixp4xx_writew(u16 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START) {
@@ -136,15 +138,16 @@ __ixp4xx_writew(u16 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
+__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
 {
        while (count--)
                writew(*vaddr++, bus_addr);
 }
 static inline void 
-__ixp4xx_writel(u32 value, u32 addr)
+__ixp4xx_writel(u32 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        if (addr >= VMALLOC_START) {
                __raw_writel(value, addr);
                return;
@@ -154,15 +157,16 @@ __ixp4xx_writel(u32 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
+__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
 {
        while (count--)
                writel(*vaddr++, bus_addr);
 }
 static inline unsigned char 
-__ixp4xx_readb(u32 addr)
+__ixp4xx_readb(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START)
@@ -177,15 +181,16 @@ __ixp4xx_readb(u32 addr)
 }
 static inline void
-__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
+__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readb(bus_addr);
 }
 static inline unsigned short 
-__ixp4xx_readw(u32 addr)
+__ixp4xx_readw(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START)
@@ -200,15 +205,16 @@ __ixp4xx_readw(u32 addr)
 }
 static inline void 
-__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
+__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readw(bus_addr);
 }
 static inline unsigned long 
-__ixp4xx_readl(u32 addr)
+__ixp4xx_readl(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 data;
        if (addr >= VMALLOC_START)
@@ -221,7 +227,7 @@ __ixp4xx_readl(u32 addr)
 }
 static inline void 
-__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
+__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readl(bus_addr);
@@ -239,7 +245,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
                                eth_copy_and_sum((s),__mem_pci(c),(l),(b))
 static inline int
-check_signature(unsigned long bus_addr, const unsigned char *signature,
+check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature,
                int length)
 {
        int retval = 0;
@@ -389,7 +395,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 static inline unsigned int
-__ixp4xx_ioread8(void __iomem *addr)
+__ixp4xx_ioread8(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -398,12 +404,12 @@ __ixp4xx_ioread8(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return (unsigned int)__raw_readb(port);
 #else
-                return (unsigned int)__ixp4xx_readb(port);
+                return (unsigned int)__ixp4xx_readb(addr);
 #endif
 }
 static inline void
-__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -412,12 +418,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsb(addr, vaddr, count);
 #else
-                __ixp4xx_readsb(port, vaddr, count);
+                __ixp4xx_readsb(addr, vaddr, count);
 #endif
 }
 static inline unsigned int
-__ixp4xx_ioread16(void __iomem *addr)
+__ixp4xx_ioread16(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -426,12 +432,12 @@ __ixp4xx_ioread16(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return le16_to_cpu(__raw_readw((u32)port));
 #else
-                return (unsigned int)__ixp4xx_readw((u32)port);
+                return (unsigned int)__ixp4xx_readw(addr);
 #endif
 }
 static inline void
-__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -440,12 +446,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsw(addr, vaddr, count);
 #else
-                __ixp4xx_readsw(port, vaddr, count);
+                __ixp4xx_readsw(addr, vaddr, count);
 #endif
 }
 static inline unsigned int
-__ixp4xx_ioread32(void __iomem *addr)
+__ixp4xx_ioread32(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -454,13 +460,13 @@ __ixp4xx_ioread32(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return le32_to_cpu(__raw_readl((u32)port));
 #else
-                return (unsigned int)__ixp4xx_readl((u32)port);
+                return (unsigned int)__ixp4xx_readl(addr);
 #endif
        }
 }
 static inline void
-__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -469,7 +475,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsl(addr, vaddr, count);
 #else
-                __ixp4xx_readsl(port, vaddr, count);
+                __ixp4xx_readsl(addr, vaddr, count);
 #endif
 }
@@ -483,7 +489,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writeb(value, port);
 #else
-                __ixp4xx_writeb(value, port);
+                __ixp4xx_writeb(value, addr);
 #endif
 }
@@ -497,7 +503,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesb(addr, vaddr, count);
 #else
-                __ixp4xx_writesb(port, vaddr, count);
+                __ixp4xx_writesb(addr, vaddr, count);
 #endif
 }
@@ -511,7 +517,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writew(cpu_to_le16(value), addr);
 #else
-                __ixp4xx_writew(value, port);
+                __ixp4xx_writew(value, addr);
 #endif
 }
@@ -525,7 +531,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesw(addr, vaddr, count);
 #else
-                __ixp4xx_writesw(port, vaddr, count);
+                __ixp4xx_writesw(addr, vaddr, count);
 #endif
 }
@@ -539,7 +545,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writel(cpu_to_le32(value), port);
 #else
-                __ixp4xx_writel(value, port);
+                __ixp4xx_writel(value, addr);
 #endif
 }
@@ -553,7 +559,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesl(addr, vaddr, count);
 #else
-                __ixp4xx_writesl(port, vaddr, count);
+                __ixp4xx_writesl(addr, vaddr, count);
 #endif
 }
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 004696a95bdb..2b149ed59149 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -36,11 +36,11 @@
 *
 * 0x6000000    0x00004000      ioremap'd       QMgr
 *
- * 0xC0000000   0x00001000      0xffbfe000      PCI CFG 
+ * 0xC0000000   0x00001000      0xffbff000      PCI CFG
 *
- * 0xC4000000   0x00001000      0xffbfd000      EXP CFG 
+ * 0xC4000000   0x00001000      0xffbfe000      EXP CFG
 *
- * 0xC8000000   0x0000C000      0xffbf2000      On-Chip Peripherals
+ * 0xC8000000   0x00013000      0xffbeb000      On-Chip Peripherals
 */
 /*
@@ -52,22 +52,22 @@
 * Expansion BUS Configuration registers
 */
 #define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFD000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
 /*
 * PCI Config registers
 */
 #define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
 /*
 * Peripheral space
 */
 #define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBF2000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
-#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x0000C000)
+#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 /*
 * Debug UART
@@ -115,25 +115,48 @@
 /*
 * Peripheral Space Register Region Base Addresses
 */
-#define IXP4XX_UART1_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP4XX_UART1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP4XX_UART2_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP4XX_UART2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP4XX_PMU_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP4XX_PMU_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP4XX_INTC_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP4XX_INTC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP4XX_GPIO_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP4XX_GPIO_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP4XX_TIMER_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP4XX_TIMER_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP4XX_EthA_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP4XX_NPEA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP4XX_EthB_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP4XX_NPEB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP4XX_USB_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
+#define IXP4XX_NPEC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP4XX_UART1_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_EthC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP4XX_UART2_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_USB_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
-#define IXP4XX_PMU_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+/* ixp46X only */
-#define IXP4XX_INTC_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_EthA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
-#define IXP4XX_GPIO_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_EthB1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
-#define IXP4XX_TIMER_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_EthB2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
-#define IXP4XX_EthA_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthB3_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
-#define IXP4XX_EthB_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_TIMESYNC_BASE_PHYS       (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
-#define IXP4XX_USB_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+#define IXP4XX_I2C_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
+#define IXP4XX_SSP_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
+#define IXP4XX_UART1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_UART2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_PMU_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP4XX_INTC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_GPIO_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_TIMER_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_NPEA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP4XX_NPEB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP4XX_NPEC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_USB_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+/* ixp46X only */
+#define IXP4XX_EthA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
+#define IXP4XX_EthB1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
+#define IXP4XX_EthB2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
+#define IXP4XX_EthB3_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
+#define IXP4XX_TIMESYNC_BASE_VIRT       (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
+#define IXP4XX_I2C_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
+#define IXP4XX_SSP_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
 /*
 * Constants to make it easy to access  Interrupt Controller registers
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
index d348548b592b..e024d0a1a669 100644
--- a/include/asm-arm/arch-ixp4xx/memory.h
+++ b/include/asm-arm/arch-ixp4xx/memory.h
@@ -12,7 +12,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index fc012a39e2cb..cab8ad0adf09 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -10,7 +10,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h
index c5b9608cb137..9e50a171f78a 100644
--- a/include/asm-arm/arch-l7200/memory.h
+++ b/include/asm-arm/arch-l7200/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset on the L7200 SDB.
 */
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 #define __virt_to_bus(x) __virt_to_phys(x)
 #define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
index c13bdd9add92..bbcd4335f441 100644
--- a/include/asm-arm/arch-lh7a40x/io.h
+++ b/include/asm-arm/arch-lh7a40x/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /* No ISA or PCI bus on this machine. */
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index c650e6feb9d5..c92bcb837629 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -17,7 +17,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 11fbf629bf75..3d5bcd545082 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -34,6 +34,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index ef32d61eec7a..bf545b6e0a26 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -37,9 +37,9 @@
 * Physical DRAM offset.
 */
 #if defined(CONFIG_ARCH_OMAP1)
-#define PHYS_OFFSET             (0x10000000UL)
+#define PHYS_OFFSET             UL(0x10000000)
 #elif defined(CONFIG_ARCH_OMAP2)
-#define PHYS_OFFSET             (0x80000000UL)
+#define PHYS_OFFSET             UL(0x80000000)
 #endif
 /*
@@ -66,7 +66,7 @@
 /*
 * OMAP-1510 Local Bus address offset
 */
-#define OMAP1510_LB_OFFSET      (0x30000000UL)
+#define OMAP1510_LB_OFFSET      UL(0x30000000)
 #define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index cf35721cfa45..3e70bd95472c 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -44,12 +44,12 @@
 #ifndef __ASSEMBLY__
-# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
+# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
 /* With indexed regs we don't want to feed the index through io_p2v()
   especially if it is a variable, otherwise horrible code will result. */
 # define __REG2(x,y)    \
-        (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
+        (*(volatile u32 *)((u32)&__REG(x) + (y)))
 # define __PREG(x)      (io_v2p((u32)&(x)))
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
index c3bdbe44e21f..eb2dd58d397f 100644
--- a/include/asm-arm/arch-pxa/io.h
+++ b/include/asm-arm/arch-pxa/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
new file mode 100644
index 000000000000..748406f384c2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_ARCH_IRDA_H
+#define ASMARM_ARCH_IRDA_H
+/* board specific transceiver capabilities */
+#define IR_OFF          1
+#define IR_SIRMODE      2
+#define IR_FIRMODE      4
+struct pxaficp_platform_data {
+        int transceiver_cap;
+        void (*transceiver_mode)(struct device *dev, int mode);
+};
+extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
+#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index 58bad9748b5c..eaf6d43939e9 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 3af7165ab0d7..a75a2470f4f5 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -326,6 +326,25 @@
 #define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
 #define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+/* Hardware UART (HWUART) */
+#define HWUART          HWRBR
+#define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
+#define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
+#define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
+#define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
+#define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
+#define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
+#define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
+#define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
+#define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
+#define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
+#define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
+#define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
+#define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
+#define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
+#define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 #define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
 #define IER_UUE         (1 << 6)        /* UART Unit Enable */
 #define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
@@ -1013,14 +1032,12 @@
 #define ICCR0_LBM       (1 << 1)        /* Loopback mode */
 #define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
-#ifdef CONFIG_PXA27x
 #define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
 #define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
 #define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
 #define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
 #define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
 #define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
-#endif
 #ifdef CONFIG_PXA27x
 #define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
@@ -1250,9 +1267,13 @@
 #define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
 #define GPIO41_FFRTS            41      /* FFUART request to send */
 #define GPIO42_BTRXD            42      /* BTUART receive data */
+#define GPIO42_HWRXD            42      /* HWUART receive data */
 #define GPIO43_BTTXD            43      /* BTUART transmit data */
+#define GPIO43_HWTXD            43      /* HWUART transmit data */
 #define GPIO44_BTCTS            44      /* BTUART clear to send */
+#define GPIO44_HWCTS            44      /* HWUART clear to send */
 #define GPIO45_BTRTS            45      /* BTUART request to send */
+#define GPIO45_HWRTS            45      /* HWUART request to send */
 #define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
 #define GPIO46_ICPRXD           46      /* ICP receive data */
 #define GPIO46_STRXD            46      /* STD_UART receive data */
@@ -1378,17 +1399,26 @@
 #define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
 #define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
 #define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
 #define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
 #define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
 #define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
 #define GPIO45_SYSCLK_AC97_MD           (45 | GPIO_ALT_FN_1_OUT)
 #define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
 #define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
 #define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
 #define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
 #define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
 #define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
 #define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
 #define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
 #define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
 #define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
@@ -1763,6 +1793,7 @@
 #define CKEN7_BTUART    (1 << 7)        /* BTUART Unit Clock Enable */
 #define CKEN6_FFUART    (1 << 6)        /* FFUART Unit Clock Enable */
 #define CKEN5_STUART    (1 << 5)        /* STUART Unit Clock Enable */
+#define CKEN4_HWUART    (1 << 4)        /* HWUART Unit Clock Enable */
 #define CKEN4_SSP3      (1 << 4)        /* SSP3 Unit Clock Enable */
 #define CKEN3_SSP       (1 << 3)        /* SSP Unit Clock Enable */
 #define CKEN3_SSP2      (1 << 3)        /* SSP2 Unit Clock Enable */
@@ -2282,4 +2313,11 @@
 #endif
+/* PWRMODE register M field values */
+#define PWRMODE_IDLE            0x1
+#define PWRMODE_STANDBY         0x2
+#define PWRMODE_SLEEP           0x3
+#define PWRMODE_DEEPSLEEP       0x7
 #endif
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 4428d3eb7432..fe38090444e0 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -12,6 +12,7 @@
 #define FFUART          ((volatile unsigned long *)0x40100000)
 #define BTUART          ((volatile unsigned long *)0x40200000)
 #define STUART          ((volatile unsigned long *)0x40700000)
+#define HWUART          ((volatile unsigned long *)0x41600000)
 #define UART            FFUART
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
new file mode 100644
index 000000000000..ed28bd012236
--- /dev/null
+++ b/include/asm-arm/arch-realview/debug-macro.S
@@ -0,0 +1,38 @@
+/* linux/include/asm-arm/arch-realview/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <asm/hardware/amba_serial.h>
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx,      #0x10000000
+                movne   \rx,      #0xf1000000   @ virtual base
+                orr     \rx, \rx, #0x00009000
+                .endm
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #UART01x_DR]
+                .endm
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-realview/dma.h b/include/asm-arm/arch-realview/dma.h
new file mode 100644
index 000000000000..744491a74bd9
--- /dev/null
+++ b/include/asm-arm/arch-realview/dma.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/include/asm-arm/arch-realview/dma.h
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
new file mode 100644
index 000000000000..2712ba77bb3a
--- /dev/null
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -0,0 +1,49 @@
+/*
+ * include/asm-arm/arch-realview/entry-macro.S
+ *
+ * Low-level IRQ helper macros for RealView platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware/gic.h>
+                .macro  disable_fiq
+                .endm
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an interrupt if it's
+                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+                 *
+                 * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+                 * valid range for an IRQ (30-1020 inclusive).
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+                ldr     \tmp, =1021
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+                .endm
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
new file mode 100644
index 000000000000..67879cdb6ef2
--- /dev/null
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -0,0 +1,31 @@
+/*
+ *  linux/include/asm-arm/arch-realview/hardware.h
+ *
+ *  This file contains the hardware definitions of the RealView boards.
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/sizes.h>
+#include <asm/arch/platform.h>
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+#endif
diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h
new file mode 100644
index 000000000000..d444a68ac330
--- /dev/null
+++ b/include/asm-arm/arch-realview/io.h
@@ -0,0 +1,34 @@
+/*
+ *  linux/include/asm-arm/arch-realview/io.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
new file mode 100644
index 000000000000..ff376494e5b1
--- /dev/null
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -0,0 +1,103 @@
+/*
+ *  linux/include/asm-arm/arch-realview/irqs.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/arch/platform.h>
+/* 
+ *  IRQ interrupts definitions are the same the INT definitions
+ *  held within platform.h
+ */
+#define IRQ_GIC_START           32
+#define IRQ_WDOGINT             (IRQ_GIC_START + INT_WDOGINT)
+#define IRQ_SOFTINT             (IRQ_GIC_START + INT_SOFTINT)
+#define IRQ_COMMRx              (IRQ_GIC_START + INT_COMMRx)
+#define IRQ_COMMTx              (IRQ_GIC_START + INT_COMMTx)
+#define IRQ_TIMERINT0_1         (IRQ_GIC_START + INT_TIMERINT0_1)
+#define IRQ_TIMERINT2_3         (IRQ_GIC_START + INT_TIMERINT2_3)
+#define IRQ_GPIOINT0            (IRQ_GIC_START + INT_GPIOINT0)
+#define IRQ_GPIOINT1            (IRQ_GIC_START + INT_GPIOINT1)
+#define IRQ_GPIOINT2            (IRQ_GIC_START + INT_GPIOINT2)
+#define IRQ_GPIOINT3            (IRQ_GIC_START + INT_GPIOINT3)
+#define IRQ_RTCINT              (IRQ_GIC_START + INT_RTCINT)
+#define IRQ_SSPINT              (IRQ_GIC_START + INT_SSPINT)
+#define IRQ_UARTINT0            (IRQ_GIC_START + INT_UARTINT0)
+#define IRQ_UARTINT1            (IRQ_GIC_START + INT_UARTINT1)
+#define IRQ_UARTINT2            (IRQ_GIC_START + INT_UARTINT2)
+#define IRQ_UART3               (IRQ_GIC_START + INT_UARTINT3)
+#define IRQ_SCIINT              (IRQ_GIC_START + INT_SCIINT)
+#define IRQ_CLCDINT             (IRQ_GIC_START + INT_CLCDINT)
+#define IRQ_DMAINT              (IRQ_GIC_START + INT_DMAINT)
+#define IRQ_PWRFAILINT          (IRQ_GIC_START + INT_PWRFAILINT)
+#define IRQ_MBXINT              (IRQ_GIC_START + INT_MBXINT)
+#define IRQ_GNDINT              (IRQ_GIC_START + INT_GNDINT)
+#define IRQ_MMCI0B              (IRQ_GIC_START + INT_MMCI0B)
+#define IRQ_MMCI1B              (IRQ_GIC_START + INT_MMCI1B)
+#define IRQ_KMI0                (IRQ_GIC_START + INT_KMI0)
+#define IRQ_KMI1                (IRQ_GIC_START + INT_KMI1)
+#define IRQ_SCI3                (IRQ_GIC_START + INT_SCI3)
+#define IRQ_CLCD                (IRQ_GIC_START + INT_CLCD)
+#define IRQ_TOUCH               (IRQ_GIC_START + INT_TOUCH)
+#define IRQ_KEYPAD              (IRQ_GIC_START + INT_KEYPAD)
+#define IRQ_DoC                 (IRQ_GIC_START + INT_DoC)
+#define IRQ_MMCI0A              (IRQ_GIC_START + INT_MMCI0A)
+#define IRQ_MMCI1A              (IRQ_GIC_START + INT_MMCI1A)
+#define IRQ_AACI                (IRQ_GIC_START + INT_AACI)
+#define IRQ_ETH                 (IRQ_GIC_START + INT_ETH)
+#define IRQ_USB                 (IRQ_GIC_START + INT_USB)
+#define IRQMASK_WDOGINT         INTMASK_WDOGINT
+#define IRQMASK_SOFTINT         INTMASK_SOFTINT
+#define IRQMASK_COMMRx          INTMASK_COMMRx
+#define IRQMASK_COMMTx          INTMASK_COMMTx
+#define IRQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
+#define IRQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
+#define IRQMASK_GPIOINT0        INTMASK_GPIOINT0
+#define IRQMASK_GPIOINT1        INTMASK_GPIOINT1
+#define IRQMASK_GPIOINT2        INTMASK_GPIOINT2
+#define IRQMASK_GPIOINT3        INTMASK_GPIOINT3
+#define IRQMASK_RTCINT          INTMASK_RTCINT
+#define IRQMASK_SSPINT          INTMASK_SSPINT
+#define IRQMASK_UARTINT0        INTMASK_UARTINT0
+#define IRQMASK_UARTINT1        INTMASK_UARTINT1
+#define IRQMASK_UARTINT2        INTMASK_UARTINT2
+#define IRQMASK_SCIINT          INTMASK_SCIINT
+#define IRQMASK_CLCDINT         INTMASK_CLCDINT
+#define IRQMASK_DMAINT          INTMASK_DMAINT
+#define IRQMASK_PWRFAILINT      INTMASK_PWRFAILINT
+#define IRQMASK_MBXINT          INTMASK_MBXINT
+#define IRQMASK_GNDINT          INTMASK_GNDINT
+#define IRQMASK_MMCI0B          INTMASK_MMCI0B
+#define IRQMASK_MMCI1B          INTMASK_MMCI1B
+#define IRQMASK_KMI0            INTMASK_KMI0
+#define IRQMASK_KMI1            INTMASK_KMI1
+#define IRQMASK_SCI3            INTMASK_SCI3
+#define IRQMASK_UART3           INTMASK_UART3
+#define IRQMASK_CLCD            INTMASK_CLCD
+#define IRQMASK_TOUCH           INTMASK_TOUCH
+#define IRQMASK_KEYPAD          INTMASK_KEYPAD
+#define IRQMASK_DoC             INTMASK_DoC
+#define IRQMASK_MMCI0A          INTMASK_MMCI0A
+#define IRQMASK_MMCI1A          INTMASK_MMCI1A
+#define IRQMASK_AACI            INTMASK_AACI
+#define IRQMASK_ETH             INTMASK_ETH
+#define IRQMASK_USB             INTMASK_USB
+#define NR_IRQS                 (IRQ_GIC_START + 64)
diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h
new file mode 100644
index 000000000000..ed370abb638f
--- /dev/null
+++ b/include/asm-arm/arch-realview/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-realview/memory.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x00000000)
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+#endif
diff --git a/include/asm-arm/arch-realview/param.h b/include/asm-arm/arch-realview/param.h
new file mode 100644
index 000000000000..89b1235d32bd
--- /dev/null
+++ b/include/asm-arm/arch-realview/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-realview/param.h
+ *
+ *  Copyright (C) 2002 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
new file mode 100644
index 000000000000..4b6de13a6b9a
--- /dev/null
+++ b/include/asm-arm/arch-realview/platform.h
@@ -0,0 +1,395 @@
+/*
+ * linux/include/asm-arm/arch-realview/platform.h
+ *
+ * Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __address_h
+#define __address_h                     1
+/*
+ * Memory definitions
+ */
+#define REALVIEW_BOOT_ROM_LO          0x30000000                /* DoC Base (64Mb)...*/
+#define REALVIEW_BOOT_ROM_HI          0x30000000
+#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI       /*  Normal position */
+#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
+#define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
+#define REALVIEW_SSRAM_SIZE           SZ_2M
+#define REALVIEW_FLASH_BASE           0x40000000
+#define REALVIEW_FLASH_SIZE           SZ_64M
+/* 
+ *  SDRAM
+ */
+#define REALVIEW_SDRAM_BASE           0x00000000
+/* 
+ *  Logic expansion modules
+ * 
+ */
+/* ------------------------------------------------------------------------
+ *  RealView Registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define REALVIEW_SYS_ID_OFFSET               0x00
+#define REALVIEW_SYS_SW_OFFSET               0x04
+#define REALVIEW_SYS_LED_OFFSET              0x08
+#define REALVIEW_SYS_OSC0_OFFSET             0x0C
+#define REALVIEW_SYS_OSC1_OFFSET             0x10
+#define REALVIEW_SYS_OSC2_OFFSET             0x14
+#define REALVIEW_SYS_OSC3_OFFSET             0x18
+#define REALVIEW_SYS_OSC4_OFFSET             0x1C       /* OSC1 for RealView/AB */
+#define REALVIEW_SYS_LOCK_OFFSET             0x20
+#define REALVIEW_SYS_100HZ_OFFSET            0x24
+#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
+#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
+#define REALVIEW_SYS_FLAGS_OFFSET            0x30
+#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
+#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
+#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
+#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
+#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
+#define REALVIEW_SYS_PCICTL_OFFSET           0x44
+#define REALVIEW_SYS_MCI_OFFSET              0x48
+#define REALVIEW_SYS_FLASH_OFFSET            0x4C
+#define REALVIEW_SYS_CLCD_OFFSET             0x50
+#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
+#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
+#define REALVIEW_SYS_24MHz_OFFSET            0x5C
+#define REALVIEW_SYS_MISC_OFFSET             0x60
+#define REALVIEW_SYS_IOSEL_OFFSET            0x70
+#define REALVIEW_SYS_TEST_OSC0_OFFSET        0x80
+#define REALVIEW_SYS_TEST_OSC1_OFFSET        0x84
+#define REALVIEW_SYS_TEST_OSC2_OFFSET        0x88
+#define REALVIEW_SYS_TEST_OSC3_OFFSET        0x8C
+#define REALVIEW_SYS_TEST_OSC4_OFFSET        0x90
+#define REALVIEW_SYS_BASE                    0x10000000
+#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
+#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
+#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
+#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
+#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
+#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
+#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
+#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
+#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
+#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
+#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
+#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
+#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
+#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
+#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
+#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
+#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
+#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
+#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
+#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
+#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
+#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
+#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
+#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
+#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
+#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
+#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
+#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
+#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
+/* 
+ * Values for REALVIEW_SYS_RESET_CTRL
+ */
+#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR    0x01
+#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT   0x02
+#define REALVIEW_SYS_CTRL_RESET_DLLRESET     0x03
+#define REALVIEW_SYS_CTRL_RESET_PLLRESET     0x04
+#define REALVIEW_SYS_CTRL_RESET_POR          0x05
+#define REALVIEW_SYS_CTRL_RESET_DoC          0x06
+#define REALVIEW_SYS_CTRL_LED         (1 << 0)
+/* ------------------------------------------------------------------------
+ *  RealView control registers
+ * ------------------------------------------------------------------------
+ */
+/* 
+ * REALVIEW_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+/*
+ * REALVIEW_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
+#define REALVIEW_SYS_LOCKVAL_MASK       0xFFFF          /* write 0xA05F to enable write access */
+/*
+ * REALVIEW_SYS_FLASH
+ */
+#define REALVIEW_FLASHPROG_FLVPPEN      (1 << 0)        /* Enable writing to flash */
+/*
+ * REALVIEW_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts 
+ */
+#define REALVIEW_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
+#define REALVIEW_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
+#define REALVIEW_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
+                                                /* write 1 to acknowledge and clear               */
+#define REALVIEW_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
+#define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
+/*
+ * REALVIEW peripheral addresses
+ */
+#define REALVIEW_SCTL_BASE            0x10001000        /* System controller */
+#define REALVIEW_I2C_BASE             0x10002000        /* I2C control */
+        /* Reserved 0x10003000 */
+#define REALVIEW_AACI_BASE            0x10004000        /* Audio */
+#define REALVIEW_MMCI0_BASE           0x10005000        /* MMC interface */
+#define REALVIEW_KMI0_BASE            0x10006000        /* KMI interface */
+#define REALVIEW_KMI1_BASE            0x10007000        /* KMI 2nd interface */
+#define REALVIEW_CHAR_LCD_BASE        0x10008000        /* Character LCD */
+#define REALVIEW_UART0_BASE           0x10009000        /* UART 0 */
+#define REALVIEW_UART1_BASE           0x1000A000        /* UART 1 */
+#define REALVIEW_UART2_BASE           0x1000B000        /* UART 2 */
+#define REALVIEW_UART3_BASE           0x1000C000        /* UART 3 */
+#define REALVIEW_SSP_BASE             0x1000D000        /* Synchronous Serial Port */
+#define REALVIEW_SCI_BASE             0x1000E000        /* Smart card controller */
+        /* Reserved 0x1000F000 */
+#define REALVIEW_WATCHDOG_BASE        0x10010000        /* watchdog interface */
+#define REALVIEW_TIMER0_1_BASE        0x10011000        /* Timer 0 and 1 */
+#define REALVIEW_TIMER2_3_BASE        0x10012000        /* Timer 2 and 3 */
+#define REALVIEW_GPIO0_BASE           0x10013000        /* GPIO port 0 */
+#define REALVIEW_GPIO1_BASE           0x10014000        /* GPIO port 1 */
+#define REALVIEW_GPIO2_BASE           0x10015000        /* GPIO port 2 */
+        /* Reserved 0x10016000 */
+#define REALVIEW_RTC_BASE             0x10017000        /* Real Time Clock */
+#define REALVIEW_DMC_BASE             0x10018000        /* DMC configuration */
+#define REALVIEW_PCI_CORE_BASE        0x10019000        /* PCI configuration */
+        /* Reserved 0x1001A000 - 0x1001FFFF */
+#define REALVIEW_CLCD_BASE            0x10020000        /* CLCD */
+#define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
+#define REALVIEW_GIC_CPU_BASE         0x10040000        /* Generic interrupt controller CPU interface */
+#define REALVIEW_GIC_DIST_BASE        0x10041000        /* Generic interrupt controller distributor */
+#define REALVIEW_SMC_BASE             0x10080000        /* SMC */
+        /* Reserved 0x10090000 - 0x100EFFFF */
+#define REALVIEW_ETH_BASE             0x4E000000        /* Ethernet */
+/* PCI space */
+#define REALVIEW_PCI_BASE             0x41000000        /* PCI Interface */
+#define REALVIEW_PCI_CFG_BASE         0x42000000
+#define REALVIEW_PCI_MEM_BASE0        0x44000000
+#define REALVIEW_PCI_MEM_BASE1        0x50000000
+#define REALVIEW_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define REALVIEW_PCI_BASE_SIZE         0x01000000
+#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
+#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000        /* 32Mb */
+#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000        /* 256Mb */
+#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000        /* 256Mb */
+#define REALVIEW_SDRAM67_BASE         0x70000000        /* SDRAM banks 6 and 7 */
+#define REALVIEW_LT_BASE              0x80000000        /* Logic Tile expansion */
+/*
+ * Disk on Chip
+ */
+#define REALVIEW_DOC_BASE             0x2C000000
+#define REALVIEW_DOC_SIZE             (16 << 20)
+#define REALVIEW_DOC_PAGE_SIZE        512
+#define REALVIEW_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
+#define ERASE_UNIT_PAGES    32
+#define START_PAGE          0x80
+/* 
+ *  LED settings, bits [7:0]
+ */
+#define REALVIEW_SYS_LED0             (1 << 0)
+#define REALVIEW_SYS_LED1             (1 << 1)
+#define REALVIEW_SYS_LED2             (1 << 2)
+#define REALVIEW_SYS_LED3             (1 << 3)
+#define REALVIEW_SYS_LED4             (1 << 4)
+#define REALVIEW_SYS_LED5             (1 << 5)
+#define REALVIEW_SYS_LED6             (1 << 6)
+#define REALVIEW_SYS_LED7             (1 << 7)
+#define ALL_LEDS                  0xFF
+#define LED_BANK                  REALVIEW_SYS_LED
+/* 
+ * Control registers
+ */
+#define REALVIEW_IDFIELD_OFFSET 0x0     /* RealView build information */
+#define REALVIEW_FLASHPROG_OFFSET       0x4     /* Flash devices */
+#define REALVIEW_INTREG_OFFSET          0x8     /* Interrupt control */
+#define REALVIEW_DECODE_OFFSET          0xC     /* Fitted logic modules */
+/* ------------------------------------------------------------------------
+ *  Interrupts - bit assignment (primary)
+ * ------------------------------------------------------------------------
+ */
+#define INT_WDOGINT                     0       /* Watchdog timer */
+#define INT_SOFTINT                     1       /* Software interrupt */
+#define INT_COMMRx                      2       /* Debug Comm Rx interrupt */
+#define INT_COMMTx                      3       /* Debug Comm Tx interrupt */
+#define INT_TIMERINT0_1                 4       /* Timer 0 and 1 */
+#define INT_TIMERINT2_3                 5       /* Timer 2 and 3 */
+#define INT_GPIOINT0                    6       /* GPIO 0 */
+#define INT_GPIOINT1                    7       /* GPIO 1 */
+#define INT_GPIOINT2                    8       /* GPIO 2 */
+/* 9 reserved */
+#define INT_RTCINT                      10      /* Real Time Clock */
+#define INT_SSPINT                      11      /* Synchronous Serial Port */
+#define INT_UARTINT0                    12      /* UART 0 on development chip */
+#define INT_UARTINT1                    13      /* UART 1 on development chip */
+#define INT_UARTINT2                    14      /* UART 2 on development chip */
+#define INT_UARTINT3                    15      /* UART 3 on development chip */
+#define INT_SCIINT                      16      /* Smart Card Interface */
+#define INT_MMCI0A                      17      /* Multimedia Card 0A */
+#define INT_MMCI0B                      18      /* Multimedia Card 0B */
+#define INT_AACI                        19      /* Audio Codec */
+#define INT_KMI0                        20      /* Keyboard/Mouse port 0 */
+#define INT_KMI1                        21      /* Keyboard/Mouse port 1 */
+#define INT_CHARLCD                     22      /* Character LCD */
+#define INT_CLCDINT                     23      /* CLCD controller */
+#define INT_DMAINT                      24      /* DMA controller */
+#define INT_PWRFAILINT                  25      /* Power failure */
+#define INT_PISMO                       26
+#define INT_DoC                         27      /* Disk on Chip memory controller */
+#define INT_ETH                         28      /* Ethernet controller */
+#define INT_USB                         29      /* USB controller */
+#define INT_TSPENINT                    30      /* Touchscreen pen */
+#define INT_TSKPADINT                   31      /* Touchscreen keypad */
+/* 
+ *  Interrupt bit positions
+ * 
+ */
+#define INTMASK_WDOGINT                 (1 << INT_WDOGINT)
+#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
+#define INTMASK_COMMRx                  (1 << INT_COMMRx)
+#define INTMASK_COMMTx                  (1 << INT_COMMTx)
+#define INTMASK_TIMERINT0_1             (1 << INT_TIMERINT0_1)
+#define INTMASK_TIMERINT2_3             (1 << INT_TIMERINT2_3)
+#define INTMASK_GPIOINT0                (1 << INT_GPIOINT0)
+#define INTMASK_GPIOINT1                (1 << INT_GPIOINT1)
+#define INTMASK_GPIOINT2                (1 << INT_GPIOINT2)
+#define INTMASK_RTCINT                  (1 << INT_RTCINT)
+#define INTMASK_SSPINT                  (1 << INT_SSPINT)
+#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
+#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
+#define INTMASK_UARTINT2                (1 << INT_UARTINT2)
+#define INTMASK_UARTINT3                (1 << INT_UARTINT3)
+#define INTMASK_SCIINT                  (1 << INT_SCIINT)
+#define INTMASK_MMCI0A                  (1 << INT_MMCI0A)
+#define INTMASK_MMCI0B                  (1 << INT_MMCI0B)
+#define INTMASK_AACI                    (1 << INT_AACI)
+#define INTMASK_KMI0                    (1 << INT_KMI0)
+#define INTMASK_KMI1                    (1 << INT_KMI1)
+#define INTMASK_CHARLCD                 (1 << INT_CHARLCD)
+#define INTMASK_CLCDINT                 (1 << INT_CLCDINT)
+#define INTMASK_DMAINT                  (1 << INT_DMAINT)
+#define INTMASK_PWRFAILINT              (1 << INT_PWRFAILINT)
+#define INTMASK_PISMO                   (1 << INT_PISMO)
+#define INTMASK_DoC                     (1 << INT_DoC)
+#define INTMASK_ETH                     (1 << INT_ETH)
+#define INTMASK_USB                     (1 << INT_USB)
+#define INTMASK_TSPENINT                (1 << INT_TSPENINT)
+#define INTMASK_TSKPADINT               (1 << INT_TSKPADINT)
+#define MAXIRQNUM                       31
+#define MAXFIQNUM                       31
+#define MAXSWINUM                       31
+/* 
+ *  Application Flash
+ * 
+ */
+#define FLASH_BASE                      REALVIEW_FLASH_BASE
+#define FLASH_SIZE                      REALVIEW_FLASH_SIZE
+#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
+#define FLASH_BLOCK_SIZE                SZ_128K
+/* 
+ *  Boot Flash
+ * 
+ */
+#define EPROM_BASE                      REALVIEW_BOOT_ROM_HI
+#define EPROM_SIZE                      REALVIEW_BOOT_ROM_SIZE
+#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      EPROM_BASE
+/*
+ * System controller bit assignment
+ */
+#define REALVIEW_REFCLK 0
+#define REALVIEW_TIMCLK 1
+#define REALVIEW_TIMER1_EnSel   15
+#define REALVIEW_TIMER2_EnSel   17
+#define REALVIEW_TIMER3_EnSel   19
+#define REALVIEW_TIMER4_EnSel   21
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  1
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+#define REALVIEW_CSR_BASE             0x10000000
+#define REALVIEW_CSR_SIZE             0x10000000
+#endif
+/*      END */
diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h
new file mode 100644
index 000000000000..9f8fcbca0869
--- /dev/null
+++ b/include/asm-arm/arch-realview/system.h
@@ -0,0 +1,51 @@
+/*
+ *  linux/include/asm-arm/arch-realview/system.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        unsigned int hdr_ctrl = (IO_ADDRESS(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET);
+        unsigned int val;
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        val = __raw_readl(hdr_ctrl);
+        val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR;
+        __raw_writel(val, hdr_ctrl);
+}
+#endif
diff --git a/include/asm-arm/arch-realview/timex.h b/include/asm-arm/arch-realview/timex.h
new file mode 100644
index 000000000000..5b9d82d0a5e0
--- /dev/null
+++ b/include/asm-arm/arch-realview/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  linux/include/asm-arm/arch-realview/timex.h
+ *
+ *  RealView architecture timex specifications
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
new file mode 100644
index 000000000000..b5e4d360665b
--- /dev/null
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -0,0 +1,54 @@
+/*
+ *  linux/include/asm-arm/arch-realview/uncompress.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/hardware.h>
+#define AMBA_UART_DR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
+#define AMBA_UART_LCRH  (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
+#define AMBA_UART_CR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
+#define AMBA_UART_FR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                while (AMBA_UART_FR & (1 << 5))
+                        barrier();
+                AMBA_UART_DR = *s;
+                if (*s == '\n') {
+                        while (AMBA_UART_FR & (1 << 5))
+                                barrier();
+                        AMBA_UART_DR = '\r';
+                }
+                s++;
+        }
+        while (AMBA_UART_FR & (1 << 3))
+                barrier();
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-realview/vmalloc.h b/include/asm-arm/arch-realview/vmalloc.h
new file mode 100644
index 000000000000..0ad49af186af
--- /dev/null
+++ b/include/asm-arm/arch-realview/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-realview/vmalloc.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index 24453c405a87..b4da08d7a336 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-rpc/memory.h b/include/asm-arm/arch-rpc/memory.h
index 33fc75cdead0..0592cb3f0c74 100644
--- a/include/asm-arm/arch-rpc/memory.h
+++ b/include/asm-arm/arch-rpc/memory.h
@@ -21,7 +21,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 /*
 * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
index ac57bc887d82..4790491ba9d0 100644
--- a/include/asm-arm/arch-s3c2410/fb.h
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -13,6 +13,7 @@
 *      07-Sep-2004     RTP     Created file
 *      03-Nov-2004     BJD     Updated and minor cleanups
 *      03-Aug-2005     RTP     Renamed to fb.h
+ *      26-Oct-2005     BJD     Changed name of platdata init
 */
 #ifndef __ASM_ARM_FB_H
@@ -64,6 +65,6 @@ struct s3c2410fb_mach_info {
        unsigned long   lpcsel;
 };
-void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
+extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
 #endif /* __ASM_ARM_FB_H */
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
index 4bf272ed9add..16fbc8afffd9 100644
--- a/include/asm-arm/arch-s3c2410/io.h
+++ b/include/asm-arm/arch-s3c2410/io.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 3380ab1d0749..6ab834a14c8e 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -28,9 +28,9 @@
 * and at 0x0C000000 for S3C2400
 */
 #ifdef CONFIG_CPU_S3C2400
-#define PHYS_OFFSET     (0x0C000000UL)
+#define PHYS_OFFSET     UL(0x0C000000)
 #else
-#define PHYS_OFFSET     (0x30000000UL)
+#define PHYS_OFFSET     UL(0x30000000)
 #endif
 /*
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 2053cbacffc3..cb33d57c146c 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -20,6 +20,7 @@
 *    18-11-2004     BJD     Added S3C2440 AC97 controls
 *    10-Mar-2005    LCVR    Changed S3C2410_VA to S3C24XX_VA
 *    28-Mar-2005    LCVR    Fixed definition of GPB10
+ *    26-Oct-2005    BJD     Added generic configuration types
 */
@@ -43,6 +44,11 @@
 /* general configuration options */
 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
+#define S3C2410_GPIO_INPUT   (0xFFFFFFF0)
+#define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
+#define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
+#define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* not available on A */
+#define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
 /* configure GPIO ports A..G */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index fdd62e8cd6cb..7fdde9b91cb4 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -55,6 +55,7 @@
 #define S3C2410_IISMOD_16FS       (0<<0)
 #define S3C2410_IISMOD_32FS       (1<<0)
 #define S3C2410_IISMOD_48FS       (2<<0)
+#define S3C2410_IISMOD_FS_MASK    (3<<0)
 #define S3C2410_IISPSR          (0x08)
 #define S3C2410_IISPSR_INTMASK  (31<<5)
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index 19c3b1e186bb..28711aaa4968 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -22,13 +22,6 @@
 /*
- * We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for 
- * in*()/out*() macros to be usable for all cases.
- */
-#define PCIO_BASE               0
-/*
 * SA1100 internal I/O mappings
 *
 * We have the following mapping:
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
index 7d969ffbd3bb..9d4fe6cf205b 100644
--- a/include/asm-arm/arch-sa1100/io.h
+++ b/include/asm-arm/arch-sa1100/io.h
@@ -10,13 +10,19 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
 * We don't actually have real ISA nor PCI buses, but there is so many 
 * drivers out there that might just work if we fake them...
 */
-#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 8743ff5c1b23..0fc555b4c912 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -13,7 +13,7 @@
 /*
 * Physical DRAM offset is 0xc0000000 on the SA1100
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h
index 6f52118ba1a4..0f0612f79b2b 100644
--- a/include/asm-arm/arch-sa1100/system.h
+++ b/include/asm-arm/arch-sa1100/system.h
@@ -4,6 +4,7 @@
 * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
 */
 #include <linux/config.h>
+#include <asm/hardware.h>
 static inline void arch_idle(void)
 {
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
index 5e6ed0038b2b..87ffa27f2962 100644
--- a/include/asm-arm/arch-shark/io.h
+++ b/include/asm-arm/arch-shark/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-shark/memory.h b/include/asm-arm/arch-shark/memory.h
index 8ff956d25463..95a29b4bc5d0 100644
--- a/include/asm-arm/arch-shark/memory.h
+++ b/include/asm-arm/arch-shark/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h
index 7b8b7cc422fa..a9370976cc5e 100644
--- a/include/asm-arm/arch-versatile/memory.h
+++ b/include/asm-arm/arch-versatile/memory.h
@@ -23,7 +23,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/cpu.h b/include/asm-arm/cpu.h
index fcbdd40cb667..751bc7462074 100644
--- a/include/asm-arm/cpu.h
+++ b/include/asm-arm/cpu.h
@@ -16,6 +16,7 @@
 struct cpuinfo_arm {
        struct cpu      cpu;
 #ifdef CONFIG_SMP
+        struct task_struct *idle;
        unsigned int    loops_per_jiffy;
 #endif
 };
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h
index ce4cf5c1c05d..6b8d73dc1ab0 100644
--- a/include/asm-arm/hardware/amba_clcd.h
+++ b/include/asm-arm/hardware/amba_clcd.h
@@ -22,7 +22,7 @@
 #define CLCD_UBAS               0x00000010
 #define CLCD_LBAS               0x00000014
-#ifndef CONFIG_ARCH_VERSATILE
+#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
 #define CLCD_IENB               0x00000018
 #define CLCD_CNTL               0x0000001c
 #else
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 5c4ae8f5dbb0..2e6799632f12 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -26,7 +26,6 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
 /*
 * ISA I/O bus memory addresses are 1:1 with the physical address.
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
index f97912fbb10f..59975ee43cf1 100644
--- a/include/asm-arm/irq.h
+++ b/include/asm-arm/irq.h
@@ -47,5 +47,6 @@ struct irqaction;
 struct pt_regs;
 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
+extern void migrate_irqs(void);
 #endif
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index 4fa95084a8c0..eb262e078c46 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -48,10 +48,11 @@ struct machine_desc {
 * Set of macros to define architecture features.  This is built into
 * a table by the linker.
 */
-#define MACHINE_START(_type,_name)              \
+#define MACHINE_START(_type,_name)                      \
-const struct machine_desc __mach_desc_##_type   \
+static const struct machine_desc __mach_desc_##_type    \
+ __attribute_used__                                     \
 __attribute__((__section__(".arch.info.init"))) = {    \
-        .nr             = MACH_TYPE_##_type,    \
+        .nr             = MACH_TYPE_##_type,            \
        .name           = _name,
 #define MACHINE_END                             \
diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h
index a92887d4b2cb..cd57436d9874 100644
--- a/include/asm-arm/mach/flash.h
+++ b/include/asm-arm/mach/flash.h
@@ -14,6 +14,7 @@ struct mtd_partition;
 /*
 * map_name:    the map probe function name
+ * name:        flash device name (eg, as used with mtdparts=)
 * width:       width of mapped device
 * init:        method called at driver/device initialisation
 * exit:        method called at driver/device removal
@@ -23,6 +24,7 @@ struct mtd_partition;
 */
 struct flash_platform_data {
        const char      *map_name;
+        const char      *name;
        unsigned int    width;
        int             (*init)(void);
        void            (*exit)(void);
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index 9ac47cf8d2e4..b338936bde4f 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -11,7 +11,7 @@
 */
 struct map_desc {
        unsigned long virtual;
-        unsigned long physical;
+        unsigned long pfn;
        unsigned long length;
        unsigned int type;
 };
@@ -27,6 +27,9 @@ struct meminfo;
 #define MT_ROM                  6
 #define MT_IXP2000_DEVICE       7
+#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
+#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
 extern void create_memmap_holes(struct meminfo *);
 extern void memtable_init(struct meminfo *);
 extern void iotable_init(struct map_desc *, int);
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index a8a933a775db..a547ee598c6c 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -12,6 +12,16 @@
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
+/*
+ * Allow for constants defined here to be used from assembly code
+ * by prepending the UL suffix only with actual C code compilation.
+ */
+#ifndef __ASSEMBLY__
+#define UL(x) (x##UL)
+#else
+#define UL(x) (x)
+#endif
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <asm/arch/memory.h>
@@ -21,20 +31,20 @@
 * TASK_SIZE - the maximum size of a user space task.
 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
 */
-#define TASK_SIZE               (0xbf000000UL)
+#define TASK_SIZE               UL(0xbf000000)
-#define TASK_UNMAPPED_BASE      (0x40000000UL)
+#define TASK_UNMAPPED_BASE      UL(0x40000000)
 #endif
 /*
 * The maximum size of a 26-bit user space task.
 */
-#define TASK_SIZE_26            (0x04000000UL)
+#define TASK_SIZE_26            UL(0x04000000)
 /*
 * Page offset: 3GB
 */
 #ifndef PAGE_OFFSET
-#define PAGE_OFFSET             (0xc0000000UL)
+#define PAGE_OFFSET             UL(0xc0000000)
 #endif
 /*
@@ -58,6 +68,13 @@
 #error Top of user space clashes with start of module space
 #endif
+/*
+ * The XIP kernel gets mapped at the bottom of the module vm area.
+ * Since we use sections to map it, this macro replaces the physical address
+ * with its virtual address while keeping offset from the base section.
+ */
+#define XIP_VIRT_ADDR(physaddr)  (MODULE_START + ((physaddr) & 0x000fffff))
 #ifndef __ASSEMBLY__
 /*
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 4af9c411c617..57b8def83d41 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -86,7 +86,8 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
                cpu_set(cpu, next->cpu_vm_mask);
                check_context(next);
                cpu_switch_mm(next->pgd, next);
-                cpu_clear(cpu, prev->cpu_vm_mask);
+                if (cache_is_vivt())
+                        cpu_clear(cpu, prev->cpu_vm_mask);
        }
 }
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 366bafbdfbb1..5a0d19b466b0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -397,9 +397,6 @@ static inline pte_t *pmd_page_kernel(pmd_t pmd)
 #define pgd_clear(pgdp)         do { } while (0)
 #define set_pgd(pgd,pgdp)       do { } while (0)
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)          mk_pte(page, __pgprot(0))
 /* to find an entry in a page-table-directory */
 #define pgd_index(addr)         ((addr) >> PGDIR_SHIFT)
diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h
index 60f33e6eb800..71ca7d412687 100644
--- a/include/asm-arm/semaphore.h
+++ b/include/asm-arm/semaphore.h
@@ -24,8 +24,6 @@ struct semaphore {
        .wait   = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
-#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INIT(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INIT(name,count)
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index dbb4d859c586..551cd3c3093c 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -66,4 +66,14 @@ struct secondary_data {
 };
 extern struct secondary_data secondary_data;
+extern int __cpu_disable(void);
+extern int mach_cpu_disable(unsigned int cpu);
+extern void __cpu_die(unsigned int cpu);
+extern void cpu_die(void);
+extern void platform_cpu_die(unsigned int cpu);
+extern int platform_cpu_kill(unsigned int cpu);
+extern void platform_cpu_enable(unsigned int cpu);
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index cb4906b45555..6ed4f916b166 100644
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -80,7 +80,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 */
 #define rwlock_is_locked(x)     (*((volatile unsigned int *)(x)) != 0)
-static inline void __raw_write_lock(rwlock_t *rw)
+static inline void __raw_write_lock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
@@ -97,7 +97,7 @@ static inline void __raw_write_lock(rwlock_t *rw)
        smp_mb();
 }
-static inline int __raw_write_trylock(rwlock_t *rw)
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
@@ -157,7 +157,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
        smp_mb();
 }
-static inline void __raw_read_unlock(rwlock_t *rw)
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
 {
        unsigned long tmp, tmp2;
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
index 9bb325c54645..f49bfb78c221 100644
--- a/include/asm-arm/tlb.h
+++ b/include/asm-arm/tlb.h
@@ -27,11 +27,7 @@
 */
 struct mmu_gather {
        struct mm_struct        *mm;
-        unsigned int            freed;
        unsigned int            fullmm;
-        unsigned int            flushes;
-        unsigned int            avoided_flushes;
 };
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -39,11 +35,9 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        int cpu = smp_processor_id();
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-        struct mmu_gather *tlb = &per_cpu(mmu_gathers, cpu);
        tlb->mm = mm;
-        tlb->freed = 0;
        tlb->fullmm = full_mm_flush;
        return tlb;
@@ -52,24 +46,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        struct mm_struct *mm = tlb->mm;
-        unsigned long freed = tlb->freed;
-        int rss = get_mm_counter(mm, rss);
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
        if (tlb->fullmm)
-                flush_tlb_mm(mm);
+                flush_tlb_mm(tlb->mm);
        /* keep the page table cache within bounds */
        check_pgt_cache();
-}
-static inline unsigned int tlb_is_full_mm(struct mmu_gather *tlb)
+        put_cpu_var(mmu_gathers);
-{
-        return tlb->fullmm;
 }
 #define tlb_remove_tlb_entry(tlb,ptep,address)  do { } while (0)
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index c49df635a80f..d626e70faded 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -544,7 +544,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
 asmlinkage int sys_fork(struct pt_regs *regs);
 asmlinkage int sys_vfork(struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,