161 files changed, 3835 insertions, 705 deletions
diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
index 0e9b7e18af05..002227924b9f 100644
--- a/include/asm-arm/arch-aaec2000/aaec2000.h
+++ b/include/asm-arm/arch-aaec2000/aaec2000.h
@@ -17,6 +17,16 @@
 #error You must include hardware.h not this file
 #endif /* __ASM_ARCH_HARDWARE_H */
+/* Chip selects */
+#define AAEC_CS0        0x00000000
+#define AAEC_CS1        0x10000000
+#define AAEC_CS2        0x20000000
+#define AAEC_CS3        0x30000000
+/* Flash */
+#define AAEC_FLASH_BASE AAEC_CS0
+#define AAEC_FLASH_SIZE SZ_64M
 /* Interrupt controller */
 #define IRQ_BASE        __REG(0x80000500)
 #define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
@@ -148,4 +158,50 @@
 #define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
 #define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
+/* GPIO Registers */
+#define AAEC_GPIO_PHYS  0x80000e00
+#define AAEC_GPIO_PADR          __REG(AAEC_GPIO_PHYS + 0x00)
+#define AAEC_GPIO_PBDR          __REG(AAEC_GPIO_PHYS + 0x04)
+#define AAEC_GPIO_PCDR          __REG(AAEC_GPIO_PHYS + 0x08)
+#define AAEC_GPIO_PDDR          __REG(AAEC_GPIO_PHYS + 0x0c)
+#define AAEC_GPIO_PADDR         __REG(AAEC_GPIO_PHYS + 0x10)
+#define AAEC_GPIO_PBDDR         __REG(AAEC_GPIO_PHYS + 0x14)
+#define AAEC_GPIO_PCDDR         __REG(AAEC_GPIO_PHYS + 0x18)
+#define AAEC_GPIO_PDDDR         __REG(AAEC_GPIO_PHYS + 0x1c)
+#define AAEC_GPIO_PEDR          __REG(AAEC_GPIO_PHYS + 0x20)
+#define AAEC_GPIO_PEDDR         __REG(AAEC_GPIO_PHYS + 0x24)
+#define AAEC_GPIO_KSCAN         __REG(AAEC_GPIO_PHYS + 0x28)
+#define AAEC_GPIO_PINMUX        __REG(AAEC_GPIO_PHYS + 0x2c)
+#define AAEC_GPIO_PFDR          __REG(AAEC_GPIO_PHYS + 0x30)
+#define AAEC_GPIO_PFDDR         __REG(AAEC_GPIO_PHYS + 0x34)
+#define AAEC_GPIO_PGDR          __REG(AAEC_GPIO_PHYS + 0x38)
+#define AAEC_GPIO_PGDDR         __REG(AAEC_GPIO_PHYS + 0x3c)
+#define AAEC_GPIO_PHDR          __REG(AAEC_GPIO_PHYS + 0x40)
+#define AAEC_GPIO_PHDDR         __REG(AAEC_GPIO_PHYS + 0x44)
+#define AAEC_GPIO_RAZ           __REG(AAEC_GPIO_PHYS + 0x48)
+#define AAEC_GPIO_INTTYPE1      __REG(AAEC_GPIO_PHYS + 0x4c)
+#define AAEC_GPIO_INTTYPE2      __REG(AAEC_GPIO_PHYS + 0x50)
+#define AAEC_GPIO_FEOI          __REG(AAEC_GPIO_PHYS + 0x54)
+#define AAEC_GPIO_INTEN         __REG(AAEC_GPIO_PHYS + 0x58)
+#define AAEC_GPIO_INTSTATUS     __REG(AAEC_GPIO_PHYS + 0x5c)
+#define AAEC_GPIO_RAWINTSTATUS  __REG(AAEC_GPIO_PHYS + 0x60)
+#define AAEC_GPIO_DB            __REG(AAEC_GPIO_PHYS + 0x64)
+#define AAEC_GPIO_PAPINDR       __REG(AAEC_GPIO_PHYS + 0x68)
+#define AAEC_GPIO_PBPINDR       __REG(AAEC_GPIO_PHYS + 0x6c)
+#define AAEC_GPIO_PCPINDR       __REG(AAEC_GPIO_PHYS + 0x70)
+#define AAEC_GPIO_PDPINDR       __REG(AAEC_GPIO_PHYS + 0x74)
+#define AAEC_GPIO_PEPINDR       __REG(AAEC_GPIO_PHYS + 0x78)
+#define AAEC_GPIO_PFPINDR       __REG(AAEC_GPIO_PHYS + 0x7c)
+#define AAEC_GPIO_PGPINDR       __REG(AAEC_GPIO_PHYS + 0x80)
+#define AAEC_GPIO_PHPINDR       __REG(AAEC_GPIO_PHYS + 0x84)
+#define AAEC_GPIO_PINMUX_PE0CON         (1 << 0)
+#define AAEC_GPIO_PINMUX_PD0CON         (1 << 1)
+#define AAEC_GPIO_PINMUX_CODECON        (1 << 2)
+#define AAEC_GPIO_PINMUX_UART3CON       (1 << 3)
+/* LCD Controller */
+#define AAEC_CLCD_PHYS  0x80003000
 #endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/include/asm-arm/arch-aaec2000/aaed2000.h b/include/asm-arm/arch-aaec2000/aaed2000.h
new file mode 100644
index 000000000000..bc76d2badb91
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/aaed2000.h
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/aaed2000.h
+ *
+ *  AAED-2000 specific bits definition
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_AAED2000_H
+#define __ASM_ARCH_AAED2000_H
+/* External GPIOs. */
+#define EXT_GPIO_PBASE  AAEC_CS3
+#define EXT_GPIO_VBASE  0xf8100000
+#define EXT_GPIO_LENGTH 0x00001000
+#define __ext_gpio_p2v(x)       ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
+#define __ext_gpio_v2p(x)       ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
+#define __EXT_GPIO_REG(x)       (*((volatile u32 *)__ext_gpio_p2v(x)))
+#define __EXT_GPIO_PREG(x)      (__ext_gpio_v2p((u32)&(x)))
+#define AAED_EXT_GPIO   __EXT_GPIO_REG(EXT_GPIO_PBASE)
+#define AAED_EGPIO_KBD_SCAN     0x00003fff /* Keyboard scan data */
+#define AAED_EGPIO_PWR_INT      0x00008fff /* Smart battery charger interrupt */
+#define AAED_EGPIO_SWITCHED     0x000f0000 /* DIP Switches */
+#define AAED_EGPIO_USB_VBUS     0x00400000 /* USB Vbus sense */
+#define AAED_EGPIO_LCD_PWR_EN   0x02000000 /* LCD and backlight PWR enable */
+#define AAED_EGPIO_nLED0        0x20000000 /* LED 0 */
+#define AAED_EGPIO_nLED1        0x20000000 /* LED 1 */
+#define AAED_EGPIO_nLED2        0x20000000 /* LED 2 */
+#endif /* __ARM_ARCH_AAED2000_H */
diff --git a/include/asm-arm/arch-aaec2000/hardware.h b/include/asm-arm/arch-aaec2000/hardware.h
index 4c37219e030e..153506fd06ed 100644
--- a/include/asm-arm/arch-aaec2000/hardware.h
+++ b/include/asm-arm/arch-aaec2000/hardware.h
@@ -11,7 +11,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
-#include <linux/config.h>
+#include <asm/sizes.h>
+#include <asm/arch/aaec2000.h>
 /* The kernel is loaded at physical address 0xf8000000.
 * We map the IO space a bit after
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
index c58a8d10425a..8d67907fd4f0 100644
--- a/include/asm-arm/arch-aaec2000/io.h
+++ b/include/asm-arm/arch-aaec2000/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 79c90813bc3e..d8209f8911d6 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -13,7 +13,7 @@
 #include <linux/config.h>
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
diff --git a/include/asm-arm/arch-cl7500/io.h b/include/asm-arm/arch-cl7500/io.h
index f0113bc75630..89a33287f4fe 100644
--- a/include/asm-arm/arch-cl7500/io.h
+++ b/include/asm-arm/arch-cl7500/io.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-cl7500/memory.h b/include/asm-arm/arch-cl7500/memory.h
index 9776bba8e585..34f40a6cec30 100644
--- a/include/asm-arm/arch-cl7500/memory.h
+++ b/include/asm-arm/arch-cl7500/memory.h
@@ -17,7 +17,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 /*
 * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
index 14d7e8da5453..62613b0e2d96 100644
--- a/include/asm-arm/arch-clps711x/io.h
+++ b/include/asm-arm/arch-clps711x/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 #define __io(a)                 ((void __iomem *)(a))
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index bd978947db42..61d8717406ce 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -25,7 +25,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h
index 7d0ab791b16c..9fc4bcfa1681 100644
--- a/include/asm-arm/arch-clps711x/uncompress.h
+++ b/include/asm-arm/arch-clps711x/uncompress.h
@@ -19,7 +19,7 @@
 */
 #include <linux/config.h>
 #include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #include <asm/hardware/clps7111.h>
 #undef CLPS7111_BASE
diff --git a/include/asm-arm/arch-ebsa110/io.h b/include/asm-arm/arch-ebsa110/io.h
index 68e04c0bb3f7..ae048441c9ed 100644
--- a/include/asm-arm/arch-ebsa110/io.h
+++ b/include/asm-arm/arch-ebsa110/io.h
@@ -64,7 +64,7 @@ void __writel(u32 val, void __iomem *addr);
 #define writew(v,b)             __writew(v,b)
 #define writel(v,b)             __writel(v,b)
-#define __arch_ioremap(cookie,sz,c,a)   ((void __iomem *)(cookie))
+#define __arch_ioremap(cookie,sz,c)     ((void __iomem *)(cookie))
 #define __arch_iounmap(cookie)          do { } while (0)
 extern void insb(unsigned int port, void *buf, int sz);
diff --git a/include/asm-arm/arch-ebsa110/memory.h b/include/asm-arm/arch-ebsa110/memory.h
index 5a9493e12275..02f144520c10 100644
--- a/include/asm-arm/arch-ebsa110/memory.h
+++ b/include/asm-arm/arch-ebsa110/memory.h
@@ -19,7 +19,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * We keep this 1:1 so that we don't interfere
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
index 70576b17f922..776f9d377057 100644
--- a/include/asm-arm/arch-ebsa285/io.h
+++ b/include/asm-arm/arch-ebsa285/io.h
@@ -14,6 +14,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffff
 /*
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index d0466f9987d3..09e335cd687d 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -46,14 +46,14 @@ extern unsigned long __bus_to_virt(unsigned long);
 #if defined(CONFIG_ARCH_FOOTBRIDGE)
 /* Task size and page offset at 3GB */
-#define TASK_SIZE               (0xbf000000UL)
+#define TASK_SIZE               UL(0xbf000000)
-#define PAGE_OFFSET             (0xc0000000UL)
+#define PAGE_OFFSET             UL(0xc0000000)
 #elif defined(CONFIG_ARCH_CO285)
 /* Task size and page offset at 1.5GB */
-#define TASK_SIZE               (0x5f000000UL)
+#define TASK_SIZE               UL(0x5f000000)
-#define PAGE_OFFSET             (0x60000000UL)
+#define PAGE_OFFSET             UL(0x60000000)
 #else
@@ -64,7 +64,7 @@ extern unsigned long __bus_to_virt(unsigned long);
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET             (0x00000000UL)
+#define PHYS_OFFSET             UL(0x00000000)
 /*
 * This decides where the kernel will search for a free chunk of vm
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
index 1f0afa257621..9fe100c9d6be 100644
--- a/include/asm-arm/arch-epxa10db/io.h
+++ b/include/asm-arm/arch-epxa10db/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffff
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h
index 3f86bf7f67f0..999541b6a9f5 100644
--- a/include/asm-arm/arch-epxa10db/memory.h
+++ b/include/asm-arm/arch-epxa10db/memory.h
@@ -23,7 +23,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h
index d33ad6a93749..fdfe0e6848f8 100644
--- a/include/asm-arm/arch-epxa10db/uncompress.h
+++ b/include/asm-arm/arch-epxa10db/uncompress.h
@@ -19,7 +19,7 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include "asm/arch/platform.h"
-#include "asm/arch/hardware.h"
+#include "asm/hardware.h"
 #define UART00_TYPE (volatile unsigned int*)
 #include "asm/arch/uart00.h"
diff --git a/include/asm-arm/arch-h720x/io.h b/include/asm-arm/arch-h720x/io.h
index 68814828c9a7..d3ccfd8172b7 100644
--- a/include/asm-arm/arch-h720x/io.h
+++ b/include/asm-arm/arch-h720x/io.h
@@ -14,7 +14,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
diff --git a/include/asm-arm/arch-h720x/memory.h b/include/asm-arm/arch-h720x/memory.h
index 5633447af268..4a1bfd78a0fe 100644
--- a/include/asm-arm/arch-h720x/memory.h
+++ b/include/asm-arm/arch-h720x/memory.h
@@ -11,7 +11,7 @@
 * Page offset:
 *    ( 0xc0000000UL )
 */
-#define PHYS_OFFSET     (0x40000000UL)
+#define PHYS_OFFSET     UL(0x40000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-h720x/system.h b/include/asm-arm/arch-h720x/system.h
index 0b025e227ec2..09eda84592ff 100644
--- a/include/asm-arm/arch-h720x/system.h
+++ b/include/asm-arm/arch-h720x/system.h
@@ -17,9 +17,11 @@
 static void arch_idle(void)
 {
        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
-        __asm__ __volatile__(
+        nop();
-        "mov    r0, r0\n\t"
+        nop();
-        "mov    r0, r0");
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
+        nop();
+        nop();
 }
diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h
index 2fffacf85a01..9535764bcc71 100644
--- a/include/asm-arm/arch-h720x/uncompress.h
+++ b/include/asm-arm/arch-h720x/uncompress.h
@@ -7,7 +7,7 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define LSR     0x14
 #define TEMPTY  0x40
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index 93b840e8fa60..a6912b3d8671 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -76,6 +76,7 @@
 #define GPIO_PIN_MASK 0x1f
 #define GPIO_PORT_MASK (0x3 << 5)
+#define GPIO_PORT_SHIFT 5
 #define GPIO_PORTA (0<<5)
 #define GPIO_PORTB (1<<5)
 #define GPIO_PORTC (2<<5)
@@ -88,24 +89,37 @@
 #define GPIO_PF    (0<<9)
 #define GPIO_AF    (1<<9)
+#define GPIO_OCR_SHIFT 10
 #define GPIO_OCR_MASK (3<<10)
 #define GPIO_AIN   (0<<10)
 #define GPIO_BIN   (1<<10)
 #define GPIO_CIN   (2<<10)
-#define GPIO_GPIO  (3<<10)
+#define GPIO_DR    (3<<10)
-#define GPIO_AOUT  (1<<12)
+#define GPIO_AOUT_SHIFT 12
-#define GPIO_BOUT  (1<<13)
+#define GPIO_AOUT_MASK (3<<12)
+#define GPIO_AOUT     (0<<12)
+#define GPIO_AOUT_ISR (1<<12)
+#define GPIO_AOUT_0   (2<<12)
+#define GPIO_AOUT_1   (3<<12)
+#define GPIO_BOUT_SHIFT 14
+#define GPIO_BOUT_MASK (3<<14)
+#define GPIO_BOUT      (0<<14)
+#define GPIO_BOUT_ISR  (1<<14)
+#define GPIO_BOUT_0    (2<<14)
+#define GPIO_BOUT_1    (3<<14)
+#define GPIO_GIUS      (1<<16)
 /* assignements for GPIO alternate/primary functions */
 /* FIXME: This list is not completed. The correct directions are
 * missing on some (many) pins
 */
-#define PA0_PF_A24           ( GPIO_PORTA | GPIO_PF | 0 )
+#define PA0_AIN_SPI2_CLK     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
-#define PA0_AIN_SPI2_CLK     ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
 #define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD    ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
 #define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
 #define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
 #define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
@@ -123,7 +137,7 @@
 #define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
 #define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
 #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS     ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA17_AIN_SPI2_SS     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
 #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
 #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
 #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
@@ -191,19 +205,27 @@
 #define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
 #define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
 #define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
+#define PC24_BIN_UART3_RI    ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
+#define PC25_BIN_UART3_DSR   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
+#define PC26_AOUT_UART3_DTR  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
+#define PC27_BIN_UART3_DCD   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
+#define PC28_BIN_UART3_CTS   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
+#define PC29_AOUT_UART3_RTS  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
+#define PC30_BIN_UART3_TX    ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
+#define PC31_AOUT_UART3_RX   ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
 #define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
 #define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR     ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AF_UART2_DTR     ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK    ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD7_AIN_SPI2_SCLK    ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
 #define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
 #define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS      ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD8_AIN_SPI2_SS      ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
 #define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
 #define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD    ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD9_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
 #define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
 #define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD    ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD10_AIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
 #define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
 #define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
 #define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
@@ -225,7 +247,7 @@
 #define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
 #define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
 #define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD    ( GPIO_PORTD | GPIO_BIN | 31 )
+#define PD31_BIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
 /*
 * PWM controller
diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h
index 28a4cca6a4cb..b191cdd05576 100644
--- a/include/asm-arm/arch-imx/io.h
+++ b/include/asm-arm/arch-imx/io.h
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 #define __io(a)         ((void __iomem *)(a))
diff --git a/include/asm-arm/arch-imx/irqs.h b/include/asm-arm/arch-imx/irqs.h
index 238197cfb9d9..f195542898e0 100644
--- a/include/asm-arm/arch-imx/irqs.h
+++ b/include/asm-arm/arch-imx/irqs.h
@@ -23,7 +23,7 @@
 #define __ARM_IRQS_H__
 /* Use the imx definitions */
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 /*
 *  IMX Interrupt numbers
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h
index 116a91fa14f1..d09ae32cd2f4 100644
--- a/include/asm-arm/arch-imx/memory.h
+++ b/include/asm-arm/arch-imx/memory.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_MMU_H
 #define __ASM_ARCH_MMU_H
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h
index d65ab3cd5d5d..8c91674706b1 100644
--- a/include/asm-arm/arch-imx/timex.h
+++ b/include/asm-arm/arch-imx/timex.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define CLOCK_TICK_RATE         (CLK32)
 #endif
diff --git a/include/asm-arm/arch-integrator/hardware.h b/include/asm-arm/arch-integrator/hardware.h
index be2716eeaa02..6f0947bc500d 100644
--- a/include/asm-arm/arch-integrator/hardware.h
+++ b/include/asm-arm/arch-integrator/hardware.h
@@ -33,15 +33,6 @@
 #define IO_SIZE                 0x0B000000                 // How much?
 #define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
-/*
- * Similar to above, but for PCI addresses (memory, IO, Config and the
- * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
 #define PCIO_BASE               PCI_IO_VADDR
 #define PCIMEM_BASE             PCI_MEMORY_VADDR
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
index fbea8be67d26..31f2deab51b0 100644
--- a/include/asm-arm/arch-integrator/io.h
+++ b/include/asm-arm/arch-integrator/io.h
@@ -22,6 +22,14 @@
 #define IO_SPACE_LIMIT 0xffff
+/*
+ * WARNING: this has to mirror definitions in platform.h
+ */
+#define PCI_MEMORY_VADDR        0xe8000000
+#define PCI_CONFIG_VADDR        0xec000000
+#define PCI_V3_VADDR            0xed000000
+#define PCI_IO_VADDR            0xee000000
 #define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            ((a) + PCI_MEMORY_VADDR)
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h
index 2087ea7d28a9..1ab56d783e7c 100644
--- a/include/asm-arm/arch-integrator/memory.h
+++ b/include/asm-arm/arch-integrator/memory.h
@@ -23,8 +23,8 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
-#define BUS_OFFSET      (0x80000000UL)
+#define BUS_OFFSET      UL(0x80000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
index 0ec7093f7c37..da6981efdc39 100644
--- a/include/asm-arm/arch-integrator/smp.h
+++ b/include/asm-arm/arch-integrator/smp.h
@@ -3,7 +3,7 @@
 #include <linux/config.h>
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #include <asm/io.h>
 #define hard_smp_processor_id()                         \
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h
index 2761dfd8694d..f39046a6ab14 100644
--- a/include/asm-arm/arch-iop3xx/io.h
+++ b/include/asm-arm/arch-iop3xx/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 #define __io(p)                 ((void __iomem *)(p))
diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h
index 200621ff3690..f8df778a356f 100644
--- a/include/asm-arm/arch-iop3xx/iop321.h
+++ b/include/asm-arm/arch-iop3xx/iop321.h
@@ -40,7 +40,7 @@
 #define IOP321_PCI_UPPER_IO_BA      (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
 #define IOP321_PCI_IO_OFFSET        (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
-//#define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1)
+/* #define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1) */
 #define IOP321_PCI_MEM_WINDOW_SIZE  0x04000000 /* 64M outbound window */
 #define IOP321_PCI_LOWER_MEM_PA     0x80000000
 #define IOP321_PCI_LOWER_MEM_BA     (*IOP321_OMWTVR0)
diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h
index 96adffd8bad2..fbf0cc11bdd9 100644
--- a/include/asm-arm/arch-iop3xx/iop331.h
+++ b/include/asm-arm/arch-iop3xx/iop331.h
@@ -42,7 +42,7 @@
 /* this can be 128M if OMWTVR1 is set */
 #define IOP331_PCI_MEM_WINDOW_SIZE      0x04000000 /* 64M outbound window */
-//#define IOP331_PCI_MEM_WINDOW_SIZE  (~*IOP331_IALR1 + 1)
+/* #define IOP331_PCI_MEM_WINDOW_SIZE  (~*IOP331_IALR1 + 1) */
 #define IOP331_PCI_LOWER_MEM_PA     0x80000000
 #define IOP331_PCI_LOWER_MEM_BA     (*IOP331_OMWTVR0)
 #define IOP331_PCI_UPPER_MEM_PA     (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
index 45351f5cd904..bc62f4b13235 100644
--- a/include/asm-arm/arch-iop3xx/memory.h
+++ b/include/asm-arm/arch-iop3xx/memory.h
@@ -12,9 +12,9 @@
 * Physical DRAM offset.
 */
 #ifndef CONFIG_ARCH_IOP331
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 #else
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 #endif
 /*
diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h
index d4187fe9a85a..472badb451c4 100644
--- a/include/asm-arm/arch-iop3xx/timex.h
+++ b/include/asm-arm/arch-iop3xx/timex.h
@@ -4,7 +4,7 @@
 * IOP3xx architecture timex specifications
 */
 #include <linux/config.h>
+#include <asm/hardware.h>
 #if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
index 31ae88674968..95128d9f5026 100644
--- a/include/asm-arm/arch-ixp2000/enp2611.h
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -21,8 +21,20 @@
 #ifndef __ENP2611_H
 #define __ENP2611_H
-#define ENP2611_GPIO_SCL        0x07
+#define ENP2611_CALEB_PHYS_BASE         0xc5000000
-#define ENP2611_GPIO_SDA        0x06
+#define ENP2611_CALEB_VIRT_BASE         0xfe000000
+#define ENP2611_CALEB_SIZE              0x00100000
+#define ENP2611_PM3386_0_PHYS_BASE      0xc6000000
+#define ENP2611_PM3386_0_VIRT_BASE      0xfe100000
+#define ENP2611_PM3386_0_SIZE           0x00100000
+#define ENP2611_PM3386_1_PHYS_BASE      0xc6400000
+#define ENP2611_PM3386_1_VIRT_BASE      0xfe200000
+#define ENP2611_PM3386_1_SIZE           0x00100000
+#define ENP2611_GPIO_SCL                7
+#define ENP2611_GPIO_SDA                6
 #endif
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 3241cd6f0778..7fbcdf9931ee 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT          0xffffffff
 #define __mem_pci(a)            (a)
diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h
index 0deb96c12adb..62f09c7ff420 100644
--- a/include/asm-arm/arch-ixp2000/irqs.h
+++ b/include/asm-arm/arch-ixp2000/irqs.h
@@ -67,12 +67,45 @@
 #define IRQ_IXP2000_PCIA                40
 #define IRQ_IXP2000_PCIB                41
-#define NR_IXP2000_IRQS                 42
+/* Int sources from IRQ_ERROR_STATUS */
+#define IRQ_IXP2000_DRAM0_MIN_ERR       42
+#define IRQ_IXP2000_DRAM0_MAJ_ERR       43
+#define IRQ_IXP2000_DRAM1_MIN_ERR       44
+#define IRQ_IXP2000_DRAM1_MAJ_ERR       45
+#define IRQ_IXP2000_DRAM2_MIN_ERR       46
+#define IRQ_IXP2000_DRAM2_MAJ_ERR       47
+/* 48-57 reserved */
+#define IRQ_IXP2000_SRAM0_ERR           58
+#define IRQ_IXP2000_SRAM1_ERR           59
+#define IRQ_IXP2000_SRAM2_ERR           60
+#define IRQ_IXP2000_SRAM3_ERR           61
+/* 62-65 reserved */
+#define IRQ_IXP2000_MEDIA_ERR           66
+#define IRQ_IXP2000_PCI_ERR                     67
+#define IRQ_IXP2000_SP_INT                      68
+#define NR_IXP2000_IRQS                         69
 #define IXP2000_BOARD_IRQ(x)            (NR_IXP2000_IRQS + (x))
 #define IXP2000_BOARD_IRQ_MASK(irq)     (1 << (irq - NR_IXP2000_IRQS))  
+#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
+#define IXP2000_VALID_ERR_IRQ_MASK (\
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT)        )
 /*
 * This allows for all the on-chip sources plus up to 32 CPLD based
 * IRQs. Should be more than enough.
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b768009c3a51..c6d51426e98f 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -22,7 +22,7 @@
 #define IXDP2X01_CPLD_REGION_SIZE       0x00100000
 #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
-#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
 #define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
 #define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 32aece069869..fc5ac6aec4f2 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -59,14 +59,15 @@
 #define IXP2000_CAP_SIZE                0x00100000
 /*
- * Addresses for specific on-chip peripherals
+ * Addresses for specific on-chip peripherals.
 */
 #define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
 #define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
 #define IXP2000_UART_PHYS_BASE          0xc0030000
 #define IXP2000_UART_VIRT_BASE          0xfef30000
 #define IXP2000_TIMER_VIRT_BASE         0xfef20000
-#define IXP2000_GPIO_VIRT_BASE          0Xfef10000
+#define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
+#define IXP2000_GPIO_VIRT_BASE          0xfef10000
 /*
 * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
@@ -252,7 +253,7 @@
 #define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
 #define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
-#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Centrolfunction bit */
+#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
 #define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
 /* These are from the IRQ register in the PCI ISR register */
@@ -392,4 +393,47 @@
 #define WDT_RESET_ENABLE                0x01000000
+/*
+ * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
+ * units, but the registers that differ between the two don't overlap,
+ * so we can have one register list for both.
+ */
+#define IXP2000_MSF_REG(x)                      ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
+#define IXP2000_MSF_RX_CONTROL                  IXP2000_MSF_REG(0x0000)
+#define IXP2000_MSF_TX_CONTROL                  IXP2000_MSF_REG(0x0004)
+#define IXP2000_MSF_INTERRUPT_STATUS            IXP2000_MSF_REG(0x0008)
+#define IXP2000_MSF_INTERRUPT_ENABLE            IXP2000_MSF_REG(0x000c)
+#define IXP2000_MSF_CSIX_TYPE_MAP               IXP2000_MSF_REG(0x0010)
+#define IXP2000_MSF_FC_EGRESS_STATUS            IXP2000_MSF_REG(0x0014)
+#define IXP2000_MSF_FC_INGRESS_STATUS           IXP2000_MSF_REG(0x0018)
+#define IXP2000_MSF_HWM_CONTROL                 IXP2000_MSF_REG(0x0024)
+#define IXP2000_MSF_FC_STATUS_OVERRIDE          IXP2000_MSF_REG(0x0028)
+#define IXP2000_MSF_CLOCK_CONTROL               IXP2000_MSF_REG(0x002c)
+#define IXP2000_MSF_RX_PORT_MAP                 IXP2000_MSF_REG(0x0040)
+#define IXP2000_MSF_RBUF_ELEMENT_DONE           IXP2000_MSF_REG(0x0044)
+#define IXP2000_MSF_RX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0        IXP2000_MSF_REG(0x0050)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1        IXP2000_MSF_REG(0x0054)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2        IXP2000_MSF_REG(0x0058)
+#define IXP2000_MSF_TX_SEQUENCE_0               IXP2000_MSF_REG(0x0060)
+#define IXP2000_MSF_TX_SEQUENCE_1               IXP2000_MSF_REG(0x0064)
+#define IXP2000_MSF_TX_SEQUENCE_2               IXP2000_MSF_REG(0x0068)
+#define IXP2000_MSF_TX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_TX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_RX_UP_CONTROL_0             IXP2000_MSF_REG(0x0080)
+#define IXP2000_MSF_RX_UP_CONTROL_1             IXP2000_MSF_REG(0x0084)
+#define IXP2000_MSF_RX_UP_CONTROL_2             IXP2000_MSF_REG(0x0088)
+#define IXP2000_MSF_RX_UP_CONTROL_3             IXP2000_MSF_REG(0x008c)
+#define IXP2000_MSF_TX_UP_CONTROL_0             IXP2000_MSF_REG(0x0090)
+#define IXP2000_MSF_TX_UP_CONTROL_1             IXP2000_MSF_REG(0x0094)
+#define IXP2000_MSF_TX_UP_CONTROL_2             IXP2000_MSF_REG(0x0098)
+#define IXP2000_MSF_TX_UP_CONTROL_3             IXP2000_MSF_REG(0x009c)
+#define IXP2000_MSF_TRAIN_DATA                  IXP2000_MSF_REG(0x00a0)
+#define IXP2000_MSF_TRAIN_CALENDAR              IXP2000_MSF_REG(0x00a4)
+#define IXP2000_MSF_TRAIN_FLOW_CONTROL          IXP2000_MSF_REG(0x00a8)
+#define IXP2000_MSF_TX_CALENDAR_0               IXP2000_MSF_REG(0x1000)
+#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS     IXP2000_MSF_REG(0x1400)
 #endif                          /* _IXP2000_H_ */
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h
index d0f415c6dae9..21e1de51e3f6 100644
--- a/include/asm-arm/arch-ixp2000/memory.h
+++ b/include/asm-arm/arch-ixp2000/memory.h
@@ -13,7 +13,7 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index abdcf51bd283..a66317ab2071 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -15,40 +15,40 @@
 #ifndef __ASSEMBLY__
+static inline unsigned long ixp2000_reg_read(volatile void *reg)
+{
+        return *((volatile unsigned long *)reg);
+}
+static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
 /*
- * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
+ * On the IXP2400, we can't use XCB=000 due to chip bugs.  We use
- * to on-chip I/O register to not complete fully. What this means is
+ * XCB=101 instead, but that makes all I/O accesses bufferable.  This
- * that if you have a write to on-chip I/O followed by a back-to-back
+ * is not a problem in general, but we do have to be slightly more
- * read or write, the first write will happen twice. OR...if it's
+ * careful because I/O writes are no longer automatically flushed out
- * not a back-to-back transaction, the read or write will generate
+ * of the write buffer.
- * incorrect data.
- *
- * The official work around for this is to set the on-chip I/O regions
- * as XCB=101 and then force a read-back from the register.
 *
+ * In cases where we want to make sure that a write has been flushed
+ * out of the write buffer before we proceed, for example when masking
+ * a device interrupt before re-enabling IRQs in CPSR, we can use this
+ * function, ixp2000_reg_wrb, which performs a write, a readback, and
+ * issues a dummy instruction dependent on the value of the readback
+ * (mov rX, rX) to make sure that the readback has completed before we
+ * continue.
 */
-#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
+static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
-#include <asm/system.h>         /* Pickup local_irq_ functions */
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
 {
        unsigned long dummy;
-        unsigned long flags;
-        local_irq_save(flags);
        *((volatile unsigned long *)reg) = val;
-        barrier();
        dummy = *((volatile unsigned long *)reg);
-        local_irq_restore(flags);
+        __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
-}
-#else
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
 }
-#endif  /* IXDP2400 || IXDP2401 */
-#define ixp2000_reg_read(reg)   (*((volatile unsigned long *)reg))
 /*
 * Boards may multiplex different devices on the 2nd channel of 
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
index 4f489cc0dfa5..ddbbb34b5f95 100644
--- a/include/asm-arm/arch-ixp2000/system.h
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -26,29 +26,24 @@ static inline void arch_reset(char mode)
         * RedBoot bank.
         */
        if (machine_is_ixdp2401()) {
-                *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
+                ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
-                                                | IXDP2X01_CPLD_FLASH_INTERN);
+                                        ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
-                *IXDP2X01_CPLD_RESET_REG = 0xffffffff;
+                                                | IXDP2X01_CPLD_FLASH_INTERN));
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
        }
        /*
         * On IXDP2801 we need to write this magic sequence to the CPLD
         * to cause a complete reset of the CPU and all external devices
-         * and moves the flash bank register back to 0.
+         * and move the flash bank register back to 0.
         */
        if (machine_is_ixdp2801()) {
                unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
                reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
-                *IXDP2X01_CPLD_RESET_REG = reset_reg;
+                ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
-                mb();
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
-                *IXDP2X01_CPLD_RESET_REG = 0x80000000;
        }
-        /*
+        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
-         * We do a reset all if we are PCI master. We could be a slave and we
-         * don't want to do anything funky on the PCI bus.
-         */
-        if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
-                *(IXP2000_RESET0) |= (RSTALL);
-        }
 }
diff --git a/include/asm-arm/arch-ixp2000/uengine.h b/include/asm-arm/arch-ixp2000/uengine.h
new file mode 100644
index 000000000000..b442d65c6593
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/uengine.h
@@ -0,0 +1,62 @@
+/*
+ * Generic library functions for the microengines found on the Intel
+ * IXP2000 series of network processors.
+ *
+ * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Dedicated to Marija Kulikova.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2.1 of the
+ * License, or (at your option) any later version.
+ */
+#ifndef __IXP2000_UENGINE_H
+#define __IXP2000_UENGINE_H
+extern u32 ixp2000_uengine_mask;
+struct ixp2000_uengine_code
+{
+        u32     cpu_model_bitmask;
+        u8      cpu_min_revision;
+        u8      cpu_max_revision;
+        u32     uengine_parameters;
+        struct ixp2000_reg_value {
+                int     reg;
+                u32     value;
+        } *initial_reg_values;
+        int     num_insns;
+        u8      *insns;
+};
+u32 ixp2000_uengine_csr_read(int uengine, int offset);
+void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
+void ixp2000_uengine_reset(u32 uengine_mask);
+void ixp2000_uengine_set_mode(int uengine, u32 mode);
+void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
+void ixp2000_uengine_init_context(int uengine, int context, int pc);
+void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
+void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
+int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
+#define IXP2000_UENGINE_8_CONTEXTS              0x00000000
+#define IXP2000_UENGINE_4_CONTEXTS              0x80000000
+#define IXP2000_UENGINE_PRN_UPDATE_EVERY        0x40000000
+#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS    0x00000000
+#define IXP2000_UENGINE_NN_FROM_SELF            0x00100000
+#define IXP2000_UENGINE_NN_FROM_PREVIOUS        0x00000000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3       0x000c0000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2       0x00080000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1       0x00040000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0       0x00000000
+#define IXP2000_UENGINE_LM_ADDR1_GLOBAL         0x00020000
+#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT    0x00000000
+#define IXP2000_UENGINE_LM_ADDR0_GLOBAL         0x00010000
+#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT    0x00000000
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S
index 455da64832de..323b0bc4a39c 100644
--- a/include/asm-arm/arch-ixp4xx/entry-macro.S
+++ b/include/asm-arm/arch-ixp4xx/entry-macro.S
@@ -15,25 +15,26 @@
                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
                ldr     \irqstat, [\irqstat]            @ get interrupts
                cmp     \irqstat, #0
-                beq     1001f
+                beq     1001f                           @ upper IRQ?
                clz     \irqnr, \irqstat
                mov     \base, #31
-                subs    \irqnr, \base, \irqnr
+                sub     \irqnr, \base, \irqnr
+                b       1002f                           @ lower IRQ being
+                                                        @ handled
 1001:
                /*
                 * IXP465 has an upper IRQ status register
                 */
 #if defined(CONFIG_CPU_IXP46X)
-                bne     1002f
                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
                ldr     \irqstat, [\irqstat]            @ get upper interrupts
                mov     \irqnr, #63
                clz     \irqstat, \irqstat
                cmp     \irqstat, #32
                subne   \irqnr, \irqnr, \irqstat
-1002:
 #endif
+1002:
                .endm
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 4ac964b9078a..cfb413c845f7 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -27,7 +27,7 @@
 #define pcibios_assign_all_busses()     1
-#if defined(CONFIG_CPU_IXP465) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_CPU_IXP46X) && !defined(__ASSEMBLY__)
 extern unsigned int processor_id;
 #define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200)
 #else
@@ -44,5 +44,6 @@ extern unsigned int processor_id;
 #include "ixdp425.h"
 #include "coyote.h"
 #include "prpmc1100.h"
+#include "nslu2.h"
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index e350dcb544e8..942b622455bc 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -59,11 +59,10 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
 * fallback to the default.
 */
 static inline void __iomem *
-__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
+__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
 {
-        extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
        if((addr < 0x48000000) || (addr > 0x4fffffff))
-                return __ioremap(addr, size, flags, align);
+                return __ioremap(addr, size, flags);
        return (void *)addr;
 }
@@ -71,18 +70,16 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned
 static inline void
 __ixp4xx_iounmap(void __iomem *addr)
 {
-        extern void __iounmap(void __iomem *addr);
        if ((u32)addr >= VMALLOC_START)
                __iounmap(addr);
 }
-#define __arch_ioremap(a, s, f, x)      __ixp4xx_ioremap(a, s, f, x)
+#define __arch_ioremap(a, s, f)         __ixp4xx_ioremap(a, s, f)
 #define __arch_iounmap(a)               __ixp4xx_iounmap(a)
-#define writeb(p, v)                    __ixp4xx_writeb(p, v)
+#define writeb(v, p)                    __ixp4xx_writeb(v, p)
-#define writew(p, v)                    __ixp4xx_writew(p, v)
+#define writew(v, p)                    __ixp4xx_writew(v, p)
-#define writel(p, v)                    __ixp4xx_writel(p, v)
+#define writel(v, p)                    __ixp4xx_writel(v, p)
 #define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
 #define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
@@ -97,8 +94,9 @@ __ixp4xx_iounmap(void __iomem *addr)
 #define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
 static inline void 
-__ixp4xx_writeb(u8 value, u32 addr)
+__ixp4xx_writeb(u8 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START) {
@@ -113,15 +111,16 @@ __ixp4xx_writeb(u8 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
+__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
 {
        while (count--)
                writeb(*vaddr++, bus_addr);
 }
 static inline void 
-__ixp4xx_writew(u16 value, u32 addr)
+__ixp4xx_writew(u16 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START) {
@@ -136,15 +135,16 @@ __ixp4xx_writew(u16 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
+__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
 {
        while (count--)
                writew(*vaddr++, bus_addr);
 }
 static inline void 
-__ixp4xx_writel(u32 value, u32 addr)
+__ixp4xx_writel(u32 value, volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        if (addr >= VMALLOC_START) {
                __raw_writel(value, addr);
                return;
@@ -154,15 +154,16 @@ __ixp4xx_writel(u32 value, u32 addr)
 }
 static inline void
-__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
+__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
 {
        while (count--)
                writel(*vaddr++, bus_addr);
 }
 static inline unsigned char 
-__ixp4xx_readb(u32 addr)
+__ixp4xx_readb(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START)
@@ -177,15 +178,16 @@ __ixp4xx_readb(u32 addr)
 }
 static inline void
-__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
+__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readb(bus_addr);
 }
 static inline unsigned short 
-__ixp4xx_readw(u32 addr)
+__ixp4xx_readw(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 n, byte_enables, data;
        if (addr >= VMALLOC_START)
@@ -200,15 +202,16 @@ __ixp4xx_readw(u32 addr)
 }
 static inline void 
-__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
+__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readw(bus_addr);
 }
 static inline unsigned long 
-__ixp4xx_readl(u32 addr)
+__ixp4xx_readl(const volatile void __iomem *p)
 {
+        u32 addr = (u32)p;
        u32 data;
        if (addr >= VMALLOC_START)
@@ -221,7 +224,7 @@ __ixp4xx_readl(u32 addr)
 }
 static inline void 
-__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
+__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = readl(bus_addr);
@@ -239,7 +242,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
                                eth_copy_and_sum((s),__mem_pci(c),(l),(b))
 static inline int
-check_signature(unsigned long bus_addr, const unsigned char *signature,
+check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature,
                int length)
 {
        int retval = 0;
@@ -389,7 +392,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 static inline unsigned int
-__ixp4xx_ioread8(void __iomem *addr)
+__ixp4xx_ioread8(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -398,12 +401,12 @@ __ixp4xx_ioread8(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return (unsigned int)__raw_readb(port);
 #else
-                return (unsigned int)__ixp4xx_readb(port);
+                return (unsigned int)__ixp4xx_readb(addr);
 #endif
 }
 static inline void
-__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -412,12 +415,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsb(addr, vaddr, count);
 #else
-                __ixp4xx_readsb(port, vaddr, count);
+                __ixp4xx_readsb(addr, vaddr, count);
 #endif
 }
 static inline unsigned int
-__ixp4xx_ioread16(void __iomem *addr)
+__ixp4xx_ioread16(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -426,12 +429,12 @@ __ixp4xx_ioread16(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return le16_to_cpu(__raw_readw((u32)port));
 #else
-                return (unsigned int)__ixp4xx_readw((u32)port);
+                return (unsigned int)__ixp4xx_readw(addr);
 #endif
 }
 static inline void
-__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -440,12 +443,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsw(addr, vaddr, count);
 #else
-                __ixp4xx_readsw(port, vaddr, count);
+                __ixp4xx_readsw(addr, vaddr, count);
 #endif
 }
 static inline unsigned int
-__ixp4xx_ioread32(void __iomem *addr)
+__ixp4xx_ioread32(const void __iomem *addr)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -454,13 +457,13 @@ __ixp4xx_ioread32(void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                return le32_to_cpu(__raw_readl((u32)port));
 #else
-                return (unsigned int)__ixp4xx_readl((u32)port);
+                return (unsigned int)__ixp4xx_readl(addr);
 #endif
        }
 }
 static inline void
-__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
+__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
 {
        unsigned long port = (unsigned long __force)addr;
        if (__is_io_address(port))
@@ -469,7 +472,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_readsl(addr, vaddr, count);
 #else
-                __ixp4xx_readsl(port, vaddr, count);
+                __ixp4xx_readsl(addr, vaddr, count);
 #endif
 }
@@ -483,7 +486,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writeb(value, port);
 #else
-                __ixp4xx_writeb(value, port);
+                __ixp4xx_writeb(value, addr);
 #endif
 }
@@ -497,7 +500,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesb(addr, vaddr, count);
 #else
-                __ixp4xx_writesb(port, vaddr, count);
+                __ixp4xx_writesb(addr, vaddr, count);
 #endif
 }
@@ -511,7 +514,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writew(cpu_to_le16(value), addr);
 #else
-                __ixp4xx_writew(value, port);
+                __ixp4xx_writew(value, addr);
 #endif
 }
@@ -525,7 +528,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesw(addr, vaddr, count);
 #else
-                __ixp4xx_writesw(port, vaddr, count);
+                __ixp4xx_writesw(addr, vaddr, count);
 #endif
 }
@@ -539,7 +542,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writel(cpu_to_le32(value), port);
 #else
-                __ixp4xx_writel(value, port);
+                __ixp4xx_writel(value, addr);
 #endif
 }
@@ -553,7 +556,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                __raw_writesl(addr, vaddr, count);
 #else
-                __ixp4xx_writesl(port, vaddr, count);
+                __ixp4xx_writesl(addr, vaddr, count);
 #endif
 }
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index ca808281c7f9..2cf4930372bc 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -93,4 +93,11 @@
 #define IRQ_COYOTE_PCI_SLOT1    IRQ_IXP4XX_GPIO11
 #define IRQ_COYOTE_IDE          IRQ_IXP4XX_GPIO5
+/*
+ * NSLU2 board IRQs
+ */
+#define        IRQ_NSLU2_PCI_INTA      IRQ_IXP4XX_GPIO11
+#define        IRQ_NSLU2_PCI_INTB      IRQ_IXP4XX_GPIO10
+#define        IRQ_NSLU2_PCI_INTC      IRQ_IXP4XX_GPIO9
 #endif
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 004696a95bdb..9444958bec1e 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -36,38 +36,39 @@
 *
 * 0x6000000    0x00004000      ioremap'd       QMgr
 *
- * 0xC0000000   0x00001000      0xffbfe000      PCI CFG 
+ * 0xC0000000   0x00001000      0xffbff000      PCI CFG
 *
- * 0xC4000000   0x00001000      0xffbfd000      EXP CFG 
+ * 0xC4000000   0x00001000      0xffbfe000      EXP CFG
 *
- * 0xC8000000   0x0000C000      0xffbf2000      On-Chip Peripherals
+ * 0xC8000000   0x00013000      0xffbeb000      On-Chip Peripherals
 */
 /*
 * Queue Manager
 */
 #define IXP4XX_QMGR_BASE_PHYS           (0x60000000)
+#define IXP4XX_QMGR_REGION_SIZE         (0x00004000)
 /*
 * Expansion BUS Configuration registers
 */
 #define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFD000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
 /*
 * PCI Config registers
 */
 #define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
 /*
 * Peripheral space
 */
 #define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBF2000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
-#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x0000C000)
+#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 /*
 * Debug UART
@@ -115,25 +116,48 @@
 /*
 * Peripheral Space Register Region Base Addresses
 */
-#define IXP4XX_UART1_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP4XX_UART1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP4XX_UART2_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP4XX_UART2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP4XX_PMU_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP4XX_PMU_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP4XX_INTC_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP4XX_INTC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP4XX_GPIO_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP4XX_GPIO_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP4XX_TIMER_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP4XX_TIMER_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP4XX_EthA_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP4XX_NPEA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP4XX_EthB_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP4XX_NPEB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP4XX_USB_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
+#define IXP4XX_NPEC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP4XX_UART1_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_EthC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP4XX_UART2_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_USB_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
-#define IXP4XX_PMU_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+/* ixp46X only */
-#define IXP4XX_INTC_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_EthA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
-#define IXP4XX_GPIO_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_EthB1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
-#define IXP4XX_TIMER_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_EthB2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
-#define IXP4XX_EthA_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthB3_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
-#define IXP4XX_EthB_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_TIMESYNC_BASE_PHYS       (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
-#define IXP4XX_USB_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+#define IXP4XX_I2C_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
+#define IXP4XX_SSP_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
+#define IXP4XX_UART1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_UART2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_PMU_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP4XX_INTC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_GPIO_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_TIMER_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_NPEA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP4XX_NPEB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP4XX_NPEC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_USB_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+/* ixp46X only */
+#define IXP4XX_EthA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
+#define IXP4XX_EthB1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
+#define IXP4XX_EthB2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
+#define IXP4XX_EthB3_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
+#define IXP4XX_TIMESYNC_BASE_VIRT       (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
+#define IXP4XX_I2C_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
+#define IXP4XX_SSP_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
 /*
 * Constants to make it easy to access  Interrupt Controller registers
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
index d348548b592b..e024d0a1a669 100644
--- a/include/asm-arm/arch-ixp4xx/memory.h
+++ b/include/asm-arm/arch-ixp4xx/memory.h
@@ -12,7 +12,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
new file mode 100644
index 000000000000..b8b347a559c7
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-arm/arch-ixp4xx/nslu2.h
+ *
+ * NSLU2 platform specific definitions
+ *
+ * Author: Mark Rakes <mrakes AT mac.com>
+ * Maintainers: http://www.nslu2-linux.org
+ *
+ * based on ixdp425.h:
+ *      Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+#define NSLU2_FLASH_BASE        IXP4XX_EXP_BUS_CS0_BASE_PHYS
+#define NSLU2_FLASH_SIZE        IXP4XX_EXP_BUS_CSX_REGION_SIZE
+#define NSLU2_SDA_PIN           7
+#define NSLU2_SCL_PIN           6
+/*
+ * NSLU2 PCI IRQs
+ */
+#define NSLU2_PCI_MAX_DEV       3
+#define NSLU2_PCI_IRQ_LINES     3
+/* PCI controller GPIO to IRQ pin mappings */
+#define NSLU2_PCI_INTA_PIN      11
+#define NSLU2_PCI_INTB_PIN      10
+#define NSLU2_PCI_INTC_PIN      9
+#define NSLU2_PCI_INTD_PIN      8
+/* NSLU2 Timer */
+#define NSLU2_FREQ 66000000
+#define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
+#define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
+/* GPIO */
+#define NSLU2_GPIO0             0
+#define NSLU2_GPIO1             1
+#define NSLU2_GPIO2             2
+#define NSLU2_GPIO3             3
+#define NSLU2_GPIO4             4
+#define NSLU2_GPIO5             5
+#define NSLU2_GPIO6             6
+#define NSLU2_GPIO7             7
+#define NSLU2_GPIO8             8
+#define NSLU2_GPIO9             9
+#define NSLU2_GPIO10            10
+#define NSLU2_GPIO11            11
+#define NSLU2_GPIO12            12
+#define NSLU2_GPIO13            13
+#define NSLU2_GPIO14            14
+#define NSLU2_GPIO15            15
+/* Buttons */
+#define NSLU2_PB_GPIO           NSLU2_GPIO5
+#define NSLU2_PO_GPIO           NSLU2_GPIO8     /* power off */
+#define NSLU2_RB_GPIO           NSLU2_GPIO12
+#define NSLU2_PB_IRQ            IRQ_IXP4XX_GPIO5
+#define NSLU2_RB_IRQ            IRQ_IXP4XX_GPIO12
+#define NSLU2_PB_BM             (1L << NSLU2_PB_GPIO)
+#define NSLU2_PO_BM             (1L << NSLU2_PO_GPIO)
+#define NSLU2_RB_BM             (1L << NSLU2_RB_GPIO)
+/* Buzzer */
+#define NSLU2_GPIO_BUZZ         4
+#define NSLU2_BZ_BM             (1L << NSLU2_GPIO_BUZZ)
+/* LEDs */
+#define NSLU2_LED_RED           NSLU2_GPIO0
+#define NSLU2_LED_GRN           NSLU2_GPIO1
+#define NSLU2_LED_RED_BM        (1L << NSLU2_LED_RED)
+#define NSLU2_LED_GRN_BM        (1L << NSLU2_LED_GRN)
+#define NSLU2_LED_DISK1         NSLU2_GPIO2
+#define NSLU2_LED_DISK2         NSLU2_GPIO3
+#define NSLU2_LED_DISK1_BM      (1L << NSLU2_GPIO2)
+#define NSLU2_LED_DISK2_BM      (1L << NSLU2_GPIO3)
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index d13ee7f78c70..f14ed63590c3 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -93,7 +93,7 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 static inline void gpio_line_config(u8 line, u32 direction)
 {
-        if (direction == IXP4XX_GPIO_OUT)
+        if (direction == IXP4XX_GPIO_IN)
                *IXP4XX_GPIO_GPOER |= (1 << line);
        else
                *IXP4XX_GPIO_GPOER &= ~(1 << line);
diff --git a/include/asm-arm/arch-l7200/aux_reg.h b/include/asm-arm/arch-l7200/aux_reg.h
index 762cbc76c501..5b4396de16a0 100644
--- a/include/asm-arm/arch-l7200/aux_reg.h
+++ b/include/asm-arm/arch-l7200/aux_reg.h
@@ -9,7 +9,7 @@
 #ifndef _ASM_ARCH_AUXREG_H
 #define _ASM_ARCH_AUXREG_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define l7200aux_reg    *((volatile unsigned int *) (AUX_BASE))
diff --git a/include/asm-arm/arch-l7200/gp_timers.h b/include/asm-arm/arch-l7200/gp_timers.h
index 6f20962df248..9c4804d13578 100644
--- a/include/asm-arm/arch-l7200/gp_timers.h
+++ b/include/asm-arm/arch-l7200/gp_timers.h
@@ -10,7 +10,7 @@
 #ifndef _ASM_ARCH_GPTIMERS_H
 #define _ASM_ARCH_GPTIMERS_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 /*
 * Layout of L7200 general purpose timer registers
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index fc012a39e2cb..cab8ad0adf09 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -10,7 +10,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h
index c5b9608cb137..9e50a171f78a 100644
--- a/include/asm-arm/arch-l7200/memory.h
+++ b/include/asm-arm/arch-l7200/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset on the L7200 SDB.
 */
-#define PHYS_OFFSET     (0xf0000000UL)
+#define PHYS_OFFSET     UL(0xf0000000)
 #define __virt_to_bus(x) __virt_to_phys(x)
 #define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
index c13bdd9add92..bbcd4335f441 100644
--- a/include/asm-arm/arch-lh7a40x/io.h
+++ b/include/asm-arm/arch-lh7a40x/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /* No ISA or PCI bus on this machine. */
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index c650e6feb9d5..c92bcb837629 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -17,7 +17,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
index d64ee9211eed..33ea29a41654 100644
--- a/include/asm-arm/arch-omap/board-h4.h
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -34,5 +34,11 @@
 #define OMAP24XX_ETHR_START             0x08000300
 #define OMAP24XX_ETHR_GPIO_IRQ          92
+#define H4_CS0_BASE                  0x04000000
+#define H4_CS0_BASE                  0x04000000
+#define H4_CS0_BASE                  0x04000000
 #endif /*  __ASM_ARCH_OMAP_H4_H */
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 79574e0ed13d..b3cf33441f6e 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -26,7 +26,7 @@
 #ifndef __ASM_ARCH_OMAP_INNOVATOR_H
 #define __ASM_ARCH_OMAP_INNOVATOR_H
-#if defined (CONFIG_ARCH_OMAP1510)
+#if defined (CONFIG_ARCH_OMAP15XX)
 #ifndef OMAP_SDRAM_DEVICE
 #define OMAP_SDRAM_DEVICE                       D256M_1X16_4B
@@ -44,7 +44,7 @@ void fpga_write(unsigned char val, int reg);
 unsigned char fpga_read(int reg);
 #endif
-#endif /* CONFIG_ARCH_OMAP1510 */
+#endif /* CONFIG_ARCH_OMAP15XX */
 #if defined (CONFIG_ARCH_OMAP16XX)
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
new file mode 100644
index 000000000000..740c297eb11c
--- /dev/null
+++ b/include/asm-arm/arch-omap/clock.h
@@ -0,0 +1,91 @@
+/*
+ *  linux/include/asm-arm/arch-omap/clock.h
+ *
+ *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_OMAP_CLOCK_H
+#define __ARCH_ARM_OMAP_CLOCK_H
+struct module;
+struct clk {
+        struct list_head        node;
+        struct module           *owner;
+        const char              *name;
+        struct clk              *parent;
+        unsigned long           rate;
+        __u32                   flags;
+        void __iomem            *enable_reg;
+        __u8                    enable_bit;
+        __u8                    rate_offset;
+        __u8                    src_offset;
+        __s8                    usecount;
+        void                    (*recalc)(struct clk *);
+        int                     (*set_rate)(struct clk *, unsigned long);
+        long                    (*round_rate)(struct clk *, unsigned long);
+        void                    (*init)(struct clk *);
+        int                     (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+};
+struct clk_functions {
+        int             (*clk_enable)(struct clk *clk);
+        void            (*clk_disable)(struct clk *clk);
+        int             (*clk_use)(struct clk *clk);
+        void            (*clk_unuse)(struct clk *clk);
+        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
+        struct clk *    (*clk_get_parent)(struct clk *clk);
+        void            (*clk_allow_idle)(struct clk *clk);
+        void            (*clk_deny_idle)(struct clk *clk);
+};
+extern unsigned int mpurate;
+extern struct list_head clocks;
+extern spinlock_t clockfw_lock;
+extern int clk_init(struct clk_functions * custom_clocks);
+extern int clk_register(struct clk *clk);
+extern void clk_unregister(struct clk *clk);
+extern void propagate_rate(struct clk *clk);
+extern void followparent_recalc(struct clk * clk);
+extern void clk_allow_idle(struct clk *clk);
+extern void clk_deny_idle(struct clk *clk);
+/* Clock flags */
+#define RATE_CKCTL              (1 << 0)        /* Main fixed ratio clocks */
+#define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
+#define RATE_PROPAGATES         (1 << 2)        /* Program children too */
+#define VIRTUAL_CLOCK           (1 << 3)        /* Composite clock from table */
+#define ALWAYS_ENABLED          (1 << 4)        /* Clock cannot be disabled */
+#define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
+#define VIRTUAL_IO_ADDRESS      (1 << 6)        /* Clock in virtual address */
+#define CLOCK_IDLE_CONTROL      (1 << 7)
+#define CLOCK_NO_IDLE_PARENT    (1 << 8)
+#define DELAYED_APP             (1 << 9)        /* Delay application of clock */
+#define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
+#define CM_MPU_SEL1             (1 << 11)       /* Domain divider/source */
+#define CM_DSP_SEL1             (1 << 12)
+#define CM_GFX_SEL1             (1 << 13)
+#define CM_MODEM_SEL1           (1 << 14)
+#define CM_CORE_SEL1            (1 << 15)       /* Sets divider for many */
+#define CM_CORE_SEL2            (1 << 16)       /* sets parent for GPT */
+#define CM_WKUP_SEL1            (1 << 17)
+#define CM_PLL_SEL1             (1 << 18)
+#define CM_PLL_SEL2             (1 << 19)
+#define CM_SYSCLKOUT_SEL1       (1 << 20)
+#define CLOCK_IN_OMAP730        (1 << 21)
+#define CLOCK_IN_OMAP1510       (1 << 22)
+#define CLOCK_IN_OMAP16XX       (1 << 23)
+#define CLOCK_IN_OMAP242X       (1 << 24)
+#define CLOCK_IN_OMAP243X       (1 << 25)
+#endif
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 2a676b4f13b5..08d58abd8218 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -31,6 +31,6 @@ struct sys_timer;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
-extern void omap_serial_init(int ports[]);
+extern void omap_serial_init(void);
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index 1119e2b53e72..ec7eb675d922 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -28,12 +28,7 @@
 extern unsigned int system_rev;
-#define OMAP_DIE_ID_0           0xfffe1800
+#define omap2_cpu_rev()         ((system_rev >> 8) & 0x0f)
-#define OMAP_DIE_ID_1           0xfffe1804
-#define OMAP_PRODUCTION_ID_0    0xfffe2000
-#define OMAP_PRODUCTION_ID_1    0xfffe2004
-#define OMAP32_ID_0             0xfffed400
-#define OMAP32_ID_1             0xfffed404
 /*
 * Test if multicore OMAP support is needed
@@ -50,7 +45,7 @@ extern unsigned int system_rev;
 #  define OMAP_NAME omap730
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP1510
+#ifdef CONFIG_ARCH_OMAP15XX
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP1
 #  define MULTI_OMAP1
@@ -79,9 +74,11 @@ extern unsigned int system_rev;
 * Macros to group OMAP into cpu classes.
 * These can be used in most places.
 * cpu_is_omap7xx():    True for OMAP730
- * cpu_is_omap15xx():   True for OMAP1510 and OMAP5910
+ * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
 * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
- * cpu_is_omap24xx():   True for OMAP2420
+ * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
+ * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
+ * cpu_is_omap243x():   True for OMAP2430
 */
 #define GET_OMAP_CLASS  (system_rev & 0xff)
@@ -91,22 +88,35 @@ static inline int is_omap ##class (void)		\
        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
 }
+#define GET_OMAP_SUBCLASS       ((system_rev >> 20) & 0x0fff)
+#define IS_OMAP_SUBCLASS(subclass, id)                  \
+static inline int is_omap ##subclass (void)             \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
+IS_OMAP_SUBCLASS(242x, 0x242)
+IS_OMAP_SUBCLASS(243x, 0x243)
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
 #define cpu_is_omap16xx()               0
 #define cpu_is_omap24xx()               0
+#define cpu_is_omap242x()               0
+#define cpu_is_omap243x()               0
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
 #  undef  cpu_is_omap7xx
 #  define cpu_is_omap7xx()              is_omap7xx()
 # endif
-# if defined(CONFIG_ARCH_OMAP1510)
+# if defined(CONFIG_ARCH_OMAP15XX)
 #  undef  cpu_is_omap15xx
 #  define cpu_is_omap15xx()             is_omap15xx()
 # endif
@@ -119,7 +129,7 @@ IS_OMAP_CLASS(24xx, 0x24)
 #  undef  cpu_is_omap7xx
 #  define cpu_is_omap7xx()              1
 # endif
-# if defined(CONFIG_ARCH_OMAP1510)
+# if defined(CONFIG_ARCH_OMAP15XX)
 #  undef  cpu_is_omap15xx
 #  define cpu_is_omap15xx()             1
 # endif
@@ -129,13 +139,18 @@ IS_OMAP_CLASS(24xx, 0x24)
 # endif
 # if defined(CONFIG_ARCH_OMAP24XX)
 #  undef  cpu_is_omap24xx
+#  undef  cpu_is_omap242x
+#  undef  cpu_is_omap243x
 #  define cpu_is_omap24xx()             1
+#  define cpu_is_omap242x()             is_omap242x()
+#  define cpu_is_omap243x()             is_omap243x()
 # endif
 #endif
 /*
 * Macros to detect individual cpu types.
 * These are only rarely needed.
+ * cpu_is_omap330():    True for OMAP330
 * cpu_is_omap730():    True for OMAP730
 * cpu_is_omap1510():   True for OMAP1510
 * cpu_is_omap1610():   True for OMAP1610
@@ -144,6 +159,9 @@ IS_OMAP_CLASS(24xx, 0x24)
 * cpu_is_omap1621():   True for OMAP1621
 * cpu_is_omap1710():   True for OMAP1710
 * cpu_is_omap2420():   True for OMAP2420
+ * cpu_is_omap2422():   True for OMAP2422
+ * cpu_is_omap2423():   True for OMAP2423
+ * cpu_is_omap2430():   True for OMAP2430
 */
 #define GET_OMAP_TYPE   ((system_rev >> 16) & 0xffff)
@@ -153,6 +171,7 @@ static inline int is_omap ##type (void)			\
        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
 }
+IS_OMAP_TYPE(310, 0x0310)
 IS_OMAP_TYPE(730, 0x0730)
 IS_OMAP_TYPE(1510, 0x1510)
 IS_OMAP_TYPE(1610, 0x1610)
@@ -161,7 +180,11 @@ IS_OMAP_TYPE(5912, 0x1611)
 IS_OMAP_TYPE(1621, 0x1621)
 IS_OMAP_TYPE(1710, 0x1710)
 IS_OMAP_TYPE(2420, 0x2420)
+IS_OMAP_TYPE(2422, 0x2422)
+IS_OMAP_TYPE(2423, 0x2423)
+IS_OMAP_TYPE(2430, 0x2430)
+#define cpu_is_omap310()                0
 #define cpu_is_omap730()                0
 #define cpu_is_omap1510()               0
 #define cpu_is_omap1610()               0
@@ -170,31 +193,33 @@ IS_OMAP_TYPE(2420, 0x2420)
 #define cpu_is_omap1621()               0
 #define cpu_is_omap1710()               0
 #define cpu_is_omap2420()               0
+#define cpu_is_omap2422()               0
+#define cpu_is_omap2423()               0
+#define cpu_is_omap2430()               0
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
 #  undef  cpu_is_omap730
 #  define cpu_is_omap730()              is_omap730()
 # endif
-# if defined(CONFIG_ARCH_OMAP1510)
-#  undef  cpu_is_omap1510
-#  define cpu_is_omap1510()             is_omap1510()
-# endif
 #else
 # if defined(CONFIG_ARCH_OMAP730)
 #  undef  cpu_is_omap730
 #  define cpu_is_omap730()              1
 # endif
-# if defined(CONFIG_ARCH_OMAP1510)
-#  undef  cpu_is_omap1510
-#  define cpu_is_omap1510()             1
-# endif
 #endif
 /*
 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 1611B/5912 and 1710.
+ * between 330 vs. 1510 and 1611B/5912 vs. 1710.
 */
+#if defined(CONFIG_ARCH_OMAP15XX)
+# undef  cpu_is_omap310
+# undef  cpu_is_omap1510
+# define cpu_is_omap310()               is_omap310()
+# define cpu_is_omap1510()              is_omap1510()
+#endif
 #if defined(CONFIG_ARCH_OMAP16XX)
 # undef  cpu_is_omap1610
 # undef  cpu_is_omap1611
@@ -208,9 +233,20 @@ IS_OMAP_TYPE(2420, 0x2420)
 # define cpu_is_omap1710()              is_omap1710()
 #endif
-#if defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_ARCH_OMAP24XX)
-#  undef  cpu_is_omap2420
+# undef  cpu_is_omap2420
-#  define cpu_is_omap2420()             1
+# undef  cpu_is_omap2422
+# undef  cpu_is_omap2423
+# undef  cpu_is_omap2430
+# define cpu_is_omap2420()              is_omap2420()
+# define cpu_is_omap2422()              is_omap2422()
+# define cpu_is_omap2423()              is_omap2423()
+# define cpu_is_omap2430()              is_omap2430()
 #endif
+/* Macros to detect if we have OMAP1 or OMAP2 */
+#define cpu_class_is_omap1()    (cpu_is_omap730() || cpu_is_omap15xx() || \
+                                cpu_is_omap16xx())
+#define cpu_class_is_omap2()    cpu_is_omap24xx()
 #endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 04ebef5c6e95..ccbcb580a5c1 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,9 +22,109 @@
 #define __ASM_ARCH_DMA_H
 #define MAX_DMA_ADDRESS                 0xffffffff
+#define MAX_DMA_CHANNELS                0
+/* Hardware registers for omap1 */
+#define OMAP_DMA_BASE                   (0xfffed800)
+#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
+#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
+#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
+#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
+#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
+#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
+#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
+#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
+#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
+#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
+#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
+#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
+#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
+#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
+#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
+#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
+#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
+#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
+#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
+#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
+/* Hardware registers for omap2 */
+#define OMAP24XX_DMA_BASE               (L4_24XX_BASE + 0x56000)
+#define OMAP_DMA4_REVISION              (OMAP24XX_DMA_BASE + 0x00)
+#define OMAP_DMA4_GCR_REG               (OMAP24XX_DMA_BASE + 0x78)
+#define OMAP_DMA4_IRQSTATUS_L0          (OMAP24XX_DMA_BASE + 0x08)
+#define OMAP_DMA4_IRQSTATUS_L1          (OMAP24XX_DMA_BASE + 0x0c)
+#define OMAP_DMA4_IRQSTATUS_L2          (OMAP24XX_DMA_BASE + 0x10)
+#define OMAP_DMA4_IRQSTATUS_L3          (OMAP24XX_DMA_BASE + 0x14)
+#define OMAP_DMA4_IRQENABLE_L0          (OMAP24XX_DMA_BASE + 0x18)
+#define OMAP_DMA4_IRQENABLE_L1          (OMAP24XX_DMA_BASE + 0x1c)
+#define OMAP_DMA4_IRQENABLE_L2          (OMAP24XX_DMA_BASE + 0x20)
+#define OMAP_DMA4_IRQENABLE_L3          (OMAP24XX_DMA_BASE + 0x24)
+#define OMAP_DMA4_SYSSTATUS             (OMAP24XX_DMA_BASE + 0x28)
+#define OMAP_DMA4_CAPS_0                (OMAP24XX_DMA_BASE + 0x64)
+#define OMAP_DMA4_CAPS_2                (OMAP24XX_DMA_BASE + 0x6c)
+#define OMAP_DMA4_CAPS_3                (OMAP24XX_DMA_BASE + 0x70)
+#define OMAP_DMA4_CAPS_4                (OMAP24XX_DMA_BASE + 0x74)
+#ifdef CONFIG_ARCH_OMAP1
 #define OMAP_LOGICAL_DMA_CH_COUNT       17
+/* Common channel specific registers for omap1 */
+#define OMAP_DMA_CSDP_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
+#define OMAP_DMA_CCR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
+#define OMAP_DMA_CICR_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
+#define OMAP_DMA_CSR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
+#define OMAP_DMA_CEN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
+#define OMAP_DMA_CFN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
+#define OMAP_DMA_CSFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
+#define OMAP_DMA_CSEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
+#define OMAP_DMA_CSAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
+#define OMAP_DMA_CDAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
+#define OMAP_DMA_CDEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
+#define OMAP_DMA_CDFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
+#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
+#else
+#define OMAP_LOGICAL_DMA_CH_COUNT       32      /* REVISIT: Is this 32 + 2? */
+/* Common channel specific registers for omap2 */
+#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
+#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
+#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
+#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
+#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
+#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
+#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
+#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
+#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
+#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
+#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
+#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
+#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
+#endif
+/* Channel specific registers only on omap1 */
+#define OMAP1_DMA_CSSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CDSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
+#define OMAP1_DMA_COLOR_L_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
+#define OMAP1_DMA_CCR2_REG(n)           __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
+#define OMAP1_DMA_COLOR_U_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
+#define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+/* Channel specific registers only on omap2 */
+#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
+#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
+#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
+#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
+#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
+/*----------------------------------------------------------------------------*/
+/* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
 #define OMAP_DMA_MCSI1_TX               1
 #define OMAP_DMA_MCSI1_RX               2
@@ -85,29 +185,72 @@
 #define OMAP_DMA_MMC2_RX                55
 #define OMAP_DMA_CRYPTO_DES_OUT         56
+/* DMA channels for 24xx */
+#define OMAP24XX_DMA_NO_DEVICE          0
+#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
+#define OMAP24XX_DMA_EXT_NDMA_REQ0      2       /* S_DMA_1 */
+#define OMAP24XX_DMA_EXT_NDMA_REQ1      3       /* S_DMA_2 */
+#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
+#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
+#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
+#define OMAP24XX_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
+#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
+#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
+#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
+#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
+#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP_DMA_BASE                   (0xfffed800)
+#define OMAP24XX_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
+#define OMAP24XX_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
+#define OMAP24XX_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
+#define OMAP24XX_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
+#define OMAP24XX_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
+#define OMAP24XX_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
+#define OMAP24XX_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
+#define OMAP24XX_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
+#define OMAP24XX_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
+#define OMAP24XX_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
-#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
+#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
+#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
+#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
+#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* SDMA_30 */
-#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* SDMA_31 */
-#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* SDMA_32 */
-#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* SDMA_33 */
-#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
+#define OMAP24XX_DMA_SPI1_TX0           35      /* SDMA_34 */
-#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
+#define OMAP24XX_DMA_SPI1_RX0           36      /* SDMA_35 */
-#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
+#define OMAP24XX_DMA_SPI1_TX1           37      /* SDMA_36 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* SDMA_37 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* SDMA_38 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* SDMA_39 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* SDMA_40 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* SDMA_41 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* SDMA_42 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* SDMA_43 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* SDMA_44 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* SDMA_45 */
+#define OMAP24XX_DMA_UART1_TX           49      /* SDMA_48 */
+#define OMAP24XX_DMA_UART1_RX           50      /* SDMA_49 */
+#define OMAP24XX_DMA_UART2_TX           51      /* SDMA_50 */
+#define OMAP24XX_DMA_UART2_RX           52      /* SDMA_51 */
+#define OMAP24XX_DMA_UART3_TX           53      /* SDMA_52 */
+#define OMAP24XX_DMA_UART3_RX           54      /* SDMA_53 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* SDMA_54 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* SDMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* SDMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* SDMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* SDMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* SDMA_59 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* SDMA_60 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* SDMA_61 */
+#define OMAP24XX_DMA_MS                 63      /* SDMA_62 */
+/*----------------------------------------------------------------------------*/
+/* Hardware registers for LCD DMA */
 #define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
 #define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
 #define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
@@ -116,7 +259,7 @@
 #define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
 #define OMAP1610_DMA_LCD_BASE           (0xfffee300)
-#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
+#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
 #define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
 #define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
 #define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
@@ -134,37 +277,18 @@
 #define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
 #define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
+#define OMAP_DMA_TOUT_IRQ               (1 << 0)        /* Only on omap1 */
-/* Every LCh has its own set of the registers below */
-#define OMAP_DMA_CSDP(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
-#define OMAP_DMA_CCR(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
-#define OMAP_DMA_CICR(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
-#define OMAP_DMA_CSR(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
-#define OMAP_DMA_CSSA_L(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
-#define OMAP_DMA_CSSA_U(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
-#define OMAP_DMA_CDSA_L(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
-#define OMAP_DMA_CDSA_U(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
-#define OMAP_DMA_CEN(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
-#define OMAP_DMA_CFN(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
-#define OMAP_DMA_CSFI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
-#define OMAP_DMA_CSEI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
-#define OMAP_DMA_CSAC(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
-#define OMAP_DMA_CDAC(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
-#define OMAP_DMA_CDEI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
-#define OMAP_DMA_CDFI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
-#define OMAP_DMA_COLOR_L(n)             (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
-#define OMAP_DMA_COLOR_U(n)             (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
-#define OMAP_DMA_CCR2(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
-#define OMAP_DMA_CLNK_CTRL(n)           (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
-#define OMAP_DMA_LCH_CTRL(n)            (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
-#define OMAP_DMA_TOUT_IRQ               (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
 #define OMAP_DMA_FRAME_IRQ              (1 << 3)
 #define OMAP_DMA_LAST_IRQ               (1 << 4)
 #define OMAP_DMA_BLOCK_IRQ              (1 << 5)
-#define OMAP_DMA_SYNC_IRQ               (1 << 6)
+#define OMAP1_DMA_SYNC_IRQ              (1 << 6)
+#define OMAP2_DMA_PKT_IRQ               (1 << 7)
+#define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
+#define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
+#define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
+#define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
@@ -194,6 +318,7 @@ enum {
        OMAP_LCD_DMA_B2_BOTTOM
 };
+/* REVISIT: Check if BURST_4 is really 1 (or 2) */
 enum omap_dma_burst_mode {
        OMAP_DMA_DATA_BURST_DIS = 0,
        OMAP_DMA_DATA_BURST_4,
@@ -206,6 +331,31 @@ enum omap_dma_color_mode {
        OMAP_DMA_TRANSPARENT_COPY
 };
+struct omap_dma_channel_params {
+        int data_type;          /* data type 8,16,32 */
+        int elem_count;         /* number of elements in a frame */
+        int frame_count;        /* number of frames in a element */
+        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
+        int src_amode;          /* constant , post increment, indexed , double indexed */
+        int src_start;          /* source address : physical */
+        int src_ei;             /* source element index */
+        int src_fi;             /* source frame index */
+        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
+        int dst_amode;          /* constant , post increment, indexed , double indexed */
+        int dst_start;          /* source address : physical */
+        int dst_ei;             /* source element index */
+        int dst_fi;             /* source frame index */
+        int trigger;            /* trigger attached if the channel is synchronized */
+        int sync_mode;          /* sycn on element, frame , block or packet */
+        int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
+        int ie;                 /* interrupt enabled */
+};
 extern void omap_set_dma_priority(int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
                            void (* callback)(int lch, u16 ch_status, void *data),
@@ -217,24 +367,30 @@ extern void omap_start_dma(int lch);
 extern void omap_stop_dma(int lch);
 extern void omap_set_dma_transfer_params(int lch, int data_type,
                                         int elem_count, int frame_count,
-                                         int sync_mode);
+                                         int sync_mode,
+                                         int dma_trigger, int src_or_dst_synch);
 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
                                    u32 color);
 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
-                                    unsigned long src_start);
+                                    unsigned long src_start,
+                                    int src_ei, int src_fi);
 extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
 extern void omap_set_dma_src_data_pack(int lch, int enable);
 extern void omap_set_dma_src_burst_mode(int lch,
                                        enum omap_dma_burst_mode burst_mode);
 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
-                                     unsigned long dest_start);
+                                     unsigned long dest_start,
+                                     int dst_ei, int dst_fi);
 extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
 extern void omap_set_dma_dest_data_pack(int lch, int enable);
 extern void omap_set_dma_dest_burst_mode(int lch,
                                         enum omap_dma_burst_mode burst_mode);
+extern void omap_set_dma_params(int lch,
+                                struct omap_dma_channel_params * params);
 extern void omap_dma_link_lch (int lch_head, int lch_queue);
 extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
@@ -244,9 +400,6 @@ extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
 extern int omap_dma_running(void);
-/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-extern int omap_dma_in_1510_mode(void);
 /* LCD DMA functions */
 extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
                                void *data);
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index 0d29b9c56a95..f8814a84910e 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -10,6 +10,20 @@
 #if defined(CONFIG_ARCH_OMAP1)
+#if defined(CONFIG_ARCH_OMAP730) && \
+        (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
+#error "FIXME: OMAP730 doesn't support multiple-OMAP"
+#elif defined(CONFIG_ARCH_OMAP730)
+#define INT_IH2_IRQ             INT_730_IH2_IRQ
+#elif defined(CONFIG_ARCH_OMAP15XX)
+#define INT_IH2_IRQ             INT_1510_IH2_IRQ
+#elif defined(CONFIG_ARCH_OMAP16XX)
+#define INT_IH2_IRQ             INT_1610_IH2_IRQ
+#else
+#warning "IH2 IRQ defaulted"
+#define INT_IH2_IRQ             INT_1510_IH2_IRQ
+#endif
                .macro  disable_fiq
                .endm
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 676807dc50e1..6a883e0bdbb8 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -19,7 +19,7 @@
 #ifndef __ASM_ARCH_OMAP_FPGA_H
 #define __ASM_ARCH_OMAP_FPGA_H
-#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510)
+#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 extern void omap1510_fpga_init_irq(void);
 #else
 #define omap1510_fpga_init_irq()        (0)
@@ -77,6 +77,8 @@ struct h2p2_dbg_fpga {
 #define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
 #define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
+#define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
+#define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
 /*
 * ---------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index 74cb2b93b700..f486b72070ea 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -26,7 +26,7 @@
 #ifndef __ASM_ARCH_OMAP_GPIO_H
 #define __ASM_ARCH_OMAP_GPIO_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #include <asm/arch/irqs.h>
 #include <asm/io.h>
@@ -67,7 +67,7 @@
 #define OMAP_GPIO_IRQ(nr)       (OMAP_GPIO_IS_MPUIO(nr) ? \
                                 IH_MPUIO_BASE + ((nr) & 0x0f) : \
-                                 IH_GPIO_BASE + ((nr) & 0x3f))
+                                 IH_GPIO_BASE + (nr))
 extern int omap_gpio_init(void);        /* Call from board init only */
 extern int omap_request_gpio(int gpio);
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 60201e1dd6ad..5406b875c422 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -267,8 +267,6 @@
 #define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
 #define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
-#ifndef __ASSEMBLER__
 /*
 * ---------------------------------------------------------------------------
 * Processor specific defines
@@ -277,13 +275,11 @@
 #include "omap730.h"
 #include "omap1510.h"
-#ifdef CONFIG_ARCH_OMAP24XX
 #include "omap24xx.h"
-#endif
 #include "omap16xx.h"
+#ifndef __ASSEMBLER__
 /*
 * ---------------------------------------------------------------------------
 * Board specific defines
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 11fbf629bf75..f5bcc9a1aed6 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -34,6 +34,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
@@ -50,23 +52,33 @@
 * ----------------------------------------------------------------------------
 */
+#define PCIO_BASE       0
 #if defined(CONFIG_ARCH_OMAP1)
 #define IO_PHYS         0xFFFB0000
-#define IO_OFFSET      -0x01000000      /* Virtual IO = 0xfefb0000 */
+#define IO_OFFSET       0x01000000      /* Virtual IO = 0xfefb0000 */
 #define IO_SIZE         0x40000
+#define IO_VIRT         (IO_PHYS - IO_OFFSET)
+#define IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
+#define io_p2v(pa)      ((pa) - IO_OFFSET)
+#define io_v2p(va)      ((va) + IO_OFFSET)
 #elif defined(CONFIG_ARCH_OMAP2)
-#define IO_PHYS         0x48000000      /* L4 peripherals; other stuff has to be mapped *
-                                         * manually. */
-#define IO_OFFSET       0x90000000      /* Virtual IO = 0xd8000000 */
-#define IO_SIZE         0x08000000
-#endif
-#define IO_VIRT         (IO_PHYS + IO_OFFSET)
+/* We map both L3 and L4 on OMAP2 */
-#define IO_ADDRESS(x)   ((x) + IO_OFFSET)
+#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
-#define PCIO_BASE       0
+#define L3_24XX_VIRT    0xf8000000
-#define io_p2v(x)       ((x) + IO_OFFSET)
+#define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
-#define io_v2p(x)       ((x) - IO_OFFSET)
+#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 */
+#define L4_24XX_VIRT    0xd8000000
+#define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
+#define IO_OFFSET       0x90000000
+#define IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
+#endif
 #ifndef __ASSEMBLER__
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 74e108ccac16..4ffce1d77759 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -22,8 +22,8 @@
 *       are different.
 */
-#ifndef __ASM_ARCH_OMAP1510_IRQS_H
+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
-#define __ASM_ARCH_OMAP1510_IRQS_H
+#define __ASM_ARCH_OMAP15XX_IRQS_H
 /*
 * IRQ numbers for interrupt handler 1
@@ -31,7 +31,6 @@
 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
 *
 */
-#define INT_IH2_IRQ             0
 #define INT_CAMERA              1
 #define INT_FIQ                 3
 #define INT_RTDX                6
@@ -60,6 +59,7 @@
 /*
 * OMAP-1510 specific IRQ numbers for interrupt handler 1
 */
+#define INT_1510_IH2_IRQ        0
 #define INT_1510_RES2           2
 #define INT_1510_SPI_TX         4
 #define INT_1510_SPI_RX         5
@@ -71,6 +71,7 @@
 /*
 * OMAP-1610 specific IRQ numbers for interrupt handler 1
 */
+#define INT_1610_IH2_IRQ        0
 #define INT_1610_IH2_FIQ        2
 #define INT_1610_McBSP2_TX      4
 #define INT_1610_McBSP2_RX      5
@@ -231,6 +232,12 @@
 #define INT_730_DMA_CH15        (62 + IH2_BASE)
 #define INT_730_NAND            (63 + IH2_BASE)
+#define INT_24XX_SYS_NIRQ       7
+#define INT_24XX_SDMA_IRQ0      12
+#define INT_24XX_SDMA_IRQ1      13
+#define INT_24XX_SDMA_IRQ2      14
+#define INT_24XX_SDMA_IRQ3      15
+#define INT_24XX_DSS_IRQ        25
 #define INT_24XX_GPIO_BANK1     29
 #define INT_24XX_GPIO_BANK2     30
 #define INT_24XX_GPIO_BANK3     31
@@ -253,7 +260,7 @@ extern void omap_init_irq(void);
 * The definition of NR_IRQS is in board-specific header file, which is
 * included via hardware.h
 */
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #ifndef NR_IRQS
 #define NR_IRQS                 IH_BOARD_BASE
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
index 305bdeb16ab8..e79d98ab2ab6 100644
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -24,7 +24,7 @@
 #ifndef __ASM_ARCH_OMAP_MCBSP_H
 #define __ASM_ARCH_OMAP_MCBSP_H
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define OMAP730_MCBSP1_BASE     0xfffb1000
 #define OMAP730_MCBSP2_BASE     0xfffb1800
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index ef32d61eec7a..df50dd53e1dd 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -37,9 +37,9 @@
 * Physical DRAM offset.
 */
 #if defined(CONFIG_ARCH_OMAP1)
-#define PHYS_OFFSET             (0x10000000UL)
+#define PHYS_OFFSET             UL(0x10000000)
 #elif defined(CONFIG_ARCH_OMAP2)
-#define PHYS_OFFSET             (0x80000000UL)
+#define PHYS_OFFSET             UL(0x80000000)
 #endif
 /*
@@ -61,12 +61,12 @@
 * Note that the is_lbus_device() test is not very efficient on 1510
 * because of the strncmp().
 */
-#ifdef CONFIG_ARCH_OMAP1510
+#ifdef CONFIG_ARCH_OMAP15XX
 /*
 * OMAP-1510 Local Bus address offset
 */
-#define OMAP1510_LB_OFFSET      (0x30000000UL)
+#define OMAP1510_LB_OFFSET      UL(0x30000000)
 #define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
@@ -84,7 +84,7 @@
                                        virt_to_lbus(addr) : \
                                        __virt_to_bus(addr);})
-#endif  /* CONFIG_ARCH_OMAP1510 */
+#endif  /* CONFIG_ARCH_OMAP15XX */
 #endif
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h
new file mode 100644
index 000000000000..46be8b8d6346
--- /dev/null
+++ b/include/asm-arm/arch-omap/menelaus.h
@@ -0,0 +1,22 @@
+/*
+ * linux/include/asm-arm/arch-omap/menelaus.h
+ *
+ * Functions to access Menelaus power management chip
+ */
+#ifndef __ASM_ARCH_MENELAUS_H
+#define __ASM_ARCH_MENELAUS_H
+extern void menelaus_mmc_register(void (*callback)(u8 card_mask),
+                                  unsigned long data);
+extern void menelaus_mmc_remove(void);
+extern void menelaus_mmc_opendrain(int enable);
+#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
+#define omap_has_menelaus()     1
+#else
+#define omap_has_menelaus()     0
+#endif
+#endif
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 1b1ad4105349..13415a9aab06 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -4,7 +4,7 @@
 * Table of the Omap register configurations for the FUNC_MUX and
 * PULL_DWN combinations.
 *
- * Copyright (C) 2003 Nokia Corporation
+ * Copyright (C) 2003 - 2005 Nokia Corporation
 *
 * Written by Tony Lindgren <tony.lindgren@nokia.com>
 *
@@ -58,6 +58,16 @@
                                        .pu_pd_reg = PU_PD_SEL_##reg, \
                                        .pu_pd_val = status,
+#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
+                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+#define PULL_REG_730(reg, bit, status)  .pull_name = "OMAP730_IO_CONF_"#reg, \
+                                        .pull_reg = OMAP730_IO_CONF_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
 #else
 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
@@ -71,6 +81,15 @@
 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
                                        .pu_pd_val = status,
+#define MUX_REG_730(reg, mode_offset, mode) \
+                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+#define PULL_REG_730(reg, bit, status)  .pull_reg = OMAP730_IO_CONF_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
 #endif /* CONFIG_OMAP_MUX_DEBUG */
 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
@@ -84,13 +103,44 @@
        PU_PD_REG(pu_pd_reg, pu_pd_status)              \
 },
+/*
+ * OMAP730 has a slightly different config for the pin mux.
+ * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
+ *   not the FUNC_MUX_CTRL_x regs from hardware.h
+ * - for pull-up/down, only has one enable bit which is is in the same register
+ *   as mux config
+ */
+#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   \
+                   pull_reg, pull_bit, pull_status,     \
+                   pu_pd_reg, pu_pd_status, debug_status)\
+{                                                       \
+        .name =  desc,                                  \
+        .debug = debug_status,                          \
+        MUX_REG_730(mux_reg, mode_offset, mode)         \
+        PULL_REG_730(mux_reg, pull_bit, pull_status)    \
+        PU_PD_REG(pu_pd_reg, pu_pd_status)              \
+},
+#define MUX_CFG_24XX(desc, reg_offset, mode,                    \
+                                pull_en, pull_mode, dbg)        \
+{                                                               \
+        .name           = desc,                                 \
+        .debug          = dbg,                                  \
+        .mux_reg        = reg_offset,                           \
+        .mask           = mode,                                 \
+        .pull_val       = pull_en,                              \
+        .pu_pd_val      = pull_mode,                            \
+},
 #define PULL_DISABLED   0
 #define PULL_ENABLED    1
 #define PULL_DOWN       0
 #define PULL_UP         1
-typedef struct {
+struct pin_config {
        char *name;
        unsigned char busy;
        unsigned char debug;
@@ -108,13 +158,23 @@ typedef struct {
        const char *pu_pd_name;
        const unsigned int pu_pd_reg;
        const unsigned char pu_pd_val;
-} reg_cfg_set;
+};
-/*
+enum omap730_index {
- * Lookup table for FUNC_MUX and PULL_DWN register combinations for each
+        /* OMAP 730 keyboard */
- * device. See also reg_cfg_table below for the register values.
+        E2_730_KBR0,
- */
+        J7_730_KBR1,
-typedef enum {
+        E1_730_KBR2,
+        F3_730_KBR3,
+        D2_730_KBR4,
+        C2_730_KBC0,
+        D3_730_KBC1,
+        E4_730_KBC2,
+        F4_730_KBC3,
+        E3_730_KBC4,
+};
+enum omap1xxx_index {
        /* UART1 (BT_UART_GATING)*/
        UART1_TX = 0,
        UART1_RTS,
@@ -331,245 +391,34 @@ typedef enum {
        V10_1610_CF_IREQ,
        W10_1610_CF_RESET,
        W11_1610_CF_CD1,
-} reg_cfg_t;
+};
-#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)
+enum omap24xx_index {
+        /* 24xx I2C */
+        M19_24XX_I2C1_SCL,
+        L15_24XX_I2C1_SDA,
+        J15_24XX_I2C2_SCL,
+        H19_24XX_I2C2_SDA,
-/*
+        /* 24xx Menelaus interrupt */
- * Table of various FUNC_MUX and PULL_DWN combinations for each device.
+        W19_24XX_SYS_NIRQ,
- * See also reg_cfg_t above for the lookup table.
- */
-static const reg_cfg_set __initdata_or_module
-reg_cfg_table[] = {
-/*
- *       description            mux  mode   mux  pull pull  pull  pu_pd  pu  dbg
- *                              reg  offset mode reg  bit   ena   reg
- */
-MUX_CFG("UART1_TX",              9,   21,    1,   2,   3,   0,   NA,     0,  0)
-MUX_CFG("UART1_RTS",             9,   12,    1,   2,   0,   0,   NA,     0,  0)
-/* UART2 (COM_UART_GATING), conflicts with USB2 */
-MUX_CFG("UART2_TX",              C,   27,    1,   3,   3,   0,   NA,     0,  0)
-MUX_CFG("UART2_RX",              C,   18,    0,   3,   1,   1,   NA,     0,  0)
-MUX_CFG("UART2_CTS",             C,   21,    0,   3,   1,   1,   NA,     0,  0)
-MUX_CFG("UART2_RTS",             C,   24,    1,   3,   2,   0,   NA,     0,  0)
-/* UART3 (GIGA_UART_GATING) */
-MUX_CFG("UART3_TX",              6,    0,    1,   0,  30,   0,   NA,     0,  0)
-MUX_CFG("UART3_RX",              6,    3,    0,   0,  31,   1,   NA,     0,  0)
-MUX_CFG("UART3_CTS",             5,   12,    2,   0,  24,   0,   NA,     0,  0)
-MUX_CFG("UART3_RTS",             5,   15,    2,   0,  25,   0,   NA,     0,  0)
-MUX_CFG("UART3_CLKREQ",          9,   27,    0,   2,   5,   0,   NA,     0,  0)
-MUX_CFG("UART3_BCLK",            A,    0,    0,   2,   6,   0,   NA,     0,  0)
-MUX_CFG("Y15_1610_UART3_RTS",    A,    0,    1,   2,   6,   0,   NA,     0,  0)
-/* PWT & PWL, conflicts with UART3 */
-MUX_CFG("PWT",                   6,    0,    2,   0,  30,   0,   NA,     0,  0)
-MUX_CFG("PWL",                   6,    3,    1,   0,  31,   1,   NA,     0,  0)
-/* USB internal master generic */
-MUX_CFG("R18_USB_VBUS",          7,    9,    2,   1,  11,   0,   NA,     0,  1)
-MUX_CFG("R18_1510_USB_GPIO0",    7,    9,    0,   1,  11,   1,   NA,     0,  1)
-/* works around erratum:  W4_USB_PUEN and W4_USB_PUDIS are switched! */
-MUX_CFG("W4_USB_PUEN",           D,    3,    3,   3,   5,   1,   NA,     0,  1)
-MUX_CFG("W4_USB_CLKO",           D,    3,    1,   3,   5,   0,   NA,     0,  1)
-MUX_CFG("W4_USB_HIGHZ",          D,    3,    4,   3,   5,   0,    3,     0,  1)
-MUX_CFG("W4_GPIO58",             D,    3,    7,   3,   5,   0,    3,     0,  1)
-/* USB1 master */
-MUX_CFG("USB1_SUSP",             8,   27,    2,   1,  27,   0,   NA,     0,  1)
-MUX_CFG("USB1_SE0",              9,    0,    2,   1,  28,   0,   NA,     0,  1)
-MUX_CFG("W13_1610_USB1_SE0",     9,    0,    4,   1,  28,   0,   NA,     0,  1)
-MUX_CFG("USB1_TXEN",             9,    3,    2,   1,  29,   0,   NA,     0,  1)
-MUX_CFG("USB1_TXD",              9,   24,    1,   2,   4,   0,   NA,     0,  1)
-MUX_CFG("USB1_VP",               A,    3,    1,   2,   7,   0,   NA,     0,  1)
-MUX_CFG("USB1_VM",               A,    6,    1,   2,   8,   0,   NA,     0,  1)
-MUX_CFG("USB1_RCV",              A,    9,    1,   2,   9,   0,   NA,     0,  1)
-MUX_CFG("USB1_SPEED",            A,   12,    2,   2,  10,   0,   NA,     0,  1)
-MUX_CFG("R13_1610_USB1_SPEED",   A,   12,    5,   2,  10,   0,   NA,     0,  1)
-MUX_CFG("R13_1710_USB1_SEO",     A,   12,    5,   2,  10,   0,   NA,     0,  1)
-/* USB2 master */
-MUX_CFG("USB2_SUSP",             B,    3,    1,   2,  17,   0,   NA,     0,  1)
-MUX_CFG("USB2_VP",               B,    6,    1,   2,  18,   0,   NA,     0,  1)
-MUX_CFG("USB2_TXEN",             B,    9,    1,   2,  19,   0,   NA,     0,  1)
-MUX_CFG("USB2_VM",               C,   18,    1,   3,   0,   0,   NA,     0,  1)
-MUX_CFG("USB2_RCV",              C,   21,    1,   3,   1,   0,   NA,     0,  1)
-MUX_CFG("USB2_SE0",              C,   24,    2,   3,   2,   0,   NA,     0,  1)
-MUX_CFG("USB2_TXD",              C,   27,    2,   3,   3,   0,   NA,     0,  1)
-/* OMAP-1510 GPIO */
-MUX_CFG("R18_1510_GPIO0",        7,    9,    0,   1,  11,   1,    0,     0,  1)
-MUX_CFG("R19_1510_GPIO1",        7,    6,    0,   1,  10,   1,    0,     0,  1)
-MUX_CFG("M14_1510_GPIO2",        7,    3,    0,   1,   9,   1,    0,     0,  1)
-/* OMAP1610 GPIO */
-MUX_CFG("P18_1610_GPIO3",        7,    0,    0,   1,   8,   0,   NA,     0,  1)
-MUX_CFG("Y15_1610_GPIO17",       A,    0,    7,   2,   6,   0,   NA,     0,  1)
-/* OMAP-1710 GPIO */
-MUX_CFG("R18_1710_GPIO0",        7,    9,    0,   1,  11,   1,    1,     1,  1)
-MUX_CFG("V2_1710_GPIO10",        F,   27,    1,   4,   3,   1,    4,     1,  1)
-MUX_CFG("N21_1710_GPIO14",       6,    9,    0,   1,   1,   1,    1,     1,  1)
-MUX_CFG("W15_1710_GPIO40",       9,   27,    7,   2,   5,   1,    2,     1,  1)
-/* MPUIO */
-MUX_CFG("MPUIO2",                7,   18,    0,   1,  14,   1,   NA,     0,  1)
-MUX_CFG("N15_1610_MPUIO2",       7,   18,    0,   1,  14,   1,    1,     0,  1)
-MUX_CFG("MPUIO4",                7,   15,    0,   1,  13,   1,   NA,     0,  1)
-MUX_CFG("MPUIO5",                7,   12,    0,   1,  12,   1,   NA,     0,  1)
-MUX_CFG("T20_1610_MPUIO5",       7,   12,    0,   1,  12,   0,    3,     0,  1)
-MUX_CFG("W11_1610_MPUIO6",      10,   15,    2,   3,   8,   0,    3,     0,  1)
-MUX_CFG("V10_1610_MPUIO7",       A,   24,    2,   2,  14,   0,    2,     0,  1)
-MUX_CFG("W11_1610_MPUIO9",      10,   15,    1,   3,   8,   0,    3,     0,  1)
-MUX_CFG("V10_1610_MPUIO10",      A,   24,    1,   2,  14,   0,    2,     0,  1)
-MUX_CFG("W10_1610_MPUIO11",      A,   18,    2,   2,  11,   0,    2,     0,  1)
-MUX_CFG("E20_1610_MPUIO13",      3,   21,    1,   0,   7,   0,    0,     0,  1)
-MUX_CFG("U20_1610_MPUIO14",      9,    6,    6,   0,  30,   0,    0,     0,  1)
-MUX_CFG("E19_1610_MPUIO15",      3,   18,    1,   0,   6,   0,    0,     0,  1)
-/* MCBSP2 */
-MUX_CFG("MCBSP2_CLKR",           C,    6,    0,   2,  27,   1,   NA,     0,  1)
-MUX_CFG("MCBSP2_CLKX",           C,    9,    0,   2,  29,   1,   NA,     0,  1)
-MUX_CFG("MCBSP2_DR",             C,    0,    0,   2,  26,   1,   NA,     0,  1)
-MUX_CFG("MCBSP2_DX",             C,   15,    0,   2,  31,   1,   NA,     0,  1)
-MUX_CFG("MCBSP2_FSR",            C,   12,    0,   2,  30,   1,   NA,     0,  1)
-MUX_CFG("MCBSP2_FSX",            C,    3,    0,   2,  27,   1,   NA,     0,  1)
-/* MCBSP3 NOTE: Mode must 1 for clock */
-MUX_CFG("MCBSP3_CLKX",           9,    3,    1,   1,  29,   0,   NA,     0,  1)
-/* Misc ballouts */
-MUX_CFG("BALLOUT_V8_ARMIO3",     B,   18,    0,   2,  25,   1,   NA,     0,  1)
-MUX_CFG("N20_HDQ",             6,   18,    1,   1,   4,   0,    1,     4,  0)
-/* OMAP-1610 MMC2 */
-MUX_CFG("W8_1610_MMC2_DAT0",     B,   21,    6,   2,  23,   1,    2,     1,  1)
-MUX_CFG("V8_1610_MMC2_DAT1",     B,   27,    6,   2,  25,   1,    2,     1,  1)
-MUX_CFG("W15_1610_MMC2_DAT2",    9,   12,    6,   2,   5,   1,    2,     1,  1)
-MUX_CFG("R10_1610_MMC2_DAT3",    B,   18,    6,   2,  22,   1,    2,     1,  1)
-MUX_CFG("Y10_1610_MMC2_CLK",     B,    3,    6,   2,  17,   0,    2,     0,  1)
-MUX_CFG("Y8_1610_MMC2_CMD",      B,   24,    6,   2,  24,   1,    2,     1,  1)
-MUX_CFG("V9_1610_MMC2_CMDDIR",   B,   12,    6,   2,  20,   0,    2,     1,  1)
-MUX_CFG("V5_1610_MMC2_DATDIR0",  B,   15,    6,   2,  21,   0,    2,     1,  1)
-MUX_CFG("W19_1610_MMC2_DATDIR1", 8,   15,    6,   1,  23,   0,    1,     1,  1)
-MUX_CFG("R18_1610_MMC2_CLKIN",   7,    9,    6,   1,  11,   0,    1,    11,  1)
-/* OMAP-1610 External Trace Interface */
-MUX_CFG("M19_1610_ETM_PSTAT0",   5,   27,    1,   0,  29,   0,    0,     0,  1)
-MUX_CFG("L15_1610_ETM_PSTAT1",   5,   24,    1,   0,  28,   0,    0,     0,  1)
-MUX_CFG("L18_1610_ETM_PSTAT2",   5,   21,    1,   0,  27,   0,    0,     0,  1)
-MUX_CFG("L19_1610_ETM_D0",       5,   18,    1,   0,  26,   0,    0,     0,  1)
-MUX_CFG("J19_1610_ETM_D6",       5,    0,    1,   0,  20,   0,    0,     0,  1)
-MUX_CFG("J18_1610_ETM_D7",       5,   27,    1,   0,  19,   0,    0,     0,  1)
-/* OMAP16XX GPIO */
-MUX_CFG("P20_1610_GPIO4",        6,   27,    0,   1,   7,   0,    1,     1,  1)
-MUX_CFG("V9_1610_GPIO7",         B,   12,    1,   2,  20,   0,    2,     1,  1)
-MUX_CFG("W8_1610_GPIO9",         B,   21,    0,   2,  23,   0,    2,     1,  1)
-MUX_CFG("N20_1610_GPIO11",       6,   18,    0,   1,   4,   0,    1,     1,  1)
-MUX_CFG("N19_1610_GPIO13",       6,   12,    0,   1,   2,   0,    1,     1,  1)
-MUX_CFG("P10_1610_GPIO22",       C,    0,    7,   2,  26,   0,    2,     1,  1)
-MUX_CFG("V5_1610_GPIO24",        B,   15,    7,   2,  21,   0,    2,     1,  1)
-MUX_CFG("AA20_1610_GPIO_41",     9,    9,    7,   1,  31,   0,    1,     1,  1)
-MUX_CFG("W19_1610_GPIO48",       8,   15,    7,   1,  23,   1,    1,     0,  1)
-MUX_CFG("M7_1610_GPIO62",       10,    0,    0,   4,  24,   0,    4,     0,  1)
-MUX_CFG("V14_16XX_GPIO37",       9,   18,    7,   2,   2,   0,    2,     2,  0)
-MUX_CFG("R9_16XX_GPIO18",        C,   18,    7,   3,   0,   0,    3,     0,  0)
-MUX_CFG("L14_16XX_GPIO49",       6,    3,    7,   0,  31,   0,    0,    31,  0)
-/* OMAP-1610 uWire */
-MUX_CFG("V19_1610_UWIRE_SCLK",   8,    6,    0,   1,  20,   0,    1,     1,  1)
-MUX_CFG("U18_1610_UWIRE_SDI",    8,    0,    0,   1,  18,   0,    1,     1,  1)
-MUX_CFG("W21_1610_UWIRE_SDO",    8,    3,    0,   1,  19,   0,    1,     1,  1)
-MUX_CFG("N14_1610_UWIRE_CS0",    8,    9,    1,   1,  21,   0,    1,     1,  1)
-MUX_CFG("P15_1610_UWIRE_CS3",    8,   12,    1,   1,  22,   0,    1,     1,  1)
-MUX_CFG("N15_1610_UWIRE_CS1",    7,   18,    2,   1,  14,   0,   NA,     0,  1)
-/* OMAP-1610 Flash */
-MUX_CFG("L3_1610_FLASH_CS2B_OE",10,    6,    1,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("M8_1610_FLASH_CS2B_WE",10,    3,    1,  NA,   0,   0,   NA,     0,  1)
-/* First MMC interface, same on 1510, 1610 and 1710 */
-MUX_CFG("MMC_CMD",               A,   27,    0,   2,  15,   1,    2,     1,  1)
-MUX_CFG("MMC_DAT1",              A,   24,    0,   2,  14,   1,    2,     1,  1)
-MUX_CFG("MMC_DAT2",              A,   18,    0,   2,  12,   1,    2,     1,  1)
-MUX_CFG("MMC_DAT0",              B,    0,    0,   2,  16,   1,    2,     1,  1)
-MUX_CFG("MMC_CLK",               A,   21,    0,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("MMC_DAT3",             10,   15,    0,   3,   8,   1,    3,     1,  1)
-MUX_CFG("M15_1710_MMC_CLKI",     6,   21,    2,   0,   0,   0,   NA,     0,  1)
-MUX_CFG("P19_1710_MMC_CMDDIR",   6,   24,    6,   0,   0,   0,   NA,     0,  1)
-MUX_CFG("P20_1710_MMC_DATDIR0",  6,   27,    5,   0,   0,   0,   NA,     0,  1)
-/* OMAP-1610 USB0 alternate configuration */
-MUX_CFG("W9_USB0_TXEN",          B,   9,     5,   2,  19,   0,    2,     0,  1)
-MUX_CFG("AA9_USB0_VP",           B,   6,     5,   2,  18,   0,    2,     0,  1)
-MUX_CFG("Y5_USB0_RCV",           C,  21,     5,   3,   1,   0,    1,     0,  1)
-MUX_CFG("R9_USB0_VM",            C,  18,     5,   3,   0,   0,    3,     0,  1)
-MUX_CFG("V6_USB0_TXD",           C,  27,     5,   3,   3,   0,    3,     0,  1)
-MUX_CFG("W5_USB0_SE0",           C,  24,     5,   3,   2,   0,    3,     0,  1)
-MUX_CFG("V9_USB0_SPEED",         B,  12,     5,   2,  20,   0,    2,     0,  1)
-MUX_CFG("Y10_USB0_SUSP",         B,   3,     5,   2,  17,   0,    2,     0,  1)
-/* USB2 interface */
-MUX_CFG("W9_USB2_TXEN",          B,   9,     1,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("AA9_USB2_VP",           B,   6,     1,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("Y5_USB2_RCV",           C,  21,     1,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("R9_USB2_VM",            C,  18,     1,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("V6_USB2_TXD",           C,  27,     2,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("W5_USB2_SE0",           C,  24,     2,  NA,   0,   0,   NA,     0,  1)
-/* 16XX UART */
-MUX_CFG("R13_1610_UART1_TX",     A,  12,     6,   2,  10,   0,    2,    10,  1)
-MUX_CFG("V14_16XX_UART1_RX",     9,  18,     0,   2,   2,   0,    2,     2,  1)
-MUX_CFG("R14_1610_UART1_CTS",    9,  15,     0,   2,   1,   0,    2,     1,  1)
-MUX_CFG("AA15_1610_UART1_RTS",   9,  12,     1,   2,   0,   0,    2,     0,  1)
-MUX_CFG("R9_16XX_UART2_RX",      C,  18,     0,   3,   0,   0,    3,     0,  1)
-MUX_CFG("L14_16XX_UART3_RX",     6,   3,     0,   0,  31,   0,    0,    31,  1)
-/* I2C interface */
-MUX_CFG("I2C_SCL",               7,  24,     0,  NA,   0,   0,   NA,     0,  0)
-MUX_CFG("I2C_SDA",               7,  27,     0,  NA,   0,   0,   NA,     0,  0)
-/* Keypad */
-MUX_CFG("F18_1610_KBC0",         3,  15,     0,   0,   5,   1,    0,     0,  0)
-MUX_CFG("D20_1610_KBC1",         3,  12,     0,   0,   4,   1,    0,     0,  0)
-MUX_CFG("D19_1610_KBC2",         3,   9,     0,   0,   3,   1,    0,     0,  0)
-MUX_CFG("E18_1610_KBC3",         3,   6,     0,   0,   2,   1,    0,     0,  0)
-MUX_CFG("C21_1610_KBC4",         3,   3,     0,   0,   1,   1,    0,     0,  0)
-MUX_CFG("G18_1610_KBR0",         4,   0,     0,   0,   10,  1,    0,     1,  0)
-MUX_CFG("F19_1610_KBR1",         3,   27,    0,   0,   9,   1,    0,     1,  0)
-MUX_CFG("H14_1610_KBR2",         3,   24,    0,   0,   8,   1,    0,     1,  0)
-MUX_CFG("E20_1610_KBR3",         3,   21,    0,   0,   7,   1,    0,     1,  0)
-MUX_CFG("E19_1610_KBR4",         3,   18,    0,   0,   6,   1,    0,     1,  0)
-MUX_CFG("N19_1610_KBR5",         6,  12,     1,   1,   2,   1,    1,     1,  0)
-/* Power management */
-MUX_CFG("T20_1610_LOW_PWR",      7,   12,    1,   NA,   0,   0,   NA,    0,  0)
-/* MCLK Settings */
-MUX_CFG("V5_1710_MCLK_ON",       B,   15,    0,   NA,   0,   0,   NA,    0,  0)
-MUX_CFG("V5_1710_MCLK_OFF",      B,   15,    6,   NA,   0,   0,   NA,    0,  0)
-MUX_CFG("R10_1610_MCLK_ON",      B,   18,    0,   NA,  22,   0,   NA,    1,  0)
-MUX_CFG("R10_1610_MCLK_OFF",     B,   18,    6,   2,   22,   1,   2,     1,  1)
-/* CompactFlash controller, conflicts with MMC1 */
-MUX_CFG("P11_1610_CF_CD2",       A,   27,    3,   2,   15,   1,   2,     1,  1)
-MUX_CFG("R11_1610_CF_IOIS16",    B,    0,    3,   2,   16,   1,   2,     1,  1)
-MUX_CFG("V10_1610_CF_IREQ",      A,   24,    3,   2,   14,   0,   2,     0,  1)
-MUX_CFG("W10_1610_CF_RESET",     A,   18,    3,   2,   12,   1,   2,     1,  1)
-MUX_CFG("W11_1610_CF_CD1",      10,   15,    3,   3,    8,   1,   3,     1,  1)
-};
-#endif  /* __MUX_C__ */
+        /* 24xx GPIO */
+        Y20_24XX_GPIO60,
+        M15_24XX_GPIO92,
+};
 #ifdef  CONFIG_OMAP_MUX
 /* setup pin muxing in Linux */
-extern int omap_cfg_reg(reg_cfg_t reg_cfg);
+extern int omap1_mux_init(void);
+extern int omap2_mux_init(void);
+extern int omap_mux_register(struct pin_config * pins, unsigned long size);
+extern int omap_cfg_reg(unsigned long reg_cfg);
 #else
 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
-static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; }
+static inline int omap1_mux_init(void) { return 0; }
+static inline int omap2_mux_init(void) { return 0; }
+static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 #endif
 #endif
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
index f086a3933906..c575d354850f 100644
--- a/include/asm-arm/arch-omap/omap1510.h
+++ b/include/asm-arm/arch-omap/omap1510.h
@@ -25,8 +25,8 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#ifndef __ASM_ARCH_OMAP1510_H
+#ifndef __ASM_ARCH_OMAP15XX_H
-#define __ASM_ARCH_OMAP1510_H
+#define __ASM_ARCH_OMAP15XX_H
 /*
 * ----------------------------------------------------------------------------
@@ -44,5 +44,5 @@
 #define OMAP1510_DSPREG_SIZE    SZ_128K
 #define OMAP1510_DSPREG_START   0xE1000000
-#endif /*  __ASM_ARCH_OMAP1510_H */
+#endif /*  __ASM_ARCH_OMAP15XX_H */
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index a9105466a417..6e59805fa654 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -1,15 +1,24 @@
 #ifndef __ASM_ARCH_OMAP24XX_H
 #define __ASM_ARCH_OMAP24XX_H
-#define OMAP24XX_L4_IO_BASE     0x48000000
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers. Note also that some of these defines are needed
+ * for omap1 to compile without adding ifdefs.
+ */
+#define L4_24XX_BASE            0x48000000
+#define L3_24XX_BASE            0x68000000
 /* interrupt controller */
-#define OMAP24XX_IC_BASE        (OMAP24XX_L4_IO_BASE + 0xfe000)
+#define OMAP24XX_IC_BASE        (L4_24XX_BASE + 0xfe000)
 #define VA_IC_BASE              IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP24XX_IVA_INTC_BASE  0x40000000
 #define IRQ_SIR_IRQ             0x0040
+#define OMAP24XX_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
+#define OMAP24XX_PRCM_BASE      (L4_24XX_BASE + 0x8000)
+#define OMAP24XX_SDRC_BASE      (L3_24XX_BASE + 0x9000)
 #endif /* __ASM_ARCH_OMAP24XX_H */
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h
new file mode 100644
index 000000000000..4ba2622cc142
--- /dev/null
+++ b/include/asm-arm/arch-omap/omapfb.h
@@ -0,0 +1,281 @@
+/*
+ * File: include/asm-arm/arch-omap/omapfb.h
+ *
+ * Framebuffer driver for TI OMAP boards
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __OMAPFB_H
+#define __OMAPFB_H
+/* IOCTL commands. */
+#define OMAP_IOW(num, dtype)    _IOW('O', num, dtype)
+#define OMAP_IOR(num, dtype)    _IOR('O', num, dtype)
+#define OMAP_IOWR(num, dtype)   _IOWR('O', num, dtype)
+#define OMAP_IO(num)            _IO('O', num)
+#define OMAPFB_MIRROR           OMAP_IOW(31, int)
+#define OMAPFB_SYNC_GFX         OMAP_IO(37)
+#define OMAPFB_VSYNC            OMAP_IO(38)
+#define OMAPFB_SET_UPDATE_MODE  OMAP_IOW(40, enum omapfb_update_mode)
+#define OMAPFB_GET_CAPS         OMAP_IOR(42, unsigned long)
+#define OMAPFB_GET_UPDATE_MODE  OMAP_IOW(43, enum omapfb_update_mode)
+#define OMAPFB_LCD_TEST         OMAP_IOW(45, int)
+#define OMAPFB_CTRL_TEST        OMAP_IOW(46, int)
+#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(47, struct omapfb_update_window)
+#define OMAPFB_SETUP_PLANE      OMAP_IOW(48, struct omapfb_setup_plane)
+#define OMAPFB_ENABLE_PLANE     OMAP_IOW(49, struct omapfb_enable_plane)
+#define OMAPFB_SET_COLOR_KEY    OMAP_IOW(50, struct omapfb_color_key)
+#define OMAPFB_CAPS_GENERIC_MASK        0x00000fff
+#define OMAPFB_CAPS_LCDC_MASK           0x00fff000
+#define OMAPFB_CAPS_PANEL_MASK          0xff000000
+#define OMAPFB_CAPS_MANUAL_UPDATE       0x00001000
+#define OMAPFB_CAPS_SET_BACKLIGHT       0x01000000
+/* Values from DSP must map to lower 16-bits */
+#define OMAPFB_FORMAT_MASK         0x00ff
+#define OMAPFB_FORMAT_FLAG_DOUBLE  0x0100
+enum omapfb_color_format {
+        OMAPFB_COLOR_RGB565 = 0,
+        OMAPFB_COLOR_YUV422,
+        OMAPFB_COLOR_YUV420,
+        OMAPFB_COLOR_CLUT_8BPP,
+        OMAPFB_COLOR_CLUT_4BPP,
+        OMAPFB_COLOR_CLUT_2BPP,
+        OMAPFB_COLOR_CLUT_1BPP,
+};
+struct omapfb_update_window {
+        u32 x, y;
+        u32 width, height;
+        u32 format;
+};
+enum omapfb_plane {
+        OMAPFB_PLANE_GFX = 0,
+        OMAPFB_PLANE_VID1,
+        OMAPFB_PLANE_VID2,
+};
+enum omapfb_channel_out {
+        OMAPFB_CHANNEL_OUT_LCD = 0,
+        OMAPFB_CHANNEL_OUT_DIGIT,
+};
+struct omapfb_setup_plane {
+        u8  plane;
+        u8  channel_out;
+        u32 offset;
+        u32 pos_x, pos_y;
+        u32 width, height;
+        u32 color_mode;
+};
+struct omapfb_enable_plane {
+        u8  plane;
+        u8  enable;
+};
+enum omapfb_color_key_type {
+        OMAPFB_COLOR_KEY_DISABLED = 0,
+        OMAPFB_COLOR_KEY_GFX_DST,
+        OMAPFB_COLOR_KEY_VID_SRC,
+};
+struct omapfb_color_key {
+        u8  channel_out;
+        u32 background;
+        u32 trans_key;
+        u8  key_type;
+};
+enum omapfb_update_mode {
+        OMAPFB_UPDATE_DISABLED = 0,
+        OMAPFB_AUTO_UPDATE,
+        OMAPFB_MANUAL_UPDATE
+};
+#ifdef __KERNEL__
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#define OMAP_LCDC_INV_VSYNC             0x0001
+#define OMAP_LCDC_INV_HSYNC             0x0002
+#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
+#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
+#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
+#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
+#define OMAP_LCDC_SIGNAL_MASK           0x003f
+#define OMAP_LCDC_PANEL_TFT             0x0100
+#ifdef CONFIG_ARCH_OMAP1
+#define OMAPFB_PLANE_NUM                1
+#else
+#define OMAPFB_PLANE_NUM                3
+#endif
+struct omapfb_device;
+struct lcd_panel {
+        const char      *name;
+        int             config;         /* TFT/STN, signal inversion */
+        int             bpp;            /* Pixel format in fb mem */
+        int             data_lines;     /* Lines on LCD HW interface */
+        int             x_res, y_res;
+        int             pixel_clock;    /* In kHz */
+        int             hsw;            /* Horizontal synchronization
+                                           pulse width */
+        int             hfp;            /* Horizontal front porch */
+        int             hbp;            /* Horizontal back porch */
+        int             vsw;            /* Vertical synchronization
+                                           pulse width */
+        int             vfp;            /* Vertical front porch */
+        int             vbp;            /* Vertical back porch */
+        int             acb;            /* ac-bias pin frequency */
+        int             pcd;            /* pixel clock divider.
+                                           Obsolete use pixel_clock instead */
+        int             (*init)         (struct omapfb_device *fbdev);
+        void            (*cleanup)      (void);
+        int             (*enable)       (void);
+        void            (*disable)      (void);
+        unsigned long   (*get_caps)     (void);
+        int             (*set_bklight_level)(unsigned int level);
+        unsigned int    (*get_bklight_level)(void);
+        unsigned int    (*get_bklight_max)  (void);
+        int             (*run_test)     (int test_num);
+};
+struct omapfb_device;
+struct extif_timings {
+        int cs_on_time;
+        int cs_off_time;
+        int we_on_time;
+        int we_off_time;
+        int re_on_time;
+        int re_off_time;
+        int we_cycle_time;
+        int re_cycle_time;
+        int cs_pulse_width;
+        int access_time;
+};
+struct lcd_ctrl_extif {
+        int  (*init)            (void);
+        void (*cleanup)         (void);
+        void (*set_timings)     (const struct extif_timings *timings);
+        void (*write_command)   (u32 cmd);
+        u32  (*read_data)       (void);
+        void (*write_data)      (u32 data);
+        void (*transfer_area)   (int width, int height,
+                                 void (callback)(void * data), void *data);
+};
+struct lcd_ctrl {
+        const char      *name;
+        void            *data;
+        int             (*init)           (struct omapfb_device *fbdev,
+                                           int ext_mode, int req_vram_size);
+        void            (*cleanup)        (void);
+        void            (*get_vram_layout)(unsigned long *size,
+                                           void **virt_base,
+                                           dma_addr_t *phys_base);
+        unsigned long   (*get_caps)       (void);
+        int             (*set_update_mode)(enum omapfb_update_mode mode);
+        enum omapfb_update_mode (*get_update_mode)(void);
+        int             (*setup_plane)    (int plane, int channel_out,
+                                           unsigned long offset,
+                                           int screen_width,
+                                           int pos_x, int pos_y, int width,
+                                           int height, int color_mode);
+        int             (*enable_plane)   (int plane, int enable);
+        int             (*update_window)  (struct omapfb_update_window *win,
+                                           void (*callback)(void *),
+                                           void *callback_data);
+        void            (*sync)           (void);
+        void            (*suspend)        (void);
+        void            (*resume)         (void);
+        int             (*run_test)       (int test_num);
+        int             (*setcolreg)      (u_int regno, u16 red, u16 green,
+                                           u16 blue, u16 transp,
+                                           int update_hw_mem);
+        int             (*set_color_key)  (struct omapfb_color_key *ck);
+};
+enum omapfb_state {
+        OMAPFB_DISABLED = 0,
+        OMAPFB_SUSPENDED= 99,
+        OMAPFB_ACTIVE   = 100
+};
+struct omapfb_device {
+        int                     state;
+        int                     ext_lcdc;               /* Using external
+                                                           LCD controller */
+        struct semaphore        rqueue_sema;
+        void                    *vram_virt_base;
+        dma_addr_t              vram_phys_base;
+        unsigned long           vram_size;
+        int                     color_mode;
+        int                     palette_size;
+        int                     mirror;
+        u32                     pseudo_palette[17];
+        struct lcd_panel        *panel;                 /* LCD panel */
+        struct lcd_ctrl         *ctrl;                  /* LCD controller */
+        struct lcd_ctrl         *int_ctrl;              /* internal LCD ctrl */
+        struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
+                                                           interface */
+        struct fb_info          *fb_info;
+        struct device           *dev;
+};
+extern struct lcd_panel h3_panel;
+extern struct lcd_panel h2_panel;
+extern struct lcd_panel p2_panel;
+extern struct lcd_panel osk_panel;
+extern struct lcd_panel innovator1610_panel;
+extern struct lcd_panel innovator1510_panel;
+#ifdef CONFIG_ARCH_OMAP1
+extern struct lcd_ctrl omap1_lcd_ctrl;
+#else
+extern struct lcd_ctrl omap2_disp_ctrl;
+#endif
+extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
+#endif /* __KERNEL__ */
+#endif /* __OMAPFB_H */
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
index fbd742d0c499..7c790425e363 100644
--- a/include/asm-arm/arch-omap/pm.h
+++ b/include/asm-arm/arch-omap/pm.h
@@ -98,7 +98,14 @@
 #define OMAP1610_IDLECT3                0xfffece24
 #define OMAP1610_IDLE_LOOP_REQUEST      0x0400
-#if     !defined(CONFIG_ARCH_OMAP1510) && \
+#define OMAP730_IDLECT1_SLEEP_VAL       0x16c7
+#define OMAP730_IDLECT2_SLEEP_VAL       0x09c7
+#define OMAP730_IDLECT3_VAL             0x3f
+#define OMAP730_IDLECT3         0xfffece24
+#define OMAP730_IDLE_LOOP_REQUEST       0x0C00
+#if     !defined(CONFIG_ARCH_OMAP730) && \
+        !defined(CONFIG_ARCH_OMAP15XX) && \
        !defined(CONFIG_ARCH_OMAP16XX) && \
        !defined(CONFIG_ARCH_OMAP24XX)
 #error "Power management for this processor not implemented yet"
@@ -107,8 +114,10 @@
 #ifndef __ASSEMBLER__
 extern void omap_pm_idle(void);
 extern void omap_pm_suspend(void);
+extern void omap730_cpu_suspend(unsigned short, unsigned short);
 extern void omap1510_cpu_suspend(unsigned short, unsigned short);
 extern void omap1610_cpu_suspend(unsigned short, unsigned short);
+extern void omap730_idle_loop_suspend(void);
 extern void omap1510_idle_loop_suspend(void);
 extern void omap1610_idle_loop_suspend(void);
@@ -118,6 +127,8 @@ extern void omap_serial_wake_trigger(int enable);
 #define omap_serial_wake_trigger(x)     {}
 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
+extern unsigned int omap730_cpu_suspend_sz;
+extern unsigned int omap730_idle_loop_suspend_sz;
 extern unsigned int omap1510_cpu_suspend_sz;
 extern unsigned int omap1510_idle_loop_suspend_sz;
 extern unsigned int omap1610_cpu_suspend_sz;
@@ -131,6 +142,10 @@ extern unsigned int omap1610_idle_loop_suspend_sz;
 #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
+#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
+#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
+#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
 #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
 #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
 #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
@@ -188,13 +203,34 @@ enum mpui1510_save_state {
        MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
        MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
        MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
-#if defined(CONFIG_ARCH_OMAP1510)
+#if defined(CONFIG_ARCH_OMAP15XX)
        MPUI1510_SLEEP_SAVE_SIZE
 #else
        MPUI1510_SLEEP_SAVE_SIZE = 0
 #endif
 };
+enum mpui730_save_state {
+        MPUI730_SLEEP_SAVE_START = 0,
+        /*
+         * MPUI registers 32 bits
+         */
+        MPUI730_SLEEP_SAVE_MPUI_CTRL,
+        MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+        MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
+        MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
+        MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
+        MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
+        MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
+        MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
+        MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
+#if defined(CONFIG_ARCH_OMAP730)
+        MPUI730_SLEEP_SAVE_SIZE
+#else
+        MPUI730_SLEEP_SAVE_SIZE = 0
+#endif
+};
 enum mpui1610_save_state {
        MPUI1610_SLEEP_SAVE_START = 0,
        /*
diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h
new file mode 100644
index 000000000000..7b48a5cbb15f
--- /dev/null
+++ b/include/asm-arm/arch-omap/prcm.h
@@ -0,0 +1,429 @@
+/*
+ * prcm.h - Access definations for use in OMAP24XX clock and power management
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
+#define __ASM_ARM_ARCH_DPM_PRCM_H
+/* SET_PERFORMANCE_LEVEL PARAMETERS */
+#define PRCM_HALF_SPEED 1
+#define PRCM_FULL_SPEED 2
+#ifndef __ASSEMBLER__
+#define PRCM_REG32(offset)      __REG32(OMAP24XX_PRCM_BASE + (offset))
+#define PRCM_REVISION           PRCM_REG32(0x000)
+#define PRCM_SYSCONFIG          PRCM_REG32(0x010)
+#define PRCM_IRQSTATUS_MPU      PRCM_REG32(0x018)
+#define PRCM_IRQENABLE_MPU      PRCM_REG32(0x01C)
+#define PRCM_VOLTCTRL           PRCM_REG32(0x050)
+#define PRCM_VOLTST             PRCM_REG32(0x054)
+#define PRCM_CLKSRC_CTRL        PRCM_REG32(0x060)
+#define PRCM_CLKOUT_CTRL        PRCM_REG32(0x070)
+#define PRCM_CLKEMUL_CTRL       PRCM_REG32(0x078)
+#define PRCM_CLKCFG_CTRL        PRCM_REG32(0x080)
+#define PRCM_CLKCFG_STATUS      PRCM_REG32(0x084)
+#define PRCM_VOLTSETUP          PRCM_REG32(0x090)
+#define PRCM_CLKSSETUP          PRCM_REG32(0x094)
+#define PRCM_POLCTRL            PRCM_REG32(0x098)
+/* GENERAL PURPOSE */
+#define GENERAL_PURPOSE1        PRCM_REG32(0x0B0)
+#define GENERAL_PURPOSE2        PRCM_REG32(0x0B4)
+#define GENERAL_PURPOSE3        PRCM_REG32(0x0B8)
+#define GENERAL_PURPOSE4        PRCM_REG32(0x0BC)
+#define GENERAL_PURPOSE5        PRCM_REG32(0x0C0)
+#define GENERAL_PURPOSE6        PRCM_REG32(0x0C4)
+#define GENERAL_PURPOSE7        PRCM_REG32(0x0C8)
+#define GENERAL_PURPOSE8        PRCM_REG32(0x0CC)
+#define GENERAL_PURPOSE9        PRCM_REG32(0x0D0)
+#define GENERAL_PURPOSE10       PRCM_REG32(0x0D4)
+#define GENERAL_PURPOSE11       PRCM_REG32(0x0D8)
+#define GENERAL_PURPOSE12       PRCM_REG32(0x0DC)
+#define GENERAL_PURPOSE13       PRCM_REG32(0x0E0)
+#define GENERAL_PURPOSE14       PRCM_REG32(0x0E4)
+#define GENERAL_PURPOSE15       PRCM_REG32(0x0E8)
+#define GENERAL_PURPOSE16       PRCM_REG32(0x0EC)
+#define GENERAL_PURPOSE17       PRCM_REG32(0x0F0)
+#define GENERAL_PURPOSE18       PRCM_REG32(0x0F4)
+#define GENERAL_PURPOSE19       PRCM_REG32(0x0F8)
+#define GENERAL_PURPOSE20       PRCM_REG32(0x0FC)
+/* MPU */
+#define CM_CLKSEL_MPU           PRCM_REG32(0x140)
+#define CM_CLKSTCTRL_MPU        PRCM_REG32(0x148)
+#define RM_RSTST_MPU            PRCM_REG32(0x158)
+#define PM_WKDEP_MPU            PRCM_REG32(0x1C8)
+#define PM_EVGENCTRL_MPU        PRCM_REG32(0x1D4)
+#define PM_EVEGENONTIM_MPU      PRCM_REG32(0x1D8)
+#define PM_EVEGENOFFTIM_MPU     PRCM_REG32(0x1DC)
+#define PM_PWSTCTRL_MPU         PRCM_REG32(0x1E0)
+#define PM_PWSTST_MPU           PRCM_REG32(0x1E4)
+/* CORE */
+#define CM_FCLKEN1_CORE         PRCM_REG32(0x200)
+#define CM_FCLKEN2_CORE         PRCM_REG32(0x204)
+#define CM_FCLKEN3_CORE         PRCM_REG32(0x208)
+#define CM_ICLKEN1_CORE         PRCM_REG32(0x210)
+#define CM_ICLKEN2_CORE         PRCM_REG32(0x214)
+#define CM_ICLKEN3_CORE         PRCM_REG32(0x218)
+#define CM_ICLKEN4_CORE         PRCM_REG32(0x21C)
+#define CM_IDLEST1_CORE         PRCM_REG32(0x220)
+#define CM_IDLEST2_CORE         PRCM_REG32(0x224)
+#define CM_IDLEST3_CORE         PRCM_REG32(0x228)
+#define CM_IDLEST4_CORE         PRCM_REG32(0x22C)
+#define CM_AUTOIDLE1_CORE       PRCM_REG32(0x230)
+#define CM_AUTOIDLE2_CORE       PRCM_REG32(0x234)
+#define CM_AUTOIDLE3_CORE       PRCM_REG32(0x238)
+#define CM_AUTOIDLE4_CORE       PRCM_REG32(0x23C)
+#define CM_CLKSEL1_CORE         PRCM_REG32(0x240)
+#define CM_CLKSEL2_CORE         PRCM_REG32(0x244)
+#define CM_CLKSTCTRL_CORE       PRCM_REG32(0x248)
+#define PM_WKEN1_CORE           PRCM_REG32(0x2A0)
+#define PM_WKEN2_CORE           PRCM_REG32(0x2A4)
+#define PM_WKST1_CORE           PRCM_REG32(0x2B0)
+#define PM_WKST2_CORE           PRCM_REG32(0x2B4)
+#define PM_WKDEP_CORE           PRCM_REG32(0x2C8)
+#define PM_PWSTCTRL_CORE        PRCM_REG32(0x2E0)
+#define PM_PWSTST_CORE          PRCM_REG32(0x2E4)
+/* GFX */
+#define CM_FCLKEN_GFX           PRCM_REG32(0x300)
+#define CM_ICLKEN_GFX           PRCM_REG32(0x310)
+#define CM_IDLEST_GFX           PRCM_REG32(0x320)
+#define CM_CLKSEL_GFX           PRCM_REG32(0x340)
+#define CM_CLKSTCTRL_GFX        PRCM_REG32(0x348)
+#define RM_RSTCTRL_GFX          PRCM_REG32(0x350)
+#define RM_RSTST_GFX            PRCM_REG32(0x358)
+#define PM_WKDEP_GFX            PRCM_REG32(0x3C8)
+#define PM_PWSTCTRL_GFX         PRCM_REG32(0x3E0)
+#define PM_PWSTST_GFX           PRCM_REG32(0x3E4)
+/* WAKE-UP */
+#define CM_FCLKEN_WKUP          PRCM_REG32(0x400)
+#define CM_ICLKEN_WKUP          PRCM_REG32(0x410)
+#define CM_IDLEST_WKUP          PRCM_REG32(0x420)
+#define CM_AUTOIDLE_WKUP        PRCM_REG32(0x430)
+#define CM_CLKSEL_WKUP          PRCM_REG32(0x440)
+#define RM_RSTCTRL_WKUP         PRCM_REG32(0x450)
+#define RM_RSTTIME_WKUP         PRCM_REG32(0x454)
+#define RM_RSTST_WKUP           PRCM_REG32(0x458)
+#define PM_WKEN_WKUP            PRCM_REG32(0x4A0)
+#define PM_WKST_WKUP            PRCM_REG32(0x4B0)
+/* CLOCKS */
+#define CM_CLKEN_PLL            PRCM_REG32(0x500)
+#define CM_IDLEST_CKGEN         PRCM_REG32(0x520)
+#define CM_AUTOIDLE_PLL         PRCM_REG32(0x530)
+#define CM_CLKSEL1_PLL          PRCM_REG32(0x540)
+#define CM_CLKSEL2_PLL          PRCM_REG32(0x544)
+/* DSP */
+#define CM_FCLKEN_DSP           PRCM_REG32(0x800)
+#define CM_ICLKEN_DSP           PRCM_REG32(0x810)
+#define CM_IDLEST_DSP           PRCM_REG32(0x820)
+#define CM_AUTOIDLE_DSP         PRCM_REG32(0x830)
+#define CM_CLKSEL_DSP           PRCM_REG32(0x840)
+#define CM_CLKSTCTRL_DSP        PRCM_REG32(0x848)
+#define RM_RSTCTRL_DSP          PRCM_REG32(0x850)
+#define RM_RSTST_DSP            PRCM_REG32(0x858)
+#define PM_WKEN_DSP             PRCM_REG32(0x8A0)
+#define PM_WKDEP_DSP            PRCM_REG32(0x8C8)
+#define PM_PWSTCTRL_DSP         PRCM_REG32(0x8E0)
+#define PM_PWSTST_DSP           PRCM_REG32(0x8E4)
+#define PRCM_IRQSTATUS_DSP      PRCM_REG32(0x8F0)
+#define PRCM_IRQENABLE_DSP      PRCM_REG32(0x8F4)
+/* IVA */
+#define PRCM_IRQSTATUS_IVA      PRCM_REG32(0x8F8)
+#define PRCM_IRQENABLE_IVA      PRCM_REG32(0x8FC)
+/* Modem on 2430 */
+#define CM_FCLKEN_MDM           PRCM_REG32(0xC00)
+#define CM_ICLKEN_MDM           PRCM_REG32(0xC10)
+#define CM_IDLEST_MDM           PRCM_REG32(0xC20)
+#define CM_CLKSEL_MDM           PRCM_REG32(0xC40)
+/* FIXME: Move to header for 2430 */
+#define DISP_BASE               (OMAP24XX_L4_IO_BASE+0x50000)
+#define DISP_REG32(offset)      __REG32(DISP_BASE + (offset))
+#define OMAP24XX_GPMC_BASE      (L3_24XX_BASE + 0xa000)
+#define GPMC_BASE               (OMAP24XX_GPMC_BASE)
+#define GPMC_REG32(offset)      __REG32(GPMC_BASE + (offset))
+#define GPT1_BASE               (OMAP24XX_GPT1)
+#define GPT1_REG32(offset)      __REG32(GPT1_BASE + (offset))
+/* Misc sysconfig */
+#define DISPC_SYSCONFIG         DISP_REG32(0x410)
+#define SPI_BASE                (OMAP24XX_L4_IO_BASE+0x98000)
+#define MCSPI1_SYSCONFIG        __REG32(SPI_BASE + 0x10)
+#define MCSPI2_SYSCONFIG        __REG32(SPI_BASE+0x2000 + 0x10)
+//#define DSP_MMU_SYSCONFIG     0x5A000010
+#define CAMERA_MMU_SYSCONFIG    __REG32(DISP_BASE+0x2C10)
+//#define IVA_MMU_SYSCONFIG     0x5D000010
+//#define DSP_DMA_SYSCONFIG     0x00FCC02C
+#define CAMERA_DMA_SYSCONFIG    __REG32(DISP_BASE+0x282C)
+#define SYSTEM_DMA_SYSCONFIG    __REG32(DISP_BASE+0x602C)
+#define GPMC_SYSCONFIG          GPMC_REG32(0x010)
+#define MAILBOXES_SYSCONFIG     __REG32(OMAP24XX_L4_IO_BASE+0x94010)
+#define UART1_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
+#define UART2_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
+#define UART3_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
+//#define IVA_SYSCONFIG         0x5C060010
+#define SDRC_SYSCONFIG          __REG32(OMAP24XX_SDRC_BASE+0x10)
+#define SMS_SYSCONFIG           __REG32(OMAP24XX_SMS_BASE+0x10)
+#define SSI_SYSCONFIG           __REG32(DISP_BASE+0x8010)
+//#define VLYNQ_SYSCONFIG       0x67FFFE10
+/* rkw - good cannidates for PM_ to start what nm was trying */
+#define OMAP24XX_GPT2           (OMAP24XX_L4_IO_BASE+0x2A000)
+#define OMAP24XX_GPT3           (OMAP24XX_L4_IO_BASE+0x78000)
+#define OMAP24XX_GPT4           (OMAP24XX_L4_IO_BASE+0x7A000)
+#define OMAP24XX_GPT5           (OMAP24XX_L4_IO_BASE+0x7C000)
+#define OMAP24XX_GPT6           (OMAP24XX_L4_IO_BASE+0x7E000)
+#define OMAP24XX_GPT7           (OMAP24XX_L4_IO_BASE+0x80000)
+#define OMAP24XX_GPT8           (OMAP24XX_L4_IO_BASE+0x82000)
+#define OMAP24XX_GPT9           (OMAP24XX_L4_IO_BASE+0x84000)
+#define OMAP24XX_GPT10          (OMAP24XX_L4_IO_BASE+0x86000)
+#define OMAP24XX_GPT11          (OMAP24XX_L4_IO_BASE+0x88000)
+#define OMAP24XX_GPT12          (OMAP24XX_L4_IO_BASE+0x8A000)
+#define GPTIMER1_SYSCONFIG      GPT1_REG32(0x010)
+#define GPTIMER2_SYSCONFIG      __REG32(OMAP24XX_GPT2 + 0x10)
+#define GPTIMER3_SYSCONFIG      __REG32(OMAP24XX_GPT3 + 0x10)
+#define GPTIMER4_SYSCONFIG      __REG32(OMAP24XX_GPT4 + 0x10)
+#define GPTIMER5_SYSCONFIG      __REG32(OMAP24XX_GPT5 + 0x10)
+#define GPTIMER6_SYSCONFIG      __REG32(OMAP24XX_GPT6 + 0x10)
+#define GPTIMER7_SYSCONFIG      __REG32(OMAP24XX_GPT7 + 0x10)
+#define GPTIMER8_SYSCONFIG      __REG32(OMAP24XX_GPT8 + 0x10)
+#define GPTIMER9_SYSCONFIG      __REG32(OMAP24XX_GPT9 + 0x10)
+#define GPTIMER10_SYSCONFIG     __REG32(OMAP24XX_GPT10 + 0x10)
+#define GPTIMER11_SYSCONFIG     __REG32(OMAP24XX_GPT11 + 0x10)
+#define GPTIMER12_SYSCONFIG     __REG32(OMAP24XX_GPT12 + 0x10)
+#define GPIOX_BASE(X)           (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
+#define GPIO1_SYSCONFIG         __REG32((GPIOX_BASE(1)+0x10))
+#define GPIO2_SYSCONFIG         __REG32((GPIOX_BASE(2)+0x10))
+#define GPIO3_SYSCONFIG         __REG32((GPIOX_BASE(3)+0x10))
+#define GPIO4_SYSCONFIG         __REG32((GPIOX_BASE(4)+0x10))
+/* GP TIMER 1 */
+#define GPTIMER1_TISTAT         GPT1_REG32(0x014)
+#define GPTIMER1_TISR           GPT1_REG32(0x018)
+#define GPTIMER1_TIER           GPT1_REG32(0x01C)
+#define GPTIMER1_TWER           GPT1_REG32(0x020)
+#define GPTIMER1_TCLR           GPT1_REG32(0x024)
+#define GPTIMER1_TCRR           GPT1_REG32(0x028)
+#define GPTIMER1_TLDR           GPT1_REG32(0x02C)
+#define GPTIMER1_TTGR           GPT1_REG32(0x030)
+#define GPTIMER1_TWPS           GPT1_REG32(0x034)
+#define GPTIMER1_TMAR           GPT1_REG32(0x038)
+#define GPTIMER1_TCAR1          GPT1_REG32(0x03C)
+#define GPTIMER1_TSICR          GPT1_REG32(0x040)
+#define GPTIMER1_TCAR2          GPT1_REG32(0x044)
+/* rkw -- base fix up please... */
+#define GPTIMER3_TISR           __REG32(OMAP24XX_L4_IO_BASE+0x78018)
+/* SDRC */
+#define SDRC_DLLA_CTRL          __REG32(OMAP24XX_SDRC_BASE+0x060)
+#define SDRC_DLLA_STATUS        __REG32(OMAP24XX_SDRC_BASE+0x064)
+#define SDRC_DLLB_CTRL          __REG32(OMAP24XX_SDRC_BASE+0x068)
+#define SDRC_DLLB_STATUS        __REG32(OMAP24XX_SDRC_BASE+0x06C)
+#define SDRC_POWER              __REG32(OMAP24XX_SDRC_BASE+0x070)
+#define SDRC_MR_0               __REG32(OMAP24XX_SDRC_BASE+0x084)
+/* GPIO 1 */
+#define GPIO1_BASE              GPIOX_BASE(1)
+#define GPIO1_REG32(offset)     __REG32(GPIO1_BASE + (offset))
+#define GPIO1_IRQENABLE1        GPIO1_REG32(0x01C)
+#define GPIO1_IRQSTATUS1        GPIO1_REG32(0x018)
+#define GPIO1_IRQENABLE2        GPIO1_REG32(0x02C)
+#define GPIO1_IRQSTATUS2        GPIO1_REG32(0x028)
+#define GPIO1_WAKEUPENABLE      GPIO1_REG32(0x020)
+#define GPIO1_RISINGDETECT      GPIO1_REG32(0x048)
+#define GPIO1_DATAIN            GPIO1_REG32(0x038)
+#define GPIO1_OE                GPIO1_REG32(0x034)
+#define GPIO1_DATAOUT           GPIO1_REG32(0x03C)
+/* GPIO2 */
+#define GPIO2_BASE              GPIOX_BASE(2)
+#define GPIO2_REG32(offset)     __REG32(GPIO2_BASE + (offset))
+#define GPIO2_IRQENABLE1        GPIO2_REG32(0x01C)
+#define GPIO2_IRQSTATUS1        GPIO2_REG32(0x018)
+#define GPIO2_IRQENABLE2        GPIO2_REG32(0x02C)
+#define GPIO2_IRQSTATUS2        GPIO2_REG32(0x028)
+#define GPIO2_WAKEUPENABLE      GPIO2_REG32(0x020)
+#define GPIO2_RISINGDETECT      GPIO2_REG32(0x048)
+#define GPIO2_DATAIN            GPIO2_REG32(0x038)
+#define GPIO2_OE                GPIO2_REG32(0x034)
+#define GPIO2_DATAOUT           GPIO2_REG32(0x03C)
+/* GPIO 3 */
+#define GPIO3_BASE              GPIOX_BASE(3)
+#define GPIO3_REG32(offset)     __REG32(GPIO3_BASE + (offset))
+#define GPIO3_IRQENABLE1        GPIO3_REG32(0x01C)
+#define GPIO3_IRQSTATUS1        GPIO3_REG32(0x018)
+#define GPIO3_IRQENABLE2        GPIO3_REG32(0x02C)
+#define GPIO3_IRQSTATUS2        GPIO3_REG32(0x028)
+#define GPIO3_WAKEUPENABLE      GPIO3_REG32(0x020)
+#define GPIO3_RISINGDETECT      GPIO3_REG32(0x048)
+#define GPIO3_FALLINGDETECT     GPIO3_REG32(0x04C)
+#define GPIO3_DATAIN            GPIO3_REG32(0x038)
+#define GPIO3_OE                GPIO3_REG32(0x034)
+#define GPIO3_DATAOUT           GPIO3_REG32(0x03C)
+#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
+#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
+/* GPIO 4 */
+#define GPIO4_BASE              GPIOX_BASE(4)
+#define GPIO4_REG32(offset)     __REG32(GPIO4_BASE + (offset))
+#define GPIO4_IRQENABLE1        GPIO4_REG32(0x01C)
+#define GPIO4_IRQSTATUS1        GPIO4_REG32(0x018)
+#define GPIO4_IRQENABLE2        GPIO4_REG32(0x02C)
+#define GPIO4_IRQSTATUS2        GPIO4_REG32(0x028)
+#define GPIO4_WAKEUPENABLE      GPIO4_REG32(0x020)
+#define GPIO4_RISINGDETECT      GPIO4_REG32(0x048)
+#define GPIO4_FALLINGDETECT     GPIO4_REG32(0x04C)
+#define GPIO4_DATAIN            GPIO4_REG32(0x038)
+#define GPIO4_OE                GPIO4_REG32(0x034)
+#define GPIO4_DATAOUT           GPIO4_REG32(0x03C)
+#define GPIO4_DEBOUNCENABLE     GPIO4_REG32(0x050)
+#define GPIO4_DEBOUNCINGTIME    GPIO4_REG32(0x054)
+/* IO CONFIG */
+#define CONTROL_BASE            (OMAP24XX_CTRL_BASE)
+#define CONTROL_REG32(offset)   __REG32(CONTROL_BASE + (offset))
+#define CONTROL_PADCONF_SPI1_NCS2       CONTROL_REG32(0x104)
+#define CONTROL_PADCONF_SYS_XTALOUT     CONTROL_REG32(0x134)
+#define CONTROL_PADCONF_UART1_RX        CONTROL_REG32(0x0C8)
+#define CONTROL_PADCONF_MCBSP1_DX       CONTROL_REG32(0x10C)
+#define CONTROL_PADCONF_GPMC_NCS4       CONTROL_REG32(0x090)
+#define CONTROL_PADCONF_DSS_D5          CONTROL_REG32(0x0B8)
+#define CONTROL_PADCONF_DSS_D9          CONTROL_REG32(0x0BC)
+#define CONTROL_PADCONF_DSS_D13         CONTROL_REG32(0x0C0)
+#define CONTROL_PADCONF_DSS_VSYNC       CONTROL_REG32(0x0CC)
+/* CONTROL */
+#define CONTROL_DEVCONF         CONTROL_REG32(0x274)
+/* INTERRUPT CONTROLLER */
+#define INTC_BASE               (OMAP24XX_L4_IO_BASE+0xfe000)
+#define INTC_REG32(offset)      __REG32(INTC_BASE + (offset))
+#define INTC1_U_BASE            INTC_REG32(0x000)
+#define INTC_MIR0               INTC_REG32(0x084)
+#define INTC_MIR_SET0           INTC_REG32(0x08C)
+#define INTC_MIR_CLEAR0         INTC_REG32(0x088)
+#define INTC_ISR_CLEAR0         INTC_REG32(0x094)
+#define INTC_MIR1               INTC_REG32(0x0A4)
+#define INTC_MIR_SET1           INTC_REG32(0x0AC)
+#define INTC_MIR_CLEAR1         INTC_REG32(0x0A8)
+#define INTC_ISR_CLEAR1         INTC_REG32(0x0B4)
+#define INTC_MIR2               INTC_REG32(0x0C4)
+#define INTC_MIR_SET2           INTC_REG32(0x0CC)
+#define INTC_MIR_CLEAR2         INTC_REG32(0x0C8)
+#define INTC_ISR_CLEAR2         INTC_REG32(0x0D4)
+#define INTC_SIR_IRQ            INTC_REG32(0x040)
+#define INTC_CONTROL            INTC_REG32(0x048)
+#define INTC_ILR11              INTC_REG32(0x12C)
+#define INTC_ILR32              INTC_REG32(0x180)
+#define INTC_ILR37              INTC_REG32(0x194)
+#define INTC_SYSCONFIG          INTC_REG32(0x010)
+/* RAM FIREWALL */
+#define RAMFW_BASE              (0x68005000)
+#define RAMFW_REG32(offset)     __REG32(RAMFW_BASE + (offset))
+#define RAMFW_REQINFOPERM0      RAMFW_REG32(0x048)
+#define RAMFW_READPERM0         RAMFW_REG32(0x050)
+#define RAMFW_WRITEPERM0        RAMFW_REG32(0x058)
+/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
+//#define DEBUG_BOARD_LED_REGISTER 0x04000014
+/* GPMC CS0 */
+#define GPMC_CONFIG1_0          GPMC_REG32(0x060)
+#define GPMC_CONFIG2_0          GPMC_REG32(0x064)
+#define GPMC_CONFIG3_0          GPMC_REG32(0x068)
+#define GPMC_CONFIG4_0          GPMC_REG32(0x06C)
+#define GPMC_CONFIG5_0          GPMC_REG32(0x070)
+#define GPMC_CONFIG6_0          GPMC_REG32(0x074)
+#define GPMC_CONFIG7_0          GPMC_REG32(0x078)
+/* GPMC CS1 */
+#define GPMC_CONFIG1_1          GPMC_REG32(0x090)
+#define GPMC_CONFIG2_1          GPMC_REG32(0x094)
+#define GPMC_CONFIG3_1          GPMC_REG32(0x098)
+#define GPMC_CONFIG4_1          GPMC_REG32(0x09C)
+#define GPMC_CONFIG5_1          GPMC_REG32(0x0a0)
+#define GPMC_CONFIG6_1          GPMC_REG32(0x0a4)
+#define GPMC_CONFIG7_1          GPMC_REG32(0x0a8)
+/* DSS */
+#define DSS_CONTROL             DISP_REG32(0x040)
+#define DISPC_CONTROL           DISP_REG32(0x440)
+#define DISPC_SYSSTATUS         DISP_REG32(0x414)
+#define DISPC_IRQSTATUS         DISP_REG32(0x418)
+#define DISPC_IRQENABLE         DISP_REG32(0x41C)
+#define DISPC_CONFIG            DISP_REG32(0x444)
+#define DISPC_DEFAULT_COLOR0    DISP_REG32(0x44C)
+#define DISPC_DEFAULT_COLOR1    DISP_REG32(0x450)
+#define DISPC_TRANS_COLOR0      DISP_REG32(0x454)
+#define DISPC_TRANS_COLOR1      DISP_REG32(0x458)
+#define DISPC_LINE_NUMBER       DISP_REG32(0x460)
+#define DISPC_TIMING_H          DISP_REG32(0x464)
+#define DISPC_TIMING_V          DISP_REG32(0x468)
+#define DISPC_POL_FREQ          DISP_REG32(0x46C)
+#define DISPC_DIVISOR           DISP_REG32(0x470)
+#define DISPC_SIZE_DIG          DISP_REG32(0x478)
+#define DISPC_SIZE_LCD          DISP_REG32(0x47C)
+#define DISPC_GFX_BA0           DISP_REG32(0x480)
+#define DISPC_GFX_BA1           DISP_REG32(0x484)
+#define DISPC_GFX_POSITION      DISP_REG32(0x488)
+#define DISPC_GFX_SIZE          DISP_REG32(0x48C)
+#define DISPC_GFX_ATTRIBUTES    DISP_REG32(0x4A0)
+#define DISPC_GFX_FIFO_THRESHOLD        DISP_REG32(0x4A4)
+#define DISPC_GFX_ROW_INC       DISP_REG32(0x4AC)
+#define DISPC_GFX_PIXEL_INC     DISP_REG32(0x4B0)
+#define DISPC_GFX_WINDOW_SKIP   DISP_REG32(0x4B4)
+#define DISPC_GFX_TABLE_BA      DISP_REG32(0x4B8)
+#define DISPC_DATA_CYCLE1       DISP_REG32(0x5D4)
+#define DISPC_DATA_CYCLE2       DISP_REG32(0x5D8)
+#define DISPC_DATA_CYCLE3       DISP_REG32(0x5DC)
+/* Wake up define for board */
+#define GPIO97                  (1 << 1)
+#define GPIO88                  (1 << 24)
+#endif /* __ASSEMBLER__ */
+#endif
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
new file mode 100644
index 000000000000..e72ccbf0fe06
--- /dev/null
+++ b/include/asm-arm/arch-omap/sram.h
@@ -0,0 +1,38 @@
+/*
+ * linux/include/asm-arm/arch-omap/sram.h
+ *
+ * Interface for functions that need to be run in internal SRAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_OMAP_SRAM_H
+#define __ARCH_ARM_OMAP_SRAM_H
+extern void * omap_sram_push(void * start, unsigned long size);
+extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
+extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                u32 base_cs, u32 force_unlock);
+extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                      u32 mem_type);
+extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+/* Do not use these */
+extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long sram_reprogram_clock_sz;
+extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                          u32 base_cs, u32 force_unlock);
+extern unsigned long sram_ddr_init_sz;
+extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+extern unsigned long sram_set_prcm_sz;
+extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type);
+extern unsigned long sram_reprogram_sdrc_sz;
+#endif
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index ff37bc27e603..9af415d2944a 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -6,18 +6,21 @@
 #define __ASM_ARCH_SYSTEM_H
 #include <linux/config.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <asm/hardware/clock.h>
-#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/arch/prcm.h>
+#ifndef CONFIG_MACH_VOICEBLUE
+#define voiceblue_reset()               do {} while (0)
+#endif
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode)
+static inline void omap1_arch_reset(char mode)
 {
-#ifdef CONFIG_ARCH_OMAP16XX
        /*
         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
         * "Global Software Reset Affects Traffic Controller Frequency".
@@ -27,13 +30,31 @@ static inline void arch_reset(char mode)
                                 DPLL_CTL);
                omap_writew(0x8, ARM_RSTCT1);
        }
-#endif
-#ifdef CONFIG_MACH_VOICEBLUE
        if (machine_is_voiceblue())
                voiceblue_reset();
        else
-#endif
                omap_writew(1, ARM_RSTCT1);
 }
+static inline void omap2_arch_reset(char mode)
+{
+        u32 rate;
+        struct clk *vclk, *sclk;
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);       /* go to bypass for OMAP limitation */
+        RM_RSTCTRL_WKUP |= 2;
+}
+static inline void arch_reset(char mode)
+{
+        if (!cpu_is_omap24xx())
+                omap1_arch_reset(mode);
+        else
+                omap2_arch_reset(mode);
+}
 #endif
diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h
index b61ddb491e83..21f2e367185a 100644
--- a/include/asm-arm/arch-omap/timex.h
+++ b/include/asm-arm/arch-omap/timex.h
@@ -28,6 +28,14 @@
 #if !defined(__ASM_ARCH_OMAP_TIMEX_H)
 #define __ASM_ARCH_OMAP_TIMEX_H
+/*
+ * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
+ * and that's why the CLOCK_TICK_RATE is not 32768.
+ */
+#ifdef CONFIG_OMAP_32K_TIMER
+#define CLOCK_TICK_RATE         (CONFIG_OMAP_32K_TIMER_HZ)
+#else
 #define CLOCK_TICK_RATE         (HZ * 100000UL)
+#endif
 #endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
index 3545c86859cc..c718264affbd 100644
--- a/include/asm-arm/arch-omap/uncompress.h
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -36,10 +36,14 @@ putstr(const char *s)
        volatile u8 * uart = 0;
        int shift = 2;
+#ifdef CONFIG_MACH_OMAP_PALMTE
+        return;
+#endif
 #ifdef CONFIG_ARCH_OMAP
 #ifdef  CONFIG_OMAP_LL_DEBUG_UART3
        uart = (volatile u8 *)(OMAP_UART3_BASE);
-#elif   CONFIG_OMAP_LL_DEBUG_UART2
+#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
        uart = (volatile u8 *)(OMAP_UART2_BASE);
 #else
        uart = (volatile u8 *)(OMAP_UART1_BASE);
diff --git a/include/asm-arm/arch-pxa/akita.h b/include/asm-arm/arch-pxa/akita.h
index 4a1fbcfccc39..5d8cc1d9cb10 100644
--- a/include/asm-arm/arch-pxa/akita.h
+++ b/include/asm-arm/arch-pxa/akita.h
@@ -25,6 +25,8 @@
 /* Default Values */
 #define AKITA_IOEXP_IO_OUT      (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
+extern struct platform_device akitaioexp_device;
 void akita_set_ioexp(struct device *dev, unsigned char bitmask);
 void akita_reset_ioexp(struct device *dev, unsigned char bitmask);
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index cf35721cfa45..3e70bd95472c 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -44,12 +44,12 @@
 #ifndef __ASSEMBLY__
-# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
+# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
 /* With indexed regs we don't want to feed the index through io_p2v()
   especially if it is a variable, otherwise horrible code will result. */
 # define __REG2(x,y)    \
-        (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
+        (*(volatile u32 *)((u32)&__REG(x) + (y)))
 # define __PREG(x)      (io_v2p((u32)&(x)))
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
index c3bdbe44e21f..eb2dd58d397f 100644
--- a/include/asm-arm/arch-pxa/io.h
+++ b/include/asm-arm/arch-pxa/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
new file mode 100644
index 000000000000..748406f384c2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_ARCH_IRDA_H
+#define ASMARM_ARCH_IRDA_H
+/* board specific transceiver capabilities */
+#define IR_OFF          1
+#define IR_SIRMODE      2
+#define IR_FIRMODE      4
+struct pxaficp_platform_data {
+        int transceiver_cap;
+        void (*transceiver_mode)(struct device *dev, int mode);
+};
+extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
+#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index 58bad9748b5c..eaf6d43939e9 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0xa0000000UL)
+#define PHYS_OFFSET     UL(0xa0000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
new file mode 100644
index 000000000000..7a8a1cdf430d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2005 Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+extern int pxa_pm_prepare(suspend_state_t state);
+extern int pxa_pm_enter(suspend_state_t state);
+extern int pxa_pm_finish(suspend_state_t state);
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 939d9e5020a0..a75a2470f4f5 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -126,8 +126,8 @@
 #define DRCMR12         __REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
 #define DRCMR13         __REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
 #define DRCMR14         __REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15         __REG(0x4000013c)  /* Reserved */
+#define DRCMR15         __REG(0x4000013c)  /* Request to Channel Map Register for SSP2 receive Request */
-#define DRCMR16         __REG(0x40000140)  /* Reserved */
+#define DRCMR16         __REG(0x40000140)  /* Request to Channel Map Register for SSP2 transmit Request */
 #define DRCMR17         __REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
 #define DRCMR18         __REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
 #define DRCMR19         __REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
@@ -151,7 +151,8 @@
 #define DRCMR37         __REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
 #define DRCMR38         __REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
 #define DRCMR39         __REG(0x4000019C)  /* Reserved */
+#define DRCMR66         __REG(0x40001108)  /* Request to Channel Map Register for SSP3 receive Request */
+#define DRCMR67         __REG(0x4000110C)  /* Request to Channel Map Register for SSP3 transmit Request */
 #define DRCMR68         __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
 #define DRCMR69         __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
 #define DRCMR70         __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
@@ -325,6 +326,25 @@
 #define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
 #define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+/* Hardware UART (HWUART) */
+#define HWUART          HWRBR
+#define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
+#define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
+#define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
+#define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
+#define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
+#define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
+#define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
+#define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
+#define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
+#define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
+#define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
+#define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
+#define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
+#define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
+#define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 #define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
 #define IER_UUE         (1 << 6)        /* UART Unit Enable */
 #define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
@@ -652,7 +672,7 @@
 #define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
 #define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_IO_ROF    (1 << 3)        /* Receive overflow */
+#define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
 #define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
 #define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
 #define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
@@ -1012,14 +1032,12 @@
 #define ICCR0_LBM       (1 << 1)        /* Loopback mode */
 #define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
-#ifdef CONFIG_PXA27x
 #define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
 #define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
 #define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
 #define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
 #define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
 #define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
-#endif
 #ifdef CONFIG_PXA27x
 #define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
@@ -1249,9 +1267,13 @@
 #define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
 #define GPIO41_FFRTS            41      /* FFUART request to send */
 #define GPIO42_BTRXD            42      /* BTUART receive data */
+#define GPIO42_HWRXD            42      /* HWUART receive data */
 #define GPIO43_BTTXD            43      /* BTUART transmit data */
+#define GPIO43_HWTXD            43      /* HWUART transmit data */
 #define GPIO44_BTCTS            44      /* BTUART clear to send */
+#define GPIO44_HWCTS            44      /* HWUART clear to send */
 #define GPIO45_BTRTS            45      /* BTUART request to send */
+#define GPIO45_HWRTS            45      /* HWUART request to send */
 #define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
 #define GPIO46_ICPRXD           46      /* ICP receive data */
 #define GPIO46_STRXD            46      /* STD_UART receive data */
@@ -1377,17 +1399,26 @@
 #define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
 #define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
 #define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
 #define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
 #define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
 #define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
 #define GPIO45_SYSCLK_AC97_MD           (45 | GPIO_ALT_FN_1_OUT)
 #define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
 #define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
 #define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
 #define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
 #define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
 #define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
 #define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
 #define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
 #define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
 #define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
@@ -1762,6 +1793,7 @@
 #define CKEN7_BTUART    (1 << 7)        /* BTUART Unit Clock Enable */
 #define CKEN6_FFUART    (1 << 6)        /* FFUART Unit Clock Enable */
 #define CKEN5_STUART    (1 << 5)        /* STUART Unit Clock Enable */
+#define CKEN4_HWUART    (1 << 4)        /* HWUART Unit Clock Enable */
 #define CKEN4_SSP3      (1 << 4)        /* SSP3 Unit Clock Enable */
 #define CKEN3_SSP       (1 << 3)        /* SSP Unit Clock Enable */
 #define CKEN3_SSP2      (1 << 3)        /* SSP2 Unit Clock Enable */
@@ -2281,4 +2313,11 @@
 #endif
+/* PWRMODE register M field values */
+#define PWRMODE_IDLE            0x1
+#define PWRMODE_STANDBY         0x2
+#define PWRMODE_SLEEP           0x3
+#define PWRMODE_DEEPSLEEP       0x7
 #endif
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
index 21c0e16dce5f..aba9b30f4249 100644
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ b/include/asm-arm/arch-pxa/pxafb.h
@@ -66,4 +66,5 @@ struct pxafb_mach_info {
 };
 void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
+void set_pxa_fb_parent(struct device *parent_dev);
 unsigned long pxafb_get_hsync_time(struct device *dev);
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h
index 311f2bb5386a..0b43495d24b4 100644
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ b/include/asm-arm/arch-pxa/sharpsl.h
@@ -21,12 +21,18 @@ struct corgits_machinfo {
        void (*wait_hsync)(void);
 };
 /*
 * SharpSL Backlight
 */
 struct corgibl_machinfo {
        int max_intensity;
        void (*set_bl_intensity)(int intensity);
 };
+extern void corgibl_limit_intensity(int limit);
+/*
+ * SharpSL Battery/PM Driver
+ */
+extern void sharpsl_battery_kick(void);
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
index 6ec67b018c09..949878c0d908 100644
--- a/include/asm-arm/arch-pxa/ssp.h
+++ b/include/asm-arm/arch-pxa/ssp.h
@@ -18,6 +18,11 @@
 #ifndef SSP_H
 #define SSP_H
+/*
+ * SSP initialisation flags
+ */
+#define SSP_NO_IRQ      0x1             /* don't register an irq handler in SSP driver */
 struct ssp_state {
        u32     cr0;
        u32 cr1;
@@ -31,6 +36,7 @@ struct ssp_dev {
        u32 flags;
        u32 psp_flags;
        u32 speed;
+        int irq;
 };
 int ssp_write_word(struct ssp_dev *dev, u32 data);
@@ -40,7 +46,7 @@ void ssp_enable(struct ssp_dev *dev);
 void ssp_disable(struct ssp_dev *dev);
 void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
 void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
-int ssp_init(struct ssp_dev *dev, u32 port);
+int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
 int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
 void ssp_exit(struct ssp_dev *dev);
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h
new file mode 100644
index 000000000000..c3364a2c4758
--- /dev/null
+++ b/include/asm-arm/arch-pxa/tosa.h
@@ -0,0 +1,166 @@
+/*
+ * Hardware specific definitions for Sharp SL-C6000x series of PDAs
+ *
+ * Copyright (c) 2005 Dirk Opfer
+ *
+ * Based on Sharp's 2.4 kernel patches
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef _ASM_ARCH_TOSA_H_
+#define _ASM_ARCH_TOSA_H_ 1
+/*  TOSA Chip selects  */
+#define TOSA_LCDC_PHYS          PXA_CS4_PHYS
+/* Internel Scoop */
+#define TOSA_CF_PHYS            (PXA_CS2_PHYS + 0x00800000)
+/* Jacket Scoop */
+#define TOSA_SCOOP_PHYS         (PXA_CS5_PHYS + 0x00800000)
+/*
+ * SCOOP2 internal GPIOs
+ */
+#define TOSA_SCOOP_PXA_VCORE1           SCOOP_GPCR_PA11
+#define TOSA_SCOOP_TC6393_REST_IN       SCOOP_GPCR_PA12
+#define TOSA_SCOOP_IR_POWERDWN          SCOOP_GPCR_PA13
+#define TOSA_SCOOP_SD_WP                SCOOP_GPCR_PA14
+#define TOSA_SCOOP_PWR_ON               SCOOP_GPCR_PA15
+#define TOSA_SCOOP_AUD_PWR_ON           SCOOP_GPCR_PA16
+#define TOSA_SCOOP_BT_RESET             SCOOP_GPCR_PA17
+#define TOSA_SCOOP_BT_PWR_EN            SCOOP_GPCR_PA18
+#define TOSA_SCOOP_AC_IN_OL             SCOOP_GPCR_PA19
+/* GPIO Direction   1 : output mode / 0:input mode */
+#define TOSA_SCOOP_IO_DIR     ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
+                TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\
+                TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
+/* GPIO out put level when init   1: Hi */
+#define TOSA_SCOOP_IO_OUT     ( TOSA_SCOOP_TC6393_REST_IN )
+/*
+ * SCOOP2 jacket GPIOs
+ */
+#define TOSA_SCOOP_JC_BT_LED            SCOOP_GPCR_PA11
+#define TOSA_SCOOP_JC_NOTE_LED          SCOOP_GPCR_PA12
+#define TOSA_SCOOP_JC_CHRG_ERR_LED      SCOOP_GPCR_PA13
+#define TOSA_SCOOP_JC_USB_PULLUP        SCOOP_GPCR_PA14
+#define TOSA_SCOOP_JC_TC6393_SUSPEND    SCOOP_GPCR_PA15
+#define TOSA_SCOOP_JC_TC3693_L3V_ON     SCOOP_GPCR_PA16
+#define TOSA_SCOOP_JC_WLAN_DETECT       SCOOP_GPCR_PA17
+#define TOSA_SCOOP_JC_WLAN_LED          SCOOP_GPCR_PA18
+#define TOSA_SCOOP_JC_CARD_LIMIT_SEL    SCOOP_GPCR_PA19
+/* GPIO Direction   1 : output mode / 0:input mode */
+#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \
+                TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \
+                TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
+                TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL )
+/* GPIO out put level when init   1: Hi */
+#define TOSA_SCOOP_JC_IO_OUT ( 0 )
+/*
+ * Timing Generator
+ */
+#define TG_PNLCTL                       0x00
+#define TG_TPOSCTL                      0x01
+#define TG_DUTYCTL                      0x02
+#define TG_GPOSR                        0x03
+#define TG_GPODR1                       0x04
+#define TG_GPODR2                       0x05
+#define TG_PINICTL                      0x06
+#define TG_HPOSCTL                      0x07
+/*
+ * LED
+ */
+#define TOSA_SCOOP_LED_BLUE             TOSA_SCOOP_GPCR_PA11
+#define TOSA_SCOOP_LED_GREEN            TOSA_SCOOP_GPCR_PA12
+#define TOSA_SCOOP_LED_ORANGE           TOSA_SCOOP_GPCR_PA13
+#define TOSA_SCOOP_LED_WLAN             TOSA_SCOOP_GPCR_PA18
+/*
+ * PXA GPIOs
+ */
+#define TOSA_GPIO_POWERON               (0)
+#define TOSA_GPIO_RESET                 (1)
+#define TOSA_GPIO_AC_IN                 (2)
+#define TOSA_GPIO_RECORD_BTN            (3)
+#define TOSA_GPIO_SYNC                  (4)     /* Cradle SYNC Button */
+#define TOSA_GPIO_USB_IN                (5)
+#define TOSA_GPIO_JACKET_DETECT         (7)
+#define TOSA_GPIO_nSD_DETECT            (9)
+#define TOSA_GPIO_nSD_INT               (10)
+#define TOSA_GPIO_TC6393_CLK            (11)
+#define TOSA_GPIO_BAT1_CRG              (12)
+#define TOSA_GPIO_CF_CD                 (13)
+#define TOSA_GPIO_BAT0_CRG              (14)
+#define TOSA_GPIO_TC6393_INT            (15)
+#define TOSA_GPIO_BAT0_LOW              (17)
+#define TOSA_GPIO_TC6393_RDY            (18)
+#define TOSA_GPIO_ON_RESET              (19)
+#define TOSA_GPIO_EAR_IN                (20)
+#define TOSA_GPIO_CF_IRQ                (21)    /* CF slot0 Ready */
+#define TOSA_GPIO_ON_KEY                (22)
+#define TOSA_GPIO_VGA_LINE              (27)
+#define TOSA_GPIO_TP_INT                (32)    /* Touch Panel pen down interrupt */
+#define TOSA_GPIO_JC_CF_IRQ             (36)    /* CF slot1 Ready */
+#define TOSA_GPIO_BAT_LOCKED            (38)    /* Battery locked */
+#define TOSA_GPIO_TG_SPI_SCLK           (81)
+#define TOSA_GPIO_TG_SPI_CS             (82)
+#define TOSA_GPIO_TG_SPI_MOSI           (83)
+#define TOSA_GPIO_BAT1_LOW              (84)
+#define TOSA_GPIO_HP_IN                 GPIO_EAR_IN
+#define TOSA_GPIO_MAIN_BAT_LOW          GPIO_BAT0_LOW
+#define TOSA_KEY_STROBE_NUM             (11)
+#define TOSA_KEY_SENSE_NUM              (7)
+#define TOSA_GPIO_HIGH_STROBE_BIT       (0xfc000000)
+#define TOSA_GPIO_LOW_STROBE_BIT        (0x0000001f)
+#define TOSA_GPIO_ALL_SENSE_BIT         (0x00000fe0)
+#define TOSA_GPIO_ALL_SENSE_RSHIFT      (5)
+#define TOSA_GPIO_STROBE_BIT(a)         GPIO_bit(58+(a))
+#define TOSA_GPIO_SENSE_BIT(a)          GPIO_bit(69+(a))
+#define TOSA_GAFR_HIGH_STROBE_BIT       (0xfff00000)
+#define TOSA_GAFR_LOW_STROBE_BIT        (0x000003ff)
+#define TOSA_GAFR_ALL_SENSE_BIT         (0x00fffc00)
+#define TOSA_GPIO_KEY_SENSE(a)          (69+(a))
+#define TOSA_GPIO_KEY_STROBE(a)         (58+(a))
+/*
+ * Interrupts
+ */
+#define TOSA_IRQ_GPIO_WAKEUP            IRQ_GPIO(TOSA_GPIO_WAKEUP)
+#define TOSA_IRQ_GPIO_AC_IN             IRQ_GPIO(TOSA_GPIO_AC_IN)
+#define TOSA_IRQ_GPIO_RECORD_BTN        IRQ_GPIO(TOSA_GPIO_RECORD_BTN)
+#define TOSA_IRQ_GPIO_SYNC              IRQ_GPIO(TOSA_GPIO_SYNC)
+#define TOSA_IRQ_GPIO_USB_IN            IRQ_GPIO(TOSA_GPIO_USB_IN)
+#define TOSA_IRQ_GPIO_JACKET_DETECT     IRQ_GPIO(TOSA_GPIO_JACKET_DETECT)
+#define TOSA_IRQ_GPIO_nSD_INT           IRQ_GPIO(TOSA_GPIO_nSD_INT)
+#define TOSA_IRQ_GPIO_nSD_DETECT        IRQ_GPIO(TOSA_GPIO_nSD_DETECT)
+#define TOSA_IRQ_GPIO_BAT1_CRG          IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
+#define TOSA_IRQ_GPIO_CF_CD             IRQ_GPIO(TOSA_GPIO_CF_CD)
+#define TOSA_IRQ_GPIO_BAT0_CRG          IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
+#define TOSA_IRQ_GPIO_TC6393_INT        IRQ_GPIO(TOSA_GPIO_TC6393_INT)
+#define TOSA_IRQ_GPIO_BAT0_LOW          IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
+#define TOSA_IRQ_GPIO_EAR_IN            IRQ_GPIO(TOSA_GPIO_EAR_IN)
+#define TOSA_IRQ_GPIO_CF_IRQ            IRQ_GPIO(TOSA_GPIO_CF_IRQ)
+#define TOSA_IRQ_GPIO_ON_KEY            IRQ_GPIO(TOSA_GPIO_ON_KEY)
+#define TOSA_IRQ_GPIO_VGA_LINE          IRQ_GPIO(TOSA_GPIO_VGA_LINE)
+#define TOSA_IRQ_GPIO_TP_INT            IRQ_GPIO(TOSA_GPIO_TP_INT)
+#define TOSA_IRQ_GPIO_JC_CF_IRQ         IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ)
+#define TOSA_IRQ_GPIO_BAT_LOCKED        IRQ_GPIO(TOSA_GPIO_BAT_LOCKED)
+#define TOSA_IRQ_GPIO_BAT1_LOW          IRQ_GPIO(TOSA_GPIO_BAT1_LOW)
+#define TOSA_IRQ_GPIO_KEY_SENSE(a)      IRQ_GPIO(69+(a))
+#define TOSA_IRQ_GPIO_MAIN_BAT_LOW      IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
+extern struct platform_device tosascoop_jc_device;
+extern struct platform_device tosascoop_device;
+#endif /* _ASM_ARCH_TOSA_H_ */
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 4428d3eb7432..fe38090444e0 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -12,6 +12,7 @@
 #define FFUART          ((volatile unsigned long *)0x40100000)
 #define BTUART          ((volatile unsigned long *)0x40200000)
 #define STUART          ((volatile unsigned long *)0x40700000)
+#define HWUART          ((volatile unsigned long *)0x41600000)
 #define UART            FFUART
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
new file mode 100644
index 000000000000..ed28bd012236
--- /dev/null
+++ b/include/asm-arm/arch-realview/debug-macro.S
@@ -0,0 +1,38 @@
+/* linux/include/asm-arm/arch-realview/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <asm/hardware/amba_serial.h>
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx,      #0x10000000
+                movne   \rx,      #0xf1000000   @ virtual base
+                orr     \rx, \rx, #0x00009000
+                .endm
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #UART01x_DR]
+                .endm
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-realview/dma.h b/include/asm-arm/arch-realview/dma.h
new file mode 100644
index 000000000000..744491a74bd9
--- /dev/null
+++ b/include/asm-arm/arch-realview/dma.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/include/asm-arm/arch-realview/dma.h
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
new file mode 100644
index 000000000000..6288fad0dc41
--- /dev/null
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -0,0 +1,74 @@
+/*
+ * include/asm-arm/arch-realview/entry-macro.S
+ *
+ * Low-level IRQ helper macros for RealView platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware/gic.h>
+                .macro  disable_fiq
+                .endm
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an interrupt if it's
+                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+                 *
+                 * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+                 * valid range for an IRQ (30-1020 inclusive).
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+                ldr     \tmp, =1021
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt on the
+                 * controller, since this requires the original irqstat value which
+                 * we won't easily be able to recreate later.
+                 */
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* As above, this assumes that irqstat and base are preserved.. */
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
new file mode 100644
index 000000000000..9ca76dc3a7af
--- /dev/null
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/arch-realview/hardware.h
+ *
+ *  This file contains the hardware definitions of the RealView boards.
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/sizes.h>
+#include <asm/arch/platform.h>
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+#define __io_address(n)         __io(IO_ADDRESS(n))
+#endif
diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h
new file mode 100644
index 000000000000..d444a68ac330
--- /dev/null
+++ b/include/asm-arm/arch-realview/io.h
@@ -0,0 +1,34 @@
+/*
+ *  linux/include/asm-arm/arch-realview/io.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
new file mode 100644
index 000000000000..c16223c9588d
--- /dev/null
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -0,0 +1,106 @@
+/*
+ *  linux/include/asm-arm/arch-realview/irqs.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/arch/platform.h>
+#define IRQ_LOCALTIMER                  29
+#define IRQ_LOCALWDOG                   30
+/* 
+ *  IRQ interrupts definitions are the same the INT definitions
+ *  held within platform.h
+ */
+#define IRQ_GIC_START           32
+#define IRQ_WDOGINT             (IRQ_GIC_START + INT_WDOGINT)
+#define IRQ_SOFTINT             (IRQ_GIC_START + INT_SOFTINT)
+#define IRQ_COMMRx              (IRQ_GIC_START + INT_COMMRx)
+#define IRQ_COMMTx              (IRQ_GIC_START + INT_COMMTx)
+#define IRQ_TIMERINT0_1         (IRQ_GIC_START + INT_TIMERINT0_1)
+#define IRQ_TIMERINT2_3         (IRQ_GIC_START + INT_TIMERINT2_3)
+#define IRQ_GPIOINT0            (IRQ_GIC_START + INT_GPIOINT0)
+#define IRQ_GPIOINT1            (IRQ_GIC_START + INT_GPIOINT1)
+#define IRQ_GPIOINT2            (IRQ_GIC_START + INT_GPIOINT2)
+#define IRQ_GPIOINT3            (IRQ_GIC_START + INT_GPIOINT3)
+#define IRQ_RTCINT              (IRQ_GIC_START + INT_RTCINT)
+#define IRQ_SSPINT              (IRQ_GIC_START + INT_SSPINT)
+#define IRQ_UARTINT0            (IRQ_GIC_START + INT_UARTINT0)
+#define IRQ_UARTINT1            (IRQ_GIC_START + INT_UARTINT1)
+#define IRQ_UARTINT2            (IRQ_GIC_START + INT_UARTINT2)
+#define IRQ_UART3               (IRQ_GIC_START + INT_UARTINT3)
+#define IRQ_SCIINT              (IRQ_GIC_START + INT_SCIINT)
+#define IRQ_CLCDINT             (IRQ_GIC_START + INT_CLCDINT)
+#define IRQ_DMAINT              (IRQ_GIC_START + INT_DMAINT)
+#define IRQ_PWRFAILINT          (IRQ_GIC_START + INT_PWRFAILINT)
+#define IRQ_MBXINT              (IRQ_GIC_START + INT_MBXINT)
+#define IRQ_GNDINT              (IRQ_GIC_START + INT_GNDINT)
+#define IRQ_MMCI0B              (IRQ_GIC_START + INT_MMCI0B)
+#define IRQ_MMCI1B              (IRQ_GIC_START + INT_MMCI1B)
+#define IRQ_KMI0                (IRQ_GIC_START + INT_KMI0)
+#define IRQ_KMI1                (IRQ_GIC_START + INT_KMI1)
+#define IRQ_SCI3                (IRQ_GIC_START + INT_SCI3)
+#define IRQ_CLCD                (IRQ_GIC_START + INT_CLCD)
+#define IRQ_TOUCH               (IRQ_GIC_START + INT_TOUCH)
+#define IRQ_KEYPAD              (IRQ_GIC_START + INT_KEYPAD)
+#define IRQ_DoC                 (IRQ_GIC_START + INT_DoC)
+#define IRQ_MMCI0A              (IRQ_GIC_START + INT_MMCI0A)
+#define IRQ_MMCI1A              (IRQ_GIC_START + INT_MMCI1A)
+#define IRQ_AACI                (IRQ_GIC_START + INT_AACI)
+#define IRQ_ETH                 (IRQ_GIC_START + INT_ETH)
+#define IRQ_USB                 (IRQ_GIC_START + INT_USB)
+#define IRQMASK_WDOGINT         INTMASK_WDOGINT
+#define IRQMASK_SOFTINT         INTMASK_SOFTINT
+#define IRQMASK_COMMRx          INTMASK_COMMRx
+#define IRQMASK_COMMTx          INTMASK_COMMTx
+#define IRQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
+#define IRQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
+#define IRQMASK_GPIOINT0        INTMASK_GPIOINT0
+#define IRQMASK_GPIOINT1        INTMASK_GPIOINT1
+#define IRQMASK_GPIOINT2        INTMASK_GPIOINT2
+#define IRQMASK_GPIOINT3        INTMASK_GPIOINT3
+#define IRQMASK_RTCINT          INTMASK_RTCINT
+#define IRQMASK_SSPINT          INTMASK_SSPINT
+#define IRQMASK_UARTINT0        INTMASK_UARTINT0
+#define IRQMASK_UARTINT1        INTMASK_UARTINT1
+#define IRQMASK_UARTINT2        INTMASK_UARTINT2
+#define IRQMASK_SCIINT          INTMASK_SCIINT
+#define IRQMASK_CLCDINT         INTMASK_CLCDINT
+#define IRQMASK_DMAINT          INTMASK_DMAINT
+#define IRQMASK_PWRFAILINT      INTMASK_PWRFAILINT
+#define IRQMASK_MBXINT          INTMASK_MBXINT
+#define IRQMASK_GNDINT          INTMASK_GNDINT
+#define IRQMASK_MMCI0B          INTMASK_MMCI0B
+#define IRQMASK_MMCI1B          INTMASK_MMCI1B
+#define IRQMASK_KMI0            INTMASK_KMI0
+#define IRQMASK_KMI1            INTMASK_KMI1
+#define IRQMASK_SCI3            INTMASK_SCI3
+#define IRQMASK_UART3           INTMASK_UART3
+#define IRQMASK_CLCD            INTMASK_CLCD
+#define IRQMASK_TOUCH           INTMASK_TOUCH
+#define IRQMASK_KEYPAD          INTMASK_KEYPAD
+#define IRQMASK_DoC             INTMASK_DoC
+#define IRQMASK_MMCI0A          INTMASK_MMCI0A
+#define IRQMASK_MMCI1A          INTMASK_MMCI1A
+#define IRQMASK_AACI            INTMASK_AACI
+#define IRQMASK_ETH             INTMASK_ETH
+#define IRQMASK_USB             INTMASK_USB
+#define NR_IRQS                 (IRQ_GIC_START + 64)
diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h
new file mode 100644
index 000000000000..ed370abb638f
--- /dev/null
+++ b/include/asm-arm/arch-realview/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-realview/memory.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x00000000)
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+#endif
diff --git a/include/asm-arm/arch-realview/param.h b/include/asm-arm/arch-realview/param.h
new file mode 100644
index 000000000000..89b1235d32bd
--- /dev/null
+++ b/include/asm-arm/arch-realview/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-realview/param.h
+ *
+ *  Copyright (C) 2002 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
new file mode 100644
index 000000000000..18d7c18b738c
--- /dev/null
+++ b/include/asm-arm/arch-realview/platform.h
@@ -0,0 +1,450 @@
+/*
+ * linux/include/asm-arm/arch-realview/platform.h
+ *
+ * Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __address_h
+#define __address_h                     1
+/*
+ * Memory definitions
+ */
+#define REALVIEW_BOOT_ROM_LO          0x30000000                /* DoC Base (64Mb)...*/
+#define REALVIEW_BOOT_ROM_HI          0x30000000
+#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI       /*  Normal position */
+#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
+#define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
+#define REALVIEW_SSRAM_SIZE           SZ_2M
+#define REALVIEW_FLASH_BASE           0x40000000
+#define REALVIEW_FLASH_SIZE           SZ_64M
+/* 
+ *  SDRAM
+ */
+#define REALVIEW_SDRAM_BASE           0x00000000
+/* 
+ *  Logic expansion modules
+ * 
+ */
+/* ------------------------------------------------------------------------
+ *  RealView Registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define REALVIEW_SYS_ID_OFFSET               0x00
+#define REALVIEW_SYS_SW_OFFSET               0x04
+#define REALVIEW_SYS_LED_OFFSET              0x08
+#define REALVIEW_SYS_OSC0_OFFSET             0x0C
+#define REALVIEW_SYS_OSC1_OFFSET             0x10
+#define REALVIEW_SYS_OSC2_OFFSET             0x14
+#define REALVIEW_SYS_OSC3_OFFSET             0x18
+#define REALVIEW_SYS_OSC4_OFFSET             0x1C       /* OSC1 for RealView/AB */
+#define REALVIEW_SYS_LOCK_OFFSET             0x20
+#define REALVIEW_SYS_100HZ_OFFSET            0x24
+#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
+#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
+#define REALVIEW_SYS_FLAGS_OFFSET            0x30
+#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
+#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
+#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
+#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
+#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
+#define REALVIEW_SYS_PCICTL_OFFSET           0x44
+#define REALVIEW_SYS_MCI_OFFSET              0x48
+#define REALVIEW_SYS_FLASH_OFFSET            0x4C
+#define REALVIEW_SYS_CLCD_OFFSET             0x50
+#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
+#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
+#define REALVIEW_SYS_24MHz_OFFSET            0x5C
+#define REALVIEW_SYS_MISC_OFFSET             0x60
+#define REALVIEW_SYS_IOSEL_OFFSET            0x70
+#define REALVIEW_SYS_TEST_OSC0_OFFSET        0x80
+#define REALVIEW_SYS_TEST_OSC1_OFFSET        0x84
+#define REALVIEW_SYS_TEST_OSC2_OFFSET        0x88
+#define REALVIEW_SYS_TEST_OSC3_OFFSET        0x8C
+#define REALVIEW_SYS_TEST_OSC4_OFFSET        0x90
+#define REALVIEW_SYS_BASE                    0x10000000
+#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
+#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
+#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
+#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
+#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
+#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
+#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
+#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
+#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
+#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
+#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
+#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
+#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
+#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
+#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
+#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
+#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
+#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
+#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
+#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
+#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
+#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
+#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
+#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
+#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
+#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
+#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
+#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
+#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
+/* 
+ * Values for REALVIEW_SYS_RESET_CTRL
+ */
+#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR    0x01
+#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT   0x02
+#define REALVIEW_SYS_CTRL_RESET_DLLRESET     0x03
+#define REALVIEW_SYS_CTRL_RESET_PLLRESET     0x04
+#define REALVIEW_SYS_CTRL_RESET_POR          0x05
+#define REALVIEW_SYS_CTRL_RESET_DoC          0x06
+#define REALVIEW_SYS_CTRL_LED         (1 << 0)
+/* ------------------------------------------------------------------------
+ *  RealView control registers
+ * ------------------------------------------------------------------------
+ */
+/* 
+ * REALVIEW_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+/*
+ * REALVIEW_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
+#define REALVIEW_SYS_LOCKVAL_MASK       0xFFFF          /* write 0xA05F to enable write access */
+/*
+ * REALVIEW_SYS_FLASH
+ */
+#define REALVIEW_FLASHPROG_FLVPPEN      (1 << 0)        /* Enable writing to flash */
+/*
+ * REALVIEW_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts 
+ */
+#define REALVIEW_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
+#define REALVIEW_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
+#define REALVIEW_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
+                                                /* write 1 to acknowledge and clear               */
+#define REALVIEW_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
+#define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
+/*
+ * REALVIEW peripheral addresses
+ */
+#define REALVIEW_SCTL_BASE            0x10001000        /* System controller */
+#define REALVIEW_I2C_BASE             0x10002000        /* I2C control */
+        /* Reserved 0x10003000 */
+#define REALVIEW_AACI_BASE            0x10004000        /* Audio */
+#define REALVIEW_MMCI0_BASE           0x10005000        /* MMC interface */
+#define REALVIEW_KMI0_BASE            0x10006000        /* KMI interface */
+#define REALVIEW_KMI1_BASE            0x10007000        /* KMI 2nd interface */
+#define REALVIEW_CHAR_LCD_BASE        0x10008000        /* Character LCD */
+#define REALVIEW_UART0_BASE           0x10009000        /* UART 0 */
+#define REALVIEW_UART1_BASE           0x1000A000        /* UART 1 */
+#define REALVIEW_UART2_BASE           0x1000B000        /* UART 2 */
+#define REALVIEW_UART3_BASE           0x1000C000        /* UART 3 */
+#define REALVIEW_SSP_BASE             0x1000D000        /* Synchronous Serial Port */
+#define REALVIEW_SCI_BASE             0x1000E000        /* Smart card controller */
+        /* Reserved 0x1000F000 */
+#define REALVIEW_WATCHDOG_BASE        0x10010000        /* watchdog interface */
+#define REALVIEW_TIMER0_1_BASE        0x10011000        /* Timer 0 and 1 */
+#define REALVIEW_TIMER2_3_BASE        0x10012000        /* Timer 2 and 3 */
+#define REALVIEW_GPIO0_BASE           0x10013000        /* GPIO port 0 */
+#define REALVIEW_GPIO1_BASE           0x10014000        /* GPIO port 1 */
+#define REALVIEW_GPIO2_BASE           0x10015000        /* GPIO port 2 */
+        /* Reserved 0x10016000 */
+#define REALVIEW_RTC_BASE             0x10017000        /* Real Time Clock */
+#define REALVIEW_DMC_BASE             0x10018000        /* DMC configuration */
+#define REALVIEW_PCI_CORE_BASE        0x10019000        /* PCI configuration */
+        /* Reserved 0x1001A000 - 0x1001FFFF */
+#define REALVIEW_CLCD_BASE            0x10020000        /* CLCD */
+#define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
+#ifndef CONFIG_REALVIEW_MPCORE
+#define REALVIEW_GIC_CPU_BASE         0x10040000        /* Generic interrupt controller CPU interface */
+#define REALVIEW_GIC_DIST_BASE        0x10041000        /* Generic interrupt controller distributor */
+#else
+#define REALVIEW_MPCORE_SCU_BASE        0x10100000      /*  SCU registers */
+#define REALVIEW_GIC_CPU_BASE           0x10100100      /* Generic interrupt controller CPU interface */
+#define REALVIEW_TWD_BASE               0x10100700
+#define REALVIEW_TWD_SIZE               0x00000100
+#define REALVIEW_GIC_DIST_BASE          0x10101000      /* Generic interrupt controller distributor */
+#endif
+#define REALVIEW_SMC_BASE             0x10080000        /* SMC */
+        /* Reserved 0x10090000 - 0x100EFFFF */
+#define REALVIEW_ETH_BASE             0x4E000000        /* Ethernet */
+/* PCI space */
+#define REALVIEW_PCI_BASE             0x41000000        /* PCI Interface */
+#define REALVIEW_PCI_CFG_BASE         0x42000000
+#define REALVIEW_PCI_MEM_BASE0        0x44000000
+#define REALVIEW_PCI_MEM_BASE1        0x50000000
+#define REALVIEW_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define REALVIEW_PCI_BASE_SIZE         0x01000000
+#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
+#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000        /* 32Mb */
+#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000        /* 256Mb */
+#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000        /* 256Mb */
+#define REALVIEW_SDRAM67_BASE         0x70000000        /* SDRAM banks 6 and 7 */
+#define REALVIEW_LT_BASE              0x80000000        /* Logic Tile expansion */
+/*
+ * Disk on Chip
+ */
+#define REALVIEW_DOC_BASE             0x2C000000
+#define REALVIEW_DOC_SIZE             (16 << 20)
+#define REALVIEW_DOC_PAGE_SIZE        512
+#define REALVIEW_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
+#define ERASE_UNIT_PAGES    32
+#define START_PAGE          0x80
+/* 
+ *  LED settings, bits [7:0]
+ */
+#define REALVIEW_SYS_LED0             (1 << 0)
+#define REALVIEW_SYS_LED1             (1 << 1)
+#define REALVIEW_SYS_LED2             (1 << 2)
+#define REALVIEW_SYS_LED3             (1 << 3)
+#define REALVIEW_SYS_LED4             (1 << 4)
+#define REALVIEW_SYS_LED5             (1 << 5)
+#define REALVIEW_SYS_LED6             (1 << 6)
+#define REALVIEW_SYS_LED7             (1 << 7)
+#define ALL_LEDS                  0xFF
+#define LED_BANK                  REALVIEW_SYS_LED
+/* 
+ * Control registers
+ */
+#define REALVIEW_IDFIELD_OFFSET 0x0     /* RealView build information */
+#define REALVIEW_FLASHPROG_OFFSET       0x4     /* Flash devices */
+#define REALVIEW_INTREG_OFFSET          0x8     /* Interrupt control */
+#define REALVIEW_DECODE_OFFSET          0xC     /* Fitted logic modules */
+/* ------------------------------------------------------------------------
+ *  Interrupts - bit assignment (primary)
+ * ------------------------------------------------------------------------
+ */
+#ifndef CONFIG_REALVIEW_MPCORE
+#define INT_WDOGINT                     0       /* Watchdog timer */
+#define INT_SOFTINT                     1       /* Software interrupt */
+#define INT_COMMRx                      2       /* Debug Comm Rx interrupt */
+#define INT_COMMTx                      3       /* Debug Comm Tx interrupt */
+#define INT_TIMERINT0_1                 4       /* Timer 0 and 1 */
+#define INT_TIMERINT2_3                 5       /* Timer 2 and 3 */
+#define INT_GPIOINT0                    6       /* GPIO 0 */
+#define INT_GPIOINT1                    7       /* GPIO 1 */
+#define INT_GPIOINT2                    8       /* GPIO 2 */
+/* 9 reserved */
+#define INT_RTCINT                      10      /* Real Time Clock */
+#define INT_SSPINT                      11      /* Synchronous Serial Port */
+#define INT_UARTINT0                    12      /* UART 0 on development chip */
+#define INT_UARTINT1                    13      /* UART 1 on development chip */
+#define INT_UARTINT2                    14      /* UART 2 on development chip */
+#define INT_UARTINT3                    15      /* UART 3 on development chip */
+#define INT_SCIINT                      16      /* Smart Card Interface */
+#define INT_MMCI0A                      17      /* Multimedia Card 0A */
+#define INT_MMCI0B                      18      /* Multimedia Card 0B */
+#define INT_AACI                        19      /* Audio Codec */
+#define INT_KMI0                        20      /* Keyboard/Mouse port 0 */
+#define INT_KMI1                        21      /* Keyboard/Mouse port 1 */
+#define INT_CHARLCD                     22      /* Character LCD */
+#define INT_CLCDINT                     23      /* CLCD controller */
+#define INT_DMAINT                      24      /* DMA controller */
+#define INT_PWRFAILINT                  25      /* Power failure */
+#define INT_PISMO                       26
+#define INT_DoC                         27      /* Disk on Chip memory controller */
+#define INT_ETH                         28      /* Ethernet controller */
+#define INT_USB                         29      /* USB controller */
+#define INT_TSPENINT                    30      /* Touchscreen pen */
+#define INT_TSKPADINT                   31      /* Touchscreen keypad */
+#else
+#define INT_AACI                        0
+#define INT_TIMERINT0_1                 1
+#define INT_TIMERINT2_3                 2
+#define INT_USB                         3
+#define INT_UARTINT0                    4
+#define INT_UARTINT1                    5
+#define INT_RTCINT                      6
+#define INT_KMI0                        7
+#define INT_KMI1                        8
+#define INT_ETH                         9
+#define INT_EB_IRQ1                     10      /* main GIC */
+#define INT_EB_IRQ2                     11      /* tile GIC */
+#define INT_EB_FIQ1                     12      /* main GIC */
+#define INT_EB_FIQ2                     13      /* tile GIC */
+#define INT_MMCI0A                      14
+#define INT_MMCI0B                      15
+#define INT_PMU_CPU0                    17
+#define INT_PMU_CPU1                    18
+#define INT_PMU_CPU2                    19
+#define INT_PMU_CPU3                    20
+#define INT_PMU_SCU0                    21
+#define INT_PMU_SCU1                    22
+#define INT_PMU_SCU2                    23
+#define INT_PMU_SCU3                    24
+#define INT_PMU_SCU4                    25
+#define INT_PMU_SCU5                    26
+#define INT_PMU_SCU6                    27
+#define INT_PMU_SCU7                    28
+#define INT_L220_EVENT                  29
+#define INT_L220_SLAVE                  30
+#define INT_L220_DECODE                 31
+#define INT_UARTINT2                    -1
+#define INT_UARTINT3                    -1
+#define INT_CLCDINT                     -1
+#define INT_DMAINT                      -1
+#define INT_WDOGINT                     -1
+#define INT_GPIOINT0                    -1
+#define INT_GPIOINT1                    -1
+#define INT_GPIOINT2                    -1
+#define INT_SCIINT                      -1
+#define INT_SSPINT                      -1
+#endif
+/* 
+ *  Interrupt bit positions
+ * 
+ */
+#define INTMASK_WDOGINT                 (1 << INT_WDOGINT)
+#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
+#define INTMASK_COMMRx                  (1 << INT_COMMRx)
+#define INTMASK_COMMTx                  (1 << INT_COMMTx)
+#define INTMASK_TIMERINT0_1             (1 << INT_TIMERINT0_1)
+#define INTMASK_TIMERINT2_3             (1 << INT_TIMERINT2_3)
+#define INTMASK_GPIOINT0                (1 << INT_GPIOINT0)
+#define INTMASK_GPIOINT1                (1 << INT_GPIOINT1)
+#define INTMASK_GPIOINT2                (1 << INT_GPIOINT2)
+#define INTMASK_RTCINT                  (1 << INT_RTCINT)
+#define INTMASK_SSPINT                  (1 << INT_SSPINT)
+#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
+#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
+#define INTMASK_UARTINT2                (1 << INT_UARTINT2)
+#define INTMASK_UARTINT3                (1 << INT_UARTINT3)
+#define INTMASK_SCIINT                  (1 << INT_SCIINT)
+#define INTMASK_MMCI0A                  (1 << INT_MMCI0A)
+#define INTMASK_MMCI0B                  (1 << INT_MMCI0B)
+#define INTMASK_AACI                    (1 << INT_AACI)
+#define INTMASK_KMI0                    (1 << INT_KMI0)
+#define INTMASK_KMI1                    (1 << INT_KMI1)
+#define INTMASK_CHARLCD                 (1 << INT_CHARLCD)
+#define INTMASK_CLCDINT                 (1 << INT_CLCDINT)
+#define INTMASK_DMAINT                  (1 << INT_DMAINT)
+#define INTMASK_PWRFAILINT              (1 << INT_PWRFAILINT)
+#define INTMASK_PISMO                   (1 << INT_PISMO)
+#define INTMASK_DoC                     (1 << INT_DoC)
+#define INTMASK_ETH                     (1 << INT_ETH)
+#define INTMASK_USB                     (1 << INT_USB)
+#define INTMASK_TSPENINT                (1 << INT_TSPENINT)
+#define INTMASK_TSKPADINT               (1 << INT_TSKPADINT)
+#define MAXIRQNUM                       31
+#define MAXFIQNUM                       31
+#define MAXSWINUM                       31
+/* 
+ *  Application Flash
+ * 
+ */
+#define FLASH_BASE                      REALVIEW_FLASH_BASE
+#define FLASH_SIZE                      REALVIEW_FLASH_SIZE
+#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
+#define FLASH_BLOCK_SIZE                SZ_128K
+/* 
+ *  Boot Flash
+ * 
+ */
+#define EPROM_BASE                      REALVIEW_BOOT_ROM_HI
+#define EPROM_SIZE                      REALVIEW_BOOT_ROM_SIZE
+#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      EPROM_BASE
+/*
+ * System controller bit assignment
+ */
+#define REALVIEW_REFCLK 0
+#define REALVIEW_TIMCLK 1
+#define REALVIEW_TIMER1_EnSel   15
+#define REALVIEW_TIMER2_EnSel   17
+#define REALVIEW_TIMER3_EnSel   19
+#define REALVIEW_TIMER4_EnSel   21
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  1
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+#define REALVIEW_CSR_BASE             0x10000000
+#define REALVIEW_CSR_SIZE             0x10000000
+#endif
+/*      END */
diff --git a/include/asm-arm/arch-realview/smp.h b/include/asm-arm/arch-realview/smp.h
new file mode 100644
index 000000000000..fc87783e8e8b
--- /dev/null
+++ b/include/asm-arm/arch-realview/smp.h
@@ -0,0 +1,31 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+#include <linux/config.h>
+#include <asm/hardware/gic.h>
+#define hard_smp_processor_id()                 \
+        ({                                              \
+                unsigned int cpunum;                    \
+                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
+                        : "=r" (cpunum));               \
+                cpunum &= 0x0F;                         \
+        })
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(cpumask_t callmap)
+{
+        gic_raise_softirq(callmap, 1);
+}
+/*
+ * Do nothing on MPcore.
+ */
+static inline void smp_cross_call_done(cpumask_t callmap)
+{
+}
+#endif
diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h
new file mode 100644
index 000000000000..6f3d0ce0ca1e
--- /dev/null
+++ b/include/asm-arm/arch-realview/system.h
@@ -0,0 +1,51 @@
+/*
+ *  linux/include/asm-arm/arch-realview/system.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET;
+        unsigned int val;
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        val = __raw_readl(hdr_ctrl);
+        val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR;
+        __raw_writel(val, hdr_ctrl);
+}
+#endif
diff --git a/include/asm-arm/arch-realview/timex.h b/include/asm-arm/arch-realview/timex.h
new file mode 100644
index 000000000000..5b9d82d0a5e0
--- /dev/null
+++ b/include/asm-arm/arch-realview/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  linux/include/asm-arm/arch-realview/timex.h
+ *
+ *  RealView architecture timex specifications
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
new file mode 100644
index 000000000000..b5e4d360665b
--- /dev/null
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -0,0 +1,54 @@
+/*
+ *  linux/include/asm-arm/arch-realview/uncompress.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/hardware.h>
+#define AMBA_UART_DR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
+#define AMBA_UART_LCRH  (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
+#define AMBA_UART_CR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
+#define AMBA_UART_FR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                while (AMBA_UART_FR & (1 << 5))
+                        barrier();
+                AMBA_UART_DR = *s;
+                if (*s == '\n') {
+                        while (AMBA_UART_FR & (1 << 5))
+                                barrier();
+                        AMBA_UART_DR = '\r';
+                }
+                s++;
+        }
+        while (AMBA_UART_FR & (1 << 3))
+                barrier();
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-realview/vmalloc.h b/include/asm-arm/arch-realview/vmalloc.h
new file mode 100644
index 000000000000..0ad49af186af
--- /dev/null
+++ b/include/asm-arm/arch-realview/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-realview/vmalloc.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/include/asm-arm/arch-rpc/hardware.h b/include/asm-arm/arch-rpc/hardware.h
index be9754a05c19..9d7f87375aa7 100644
--- a/include/asm-arm/arch-rpc/hardware.h
+++ b/include/asm-arm/arch-rpc/hardware.h
@@ -15,7 +15,7 @@
 #include <asm/arch/memory.h>
 #ifndef __ASSEMBLY__
-#define IOMEM(x) ((void __iomem *)(x))
+#define IOMEM(x) ((void __iomem *)(unsigned long)(x))
 #else
 #define IOMEM(x) x
 #endif /* __ASSEMBLY__ */
@@ -52,7 +52,7 @@
 /*
 * IO Addresses
 */
-#define VIDC_BASE               (void __iomem *)0xe0400000
+#define VIDC_BASE               IOMEM(0xe0400000)
 #define EXPMASK_BASE            0xe0360000
 #define IOMD_BASE               IOMEM(0xe0200000)
 #define IOC_BASE                IOMEM(0xe0200000)
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index 24453c405a87..b4da08d7a336 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-rpc/memory.h b/include/asm-arm/arch-rpc/memory.h
index 33fc75cdead0..0592cb3f0c74 100644
--- a/include/asm-arm/arch-rpc/memory.h
+++ b/include/asm-arm/arch-rpc/memory.h
@@ -21,7 +21,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x10000000UL)
+#define PHYS_OFFSET     UL(0x10000000)
 /*
 * These are exactly the same on the RiscPC as the
diff --git a/include/asm-arm/arch-rpc/system.h b/include/asm-arm/arch-rpc/system.h
index ca3277d1d5ea..729c2ae4b513 100644
--- a/include/asm-arm/arch-rpc/system.h
+++ b/include/asm-arm/arch-rpc/system.h
@@ -7,7 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #include <asm/hardware/iomd.h>
 #include <asm/io.h>
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
index 97741d6e506a..d529ffda8599 100644
--- a/include/asm-arm/arch-s3c2410/anubis-map.h
+++ b/include/asm-arm/arch-s3c2410/anubis-map.h
@@ -20,22 +20,22 @@
 /* start peripherals off after the S3C2410 */
-#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x02000000))
+#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x01800000))
 #define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
 /* we put the CPLD registers next, to get them out of the way */
-#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01300000 */
+#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01800000 */
 #define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
-#define ANUBIS_VA_CTRL2     ANUBIS_IOADDR(0x00100000)    /* 0x01400000 */
+#define ANUBIS_VA_CTRL2     ANUBIS_IOADDR(0x00100000)    /* 0x01900000 */
 #define ANUBIS_PA_CTRL2     (ANUBIS_PA_CPLD)
-#define ANUBIS_VA_CTRL3     ANUBIS_IOADDR(0x00200000)    /* 0x01500000 */
+#define ANUBIS_VA_CTRL3     ANUBIS_IOADDR(0x00200000)    /* 0x01A00000 */
 #define ANUBIS_PA_CTRL3     (ANUBIS_PA_CPLD)
-#define ANUBIS_VA_CTRL4     ANUBIS_IOADDR(0x00300000)    /* 0x01600000 */
+#define ANUBIS_VA_CTRL4     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
 #define ANUBIS_PA_CTRL4     (ANUBIS_PA_CPLD)
 #define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
index ac57bc887d82..4790491ba9d0 100644
--- a/include/asm-arm/arch-s3c2410/fb.h
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -13,6 +13,7 @@
 *      07-Sep-2004     RTP     Created file
 *      03-Nov-2004     BJD     Updated and minor cleanups
 *      03-Aug-2005     RTP     Renamed to fb.h
+ *      26-Oct-2005     BJD     Changed name of platdata init
 */
 #ifndef __ASM_ARM_FB_H
@@ -64,6 +65,6 @@ struct s3c2410fb_mach_info {
        unsigned long   lpcsel;
 };
-void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
+extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
 #endif /* __ASM_ARM_FB_H */
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 48a39918a760..1c9de29cafef 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -92,6 +92,13 @@ extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
 extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
+#ifdef CONFIG_CPU_S3C2440
+extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
+#endif /* CONFIG_CPU_S3C2440 */
 #endif /* __ASSEMBLY__ */
 #include <asm/sizes.h>
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
index 418233a7ee6f..16fbc8afffd9 100644
--- a/include/asm-arm/arch-s3c2410/io.h
+++ b/include/asm-arm/arch-s3c2410/io.h
@@ -9,12 +9,14 @@
 *  06-Dec-1997 RMK     Created.
 *  02-Sep-2003 BJD     Modified for S3C2410
 *  10-Mar-2005 LCVR    Changed S3C2410_VA to S3C24XX_VA
- *
+ *  13-Oct-2005 BJD     Fixed problems with LDRH/STRH offset range
 */
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
@@ -97,7 +99,7 @@ DECLARE_IO(int,l,"")
        else                                                            \
                __asm__ __volatile__(                                   \
                "strb   %0, [%1, #0]    @ outbc"                        \
-                : : "r" (value), "r" ((port)));         \
+                : : "r" (value), "r" ((port)));                         \
 })
 #define __inbc(port)                                                    \
@@ -110,35 +112,61 @@ DECLARE_IO(int,l,"")
        else                                                            \
                __asm__ __volatile__(                                   \
                "ldrb   %0, [%1, #0]    @ inbc"                         \
-                : "=r" (result) : "r" ((port)));        \
+                : "=r" (result) : "r" ((port)));                        \
        result;                                                         \
 })
 #define __outwc(value,port)                                             \
 ({                                                                      \
        unsigned long v = value;                                        \
-        if (__PORT_PCIO((port)))                                        \
+        if (__PORT_PCIO((port))) {                                      \
-                __asm__ __volatile__(                                   \
+                if ((port) < 256 && (port) > -256)                      \
-                "strh   %0, [%1, %2]    @ outwc"                        \
+                        __asm__ __volatile__(                           \
-                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
+                        "strh   %0, [%1, %2]    @ outwc"                \
-        else                                                            \
+                        : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
+                else if ((port) > 0)                                    \
+                        __asm__ __volatile__(                           \
+                        "strh   %0, [%1, %2]    @ outwc"                \
+                        : : "r" (v),                                    \
+                            "r" (PCIO_BASE + ((port) & ~0xff)),         \
+                             "Jr" (((port) & 0xff)));                   \
+                else                                                    \
+                        __asm__ __volatile__(                           \
+                        "strh   %0, [%1, #0]    @ outwc"                \
+                        : : "r" (v),                                    \
+                            "r" (PCIO_BASE + (port)));                  \
+        } else                                                          \
                __asm__ __volatile__(                                   \
                "strh   %0, [%1, #0]    @ outwc"                        \
-                : : "r" (v), "r" ((port)));     \
+                : : "r" (v), "r" ((port)));                             \
 })
 #define __inwc(port)                                                    \
 ({                                                                      \
        unsigned short result;                                          \
-        if (__PORT_PCIO((port)))                                        \
+        if (__PORT_PCIO((port))) {                                      \
-                __asm__ __volatile__(                                   \
+                if ((port) < 256 && (port) > -256 )                     \
-                "ldrh   %0, [%1, %2]    @ inwc"                         \
+                        __asm__ __volatile__(                           \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
+                        "ldrh   %0, [%1, %2]    @ inwc"                 \
-        else                                                            \
+                        : "=r" (result)                                 \
+                        : "r" (PCIO_BASE),                              \
+                          "Jr" ((port)));                               \
+                else if ((port) > 0)                                    \
+                        __asm__ __volatile__(                           \
+                        "ldrh   %0, [%1, %2]    @ inwc"                 \
+                        : "=r" (result)                                 \
+                        : "r" (PCIO_BASE + ((port) & ~0xff)),           \
+                          "Jr" (((port) & 0xff)));                      \
+                else                                                    \
+                        __asm__ __volatile__(                           \
+                        "ldrh   %0, [%1, #0]    @ inwc"                 \
+                        : "=r" (result)                                 \
+                        : "r" (PCIO_BASE + ((port))));                  \
+        } else                                                          \
                __asm__ __volatile__(                                   \
                "ldrh   %0, [%1, #0]    @ inwc"                         \
-                : "=r" (result) : "r" ((port)));                \
+                : "=r" (result) : "r" ((port)));                        \
-        result;                                         \
+        result;                                                         \
 })
 #define __outlc(value,port)                                             \
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 3380ab1d0749..6ab834a14c8e 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -28,9 +28,9 @@
 * and at 0x0C000000 for S3C2400
 */
 #ifdef CONFIG_CPU_S3C2400
-#define PHYS_OFFSET     (0x0C000000UL)
+#define PHYS_OFFSET     UL(0x0C000000)
 #else
-#define PHYS_OFFSET     (0x30000000UL)
+#define PHYS_OFFSET     UL(0x30000000)
 #endif
 /*
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 16f4c3cc1388..34360706e016 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -18,7 +18,9 @@
 *    10-Feb-2005 Ben Dooks         Fixed CAMDIVN address (Guillaume Gourat)
 *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA
 *    27-Aug-2005 Ben Dooks         Add clock-slow info
- */
+ *    20-Oct-2005 Ben Dooks         Fixed overflow in PLL (Guillaume Gourat)
+ *    20-Oct-2005 Ben Dooks         Add masks for DCLK (Guillaume Gourat)
+*/
 #ifndef __ASM_ARM_REGS_CLOCK
 #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
@@ -66,11 +68,16 @@
 #define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
 #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
 #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
+#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
+#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
 #define S3C2410_DCLKCON_DCLK1EN      (1<<16)
 #define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
 #define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
 #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
+#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
+#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
+#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
@@ -83,10 +90,13 @@
 #ifndef __ASSEMBLY__
+#include <asm/div64.h>
 static inline unsigned int
-s3c2410_get_pll(int pllval, int baseclk)
+s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 {
-        int mdiv, pdiv, sdiv;
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
        mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
        pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk)
        pdiv &= S3C2410_PLLCON_PDIVMASK;
        sdiv &= S3C2410_PLLCON_SDIVMASK;
-        return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
+        fvco = (uint64_t)baseclk * (mdiv + 8);
+        do_div(fvco, (pdiv + 2) << sdiv);
+        return (unsigned int)fvco;
 }
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 2053cbacffc3..7f1be48ad67e 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -20,6 +20,8 @@
 *    18-11-2004     BJD     Added S3C2440 AC97 controls
 *    10-Mar-2005    LCVR    Changed S3C2410_VA to S3C24XX_VA
 *    28-Mar-2005    LCVR    Fixed definition of GPB10
+ *    26-Oct-2005    BJD     Added generic configuration types
+ *    27-Nov-2005    LCVR    Added definitions to S3C2400 registers
 */
@@ -43,17 +45,26 @@
 /* general configuration options */
 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
+#define S3C2410_GPIO_INPUT   (0xFFFFFFF0)
+#define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
+#define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
+#define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* not available on A */
+#define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
 /* configure GPIO ports A..G */
 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
-/* port A - 22bits, zero in bit X makes pin X output
+/* port A - S3C2410: 22bits, zero in bit X makes pin X output
+ *          S3C2400: 18bits, zero in bit X makes pin X output
 * 1 makes port special function, this is default
 */
 #define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
 #define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
+#define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
+#define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
 #define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
 #define S3C2410_GPA0_OUT     (0<<0)
 #define S3C2410_GPA0_ADDR0   (1<<0)
@@ -97,34 +108,42 @@
 #define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
 #define S3C2410_GPA10_OUT    (0<<10)
 #define S3C2410_GPA10_ADDR25 (1<<10)
+#define S3C2400_GPA10_SCKE   (1<<10)
 #define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
 #define S3C2410_GPA11_OUT    (0<<11)
 #define S3C2410_GPA11_ADDR26 (1<<11)
+#define S3C2400_GPA11_nCAS0  (1<<11)
 #define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
 #define S3C2410_GPA12_OUT    (0<<12)
 #define S3C2410_GPA12_nGCS1  (1<<12)
+#define S3C2400_GPA12_nCAS1  (1<<12)
 #define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
 #define S3C2410_GPA13_OUT    (0<<13)
 #define S3C2410_GPA13_nGCS2  (1<<13)
+#define S3C2400_GPA13_nGCS1  (1<<13)
 #define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
 #define S3C2410_GPA14_OUT    (0<<14)
 #define S3C2410_GPA14_nGCS3  (1<<14)
+#define S3C2400_GPA14_nGCS2  (1<<14)
 #define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
 #define S3C2410_GPA15_OUT    (0<<15)
 #define S3C2410_GPA15_nGCS4  (1<<15)
+#define S3C2400_GPA15_nGCS3  (1<<15)
 #define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
 #define S3C2410_GPA16_OUT    (0<<16)
 #define S3C2410_GPA16_nGCS5  (1<<16)
+#define S3C2400_GPA16_nGCS4  (1<<16)
 #define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
 #define S3C2410_GPA17_OUT    (0<<17)
 #define S3C2410_GPA17_CLE    (1<<17)
+#define S3C2400_GPA17_nGCS5  (1<<17)
 #define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
 #define S3C2410_GPA18_OUT    (0<<18)
@@ -146,10 +165,16 @@
 #define S3C2410_GPA22_OUT    (0<<22)
 #define S3C2410_GPA22_nFCE   (1<<22)
-/* 0x08 and 0x0c are reserved */
+/* 0x08 and 0x0c are reserved on S3C2410 */
-/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
+/* S3C2410:
+ * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
 *   00 = input, 01 = output, 10=special function, 11=reserved
+ * S3C2400:
+ * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
+ *   00 = input, 01 = output, 10=data, 11=special function
 * bit 0,1 = pin 0, 2,3= pin 1...
 *
 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
@@ -159,63 +184,113 @@
 #define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
 #define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
+#define S3C2400_GPBCON     S3C2410_GPIOREG(0x08)
+#define S3C2400_GPBDAT     S3C2410_GPIOREG(0x0C)
+#define S3C2400_GPBUP      S3C2410_GPIOREG(0x10)
 /* no i/o pin in port b can have value 3! */
 #define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
 #define S3C2410_GPB0_INP     (0x00 << 0)
 #define S3C2410_GPB0_OUTP    (0x01 << 0)
 #define S3C2410_GPB0_TOUT0   (0x02 << 0)
+#define S3C2400_GPB0_DATA16  (0x02 << 0)
 #define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
 #define S3C2410_GPB1_INP     (0x00 << 2)
 #define S3C2410_GPB1_OUTP    (0x01 << 2)
 #define S3C2410_GPB1_TOUT1   (0x02 << 2)
+#define S3C2400_GPB1_DATA17  (0x02 << 2)
 #define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
 #define S3C2410_GPB2_INP     (0x00 << 4)
 #define S3C2410_GPB2_OUTP    (0x01 << 4)
 #define S3C2410_GPB2_TOUT2   (0x02 << 4)
+#define S3C2400_GPB2_DATA18  (0x02 << 4)
+#define S3C2400_GPB2_TCLK1   (0x03 << 4)
 #define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
 #define S3C2410_GPB3_INP     (0x00 << 6)
 #define S3C2410_GPB3_OUTP    (0x01 << 6)
 #define S3C2410_GPB3_TOUT3   (0x02 << 6)
+#define S3C2400_GPB3_DATA19  (0x02 << 6)
+#define S3C2400_GPB3_TXD1    (0x03 << 6)
 #define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
 #define S3C2410_GPB4_INP     (0x00 << 8)
 #define S3C2410_GPB4_OUTP    (0x01 << 8)
 #define S3C2410_GPB4_TCLK0   (0x02 << 8)
+#define S3C2400_GPB4_DATA20  (0x02 << 8)
 #define S3C2410_GPB4_MASK    (0x03 << 8)
+#define S3C2400_GPB4_RXD1    (0x03 << 8)
+#define S3C2400_GPB4_MASK    (0x03 << 8)
 #define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
 #define S3C2410_GPB5_INP     (0x00 << 10)
 #define S3C2410_GPB5_OUTP    (0x01 << 10)
 #define S3C2410_GPB5_nXBACK  (0x02 << 10)
+#define S3C2400_GPB5_DATA21  (0x02 << 10)
+#define S3C2400_GPB5_nCTS1   (0x03 << 10)
 #define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
 #define S3C2410_GPB6_INP     (0x00 << 12)
 #define S3C2410_GPB6_OUTP    (0x01 << 12)
 #define S3C2410_GPB6_nXBREQ  (0x02 << 12)
+#define S3C2400_GPB6_DATA22  (0x02 << 12)
+#define S3C2400_GPB6_nRTS1   (0x03 << 12)
 #define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
 #define S3C2410_GPB7_INP     (0x00 << 14)
 #define S3C2410_GPB7_OUTP    (0x01 << 14)
 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
+#define S3C2400_GPB7_DATA23  (0x02 << 14)
 #define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
 #define S3C2410_GPB8_INP     (0x00 << 16)
 #define S3C2410_GPB8_OUTP    (0x01 << 16)
 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
+#define S3C2400_GPB8_DATA24  (0x02 << 16)
 #define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
 #define S3C2410_GPB9_INP     (0x00 << 18)
 #define S3C2410_GPB9_OUTP    (0x01 << 18)
 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
+#define S3C2400_GPB9_DATA25  (0x02 << 18)
+#define S3C2400_GPB9_I2SSDI  (0x03 << 18)
 #define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
 #define S3C2410_GPB10_INP    (0x00 << 20)
 #define S3C2410_GPB10_OUTP   (0x01 << 20)
 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
+#define S3C2400_GPB10_DATA26 (0x02 << 20)
+#define S3C2400_GPB10_nSS    (0x03 << 20)
+#define S3C2400_GPB11        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
+#define S3C2400_GPB11_INP    (0x00 << 22)
+#define S3C2400_GPB11_OUTP   (0x01 << 22)
+#define S3C2400_GPB11_DATA27 (0x02 << 22)
+#define S3C2400_GPB12        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
+#define S3C2400_GPB12_INP    (0x00 << 24)
+#define S3C2400_GPB12_OUTP   (0x01 << 24)
+#define S3C2400_GPB12_DATA28 (0x02 << 24)
+#define S3C2400_GPB13        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
+#define S3C2400_GPB13_INP    (0x00 << 26)
+#define S3C2400_GPB13_OUTP   (0x01 << 26)
+#define S3C2400_GPB13_DATA29 (0x02 << 26)
+#define S3C2400_GPB14        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
+#define S3C2400_GPB14_INP    (0x00 << 28)
+#define S3C2400_GPB14_OUTP   (0x01 << 28)
+#define S3C2400_GPB14_DATA30 (0x02 << 28)
+#define S3C2400_GPB15        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
+#define S3C2400_GPB15_INP    (0x00 << 30)
+#define S3C2400_GPB15_OUTP   (0x01 << 30)
+#define S3C2400_GPB15_DATA31 (0x02 << 30)
+#define S3C2410_GPB_PUPDIS(x)  (1<<(x))
 /* Port C consits of 16 GPIO/Special function
 *
@@ -227,150 +302,193 @@
 #define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
 #define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
+#define S3C2400_GPCCON     S3C2410_GPIOREG(0x14)
+#define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
+#define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
 #define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
 #define S3C2410_GPC0_INP        (0x00 << 0)
 #define S3C2410_GPC0_OUTP       (0x01 << 0)
 #define S3C2410_GPC0_LEND       (0x02 << 0)
+#define S3C2400_GPC0_VD0        (0x02 << 0)
 #define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
 #define S3C2410_GPC1_INP        (0x00 << 2)
 #define S3C2410_GPC1_OUTP       (0x01 << 2)
 #define S3C2410_GPC1_VCLK       (0x02 << 2)
+#define S3C2400_GPC1_VD1        (0x02 << 2)
 #define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
 #define S3C2410_GPC2_INP        (0x00 << 4)
 #define S3C2410_GPC2_OUTP       (0x01 << 4)
 #define S3C2410_GPC2_VLINE      (0x02 << 4)
+#define S3C2400_GPC2_VD2        (0x02 << 4)
 #define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
 #define S3C2410_GPC3_INP        (0x00 << 6)
 #define S3C2410_GPC3_OUTP       (0x01 << 6)
 #define S3C2410_GPC3_VFRAME     (0x02 << 6)
+#define S3C2400_GPC3_VD3        (0x02 << 6)
 #define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
 #define S3C2410_GPC4_INP        (0x00 << 8)
 #define S3C2410_GPC4_OUTP       (0x01 << 8)
 #define S3C2410_GPC4_VM         (0x02 << 8)
+#define S3C2400_GPC4_VD4        (0x02 << 8)
 #define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
 #define S3C2410_GPC5_INP        (0x00 << 10)
 #define S3C2410_GPC5_OUTP       (0x01 << 10)
 #define S3C2410_GPC5_LCDVF0     (0x02 << 10)
+#define S3C2400_GPC5_VD5        (0x02 << 10)
 #define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
 #define S3C2410_GPC6_INP        (0x00 << 12)
 #define S3C2410_GPC6_OUTP       (0x01 << 12)
 #define S3C2410_GPC6_LCDVF1     (0x02 << 12)
+#define S3C2400_GPC6_VD6        (0x02 << 12)
 #define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
 #define S3C2410_GPC7_INP        (0x00 << 14)
 #define S3C2410_GPC7_OUTP       (0x01 << 14)
 #define S3C2410_GPC7_LCDVF2     (0x02 << 14)
+#define S3C2400_GPC7_VD7        (0x02 << 14)
 #define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
 #define S3C2410_GPC8_INP        (0x00 << 16)
 #define S3C2410_GPC8_OUTP       (0x01 << 16)
 #define S3C2410_GPC8_VD0        (0x02 << 16)
+#define S3C2400_GPC8_VD8        (0x02 << 16)
 #define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
 #define S3C2410_GPC9_INP        (0x00 << 18)
 #define S3C2410_GPC9_OUTP       (0x01 << 18)
 #define S3C2410_GPC9_VD1        (0x02 << 18)
+#define S3C2400_GPC9_VD9        (0x02 << 18)
 #define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
 #define S3C2410_GPC10_INP       (0x00 << 20)
 #define S3C2410_GPC10_OUTP      (0x01 << 20)
 #define S3C2410_GPC10_VD2       (0x02 << 20)
+#define S3C2400_GPC10_VD10      (0x02 << 20)
 #define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
 #define S3C2410_GPC11_INP       (0x00 << 22)
 #define S3C2410_GPC11_OUTP      (0x01 << 22)
 #define S3C2410_GPC11_VD3       (0x02 << 22)
+#define S3C2400_GPC11_VD11      (0x02 << 22)
 #define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
 #define S3C2410_GPC12_INP       (0x00 << 24)
 #define S3C2410_GPC12_OUTP      (0x01 << 24)
 #define S3C2410_GPC12_VD4       (0x02 << 24)
+#define S3C2400_GPC12_VD12      (0x02 << 24)
 #define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
 #define S3C2410_GPC13_INP       (0x00 << 26)
 #define S3C2410_GPC13_OUTP      (0x01 << 26)
 #define S3C2410_GPC13_VD5       (0x02 << 26)
+#define S3C2400_GPC13_VD13      (0x02 << 26)
 #define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
 #define S3C2410_GPC14_INP       (0x00 << 28)
 #define S3C2410_GPC14_OUTP      (0x01 << 28)
 #define S3C2410_GPC14_VD6       (0x02 << 28)
+#define S3C2400_GPC14_VD14      (0x02 << 28)
 #define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
 #define S3C2410_GPC15_INP       (0x00 << 30)
 #define S3C2410_GPC15_OUTP      (0x01 << 30)
 #define S3C2410_GPC15_VD7       (0x02 << 30)
+#define S3C2400_GPC15_VD15      (0x02 << 30)
+#define S3C2410_GPC_PUPDIS(x)  (1<<(x))
-/* Port D consists of 16 GPIO/Special function
+/*
+ * S3C2410: Port D consists of 16 GPIO/Special function
 *
 * almost identical setup to port b, but the special functions are mostly
 * to do with the video system's data.
+ *
+ * S3C2400: Port D consists of 11 GPIO/Special function
+ *
+ * almost identical setup to port c
 */
 #define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
 #define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
 #define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
+#define S3C2400_GPDCON     S3C2410_GPIOREG(0x20)
+#define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
+#define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
 #define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
 #define S3C2410_GPD0_INP        (0x00 << 0)
 #define S3C2410_GPD0_OUTP       (0x01 << 0)
 #define S3C2410_GPD0_VD8        (0x02 << 0)
+#define S3C2400_GPD0_VFRAME     (0x02 << 0)
 #define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
 #define S3C2410_GPD1_INP        (0x00 << 2)
 #define S3C2410_GPD1_OUTP       (0x01 << 2)
 #define S3C2410_GPD1_VD9        (0x02 << 2)
+#define S3C2400_GPD1_VM         (0x02 << 2)
 #define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
 #define S3C2410_GPD2_INP        (0x00 << 4)
 #define S3C2410_GPD2_OUTP       (0x01 << 4)
 #define S3C2410_GPD2_VD10       (0x02 << 4)
+#define S3C2400_GPD2_VLINE      (0x02 << 4)
 #define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
 #define S3C2410_GPD3_INP        (0x00 << 6)
 #define S3C2410_GPD3_OUTP       (0x01 << 6)
 #define S3C2410_GPD3_VD11       (0x02 << 6)
+#define S3C2400_GPD3_VCLK       (0x02 << 6)
 #define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
 #define S3C2410_GPD4_INP        (0x00 << 8)
 #define S3C2410_GPD4_OUTP       (0x01 << 8)
 #define S3C2410_GPD4_VD12       (0x02 << 8)
+#define S3C2400_GPD4_LEND       (0x02 << 8)
 #define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
 #define S3C2410_GPD5_INP        (0x00 << 10)
 #define S3C2410_GPD5_OUTP       (0x01 << 10)
 #define S3C2410_GPD5_VD13       (0x02 << 10)
+#define S3C2400_GPD5_TOUT0      (0x02 << 10)
 #define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
 #define S3C2410_GPD6_INP        (0x00 << 12)
 #define S3C2410_GPD6_OUTP       (0x01 << 12)
 #define S3C2410_GPD6_VD14       (0x02 << 12)
+#define S3C2400_GPD6_TOUT1      (0x02 << 12)
 #define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
 #define S3C2410_GPD7_INP        (0x00 << 14)
 #define S3C2410_GPD7_OUTP       (0x01 << 14)
 #define S3C2410_GPD7_VD15       (0x02 << 14)
+#define S3C2400_GPD7_TOUT2      (0x02 << 14)
 #define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
 #define S3C2410_GPD8_INP        (0x00 << 16)
 #define S3C2410_GPD8_OUTP       (0x01 << 16)
 #define S3C2410_GPD8_VD16       (0x02 << 16)
+#define S3C2400_GPD8_TOUT3      (0x02 << 16)
 #define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
 #define S3C2410_GPD9_INP        (0x00 << 18)
 #define S3C2410_GPD9_OUTP       (0x01 << 18)
 #define S3C2410_GPD9_VD17       (0x02 << 18)
+#define S3C2400_GPD9_TCLK0      (0x02 << 18)
+#define S3C2410_GPD9_MASK       (0x03 << 18)
 #define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
 #define S3C2410_GPD10_INP       (0x00 << 20)
 #define S3C2410_GPD10_OUTP      (0x01 << 20)
 #define S3C2410_GPD10_VD18      (0x02 << 20)
+#define S3C2400_GPD10_nWAIT     (0x02 << 20)
 #define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
 #define S3C2410_GPD11_INP       (0x00 << 22)
@@ -397,37 +515,56 @@
 #define S3C2410_GPD15_OUTP      (0x01 << 30)
 #define S3C2410_GPD15_VD23      (0x02 << 30)
-/* Port E consists of 16 GPIO/Special function
+#define S3C2410_GPD_PUPDIS(x)  (1<<(x))
+/* S3C2410:
+ * Port E consists of 16 GPIO/Special function
 *
 * again, the same as port B, but dealing with I2S, SDI, and
 * more miscellaneous functions
+ *
+ * S3C2400:
+ * Port E consists of 12 GPIO/Special function
+ *
+ * GPIO / interrupt inputs
 */
 #define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
 #define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
 #define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
+#define S3C2400_GPECON     S3C2410_GPIOREG(0x2C)
+#define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
+#define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
 #define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
 #define S3C2410_GPE0_INP       (0x00 << 0)
 #define S3C2410_GPE0_OUTP      (0x01 << 0)
 #define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
+#define S3C2400_GPE0_EINT0     (0x02 << 0)
 #define S3C2410_GPE0_MASK      (0x03 << 0)
 #define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
 #define S3C2410_GPE1_INP       (0x00 << 2)
 #define S3C2410_GPE1_OUTP      (0x01 << 2)
 #define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
+#define S3C2400_GPE1_EINT1     (0x02 << 2)
+#define S3C2400_GPE1_nSS       (0x03 << 2)
 #define S3C2410_GPE1_MASK      (0x03 << 2)
 #define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
 #define S3C2410_GPE2_INP       (0x00 << 4)
 #define S3C2410_GPE2_OUTP      (0x01 << 4)
 #define S3C2410_GPE2_CDCLK     (0x02 << 4)
+#define S3C2400_GPE2_EINT2     (0x02 << 4)
+#define S3C2400_GPE2_I2SSDI    (0x03 << 4)
 #define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
 #define S3C2410_GPE3_INP       (0x00 << 6)
 #define S3C2410_GPE3_OUTP      (0x01 << 6)
 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
+#define S3C2400_GPE3_EINT3     (0x02 << 6)
+#define S3C2400_GPE3_nCTS1     (0x03 << 6)
 #define S3C2410_GPE3_nSS0      (0x03 << 6)
 #define S3C2410_GPE3_MASK      (0x03 << 6)
@@ -435,6 +572,8 @@
 #define S3C2410_GPE4_INP       (0x00 << 8)
 #define S3C2410_GPE4_OUTP      (0x01 << 8)
 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
+#define S3C2400_GPE4_EINT4     (0x02 << 8)
+#define S3C2400_GPE4_nRTS1     (0x03 << 8)
 #define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 #define S3C2410_GPE4_MASK      (0x03 << 8)
@@ -442,36 +581,46 @@
 #define S3C2410_GPE5_INP       (0x00 << 10)
 #define S3C2410_GPE5_OUTP      (0x01 << 10)
 #define S3C2410_GPE5_SDCLK     (0x02 << 10)
+#define S3C2400_GPE5_EINT5     (0x02 << 10)
+#define S3C2400_GPE5_TCLK1     (0x03 << 10)
 #define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
 #define S3C2410_GPE6_INP       (0x00 << 12)
 #define S3C2410_GPE6_OUTP      (0x01 << 12)
 #define S3C2410_GPE6_SDCMD     (0x02 << 12)
+#define S3C2400_GPE6_EINT6     (0x02 << 12)
 #define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
 #define S3C2410_GPE7_INP       (0x00 << 14)
 #define S3C2410_GPE7_OUTP      (0x01 << 14)
 #define S3C2410_GPE7_SDDAT0    (0x02 << 14)
+#define S3C2400_GPE7_EINT7     (0x02 << 14)
 #define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
 #define S3C2410_GPE8_INP       (0x00 << 16)
 #define S3C2410_GPE8_OUTP      (0x01 << 16)
 #define S3C2410_GPE8_SDDAT1    (0x02 << 16)
+#define S3C2400_GPE8_nXDACK0   (0x02 << 16)
 #define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
 #define S3C2410_GPE9_INP       (0x00 << 18)
 #define S3C2410_GPE9_OUTP      (0x01 << 18)
 #define S3C2410_GPE9_SDDAT2    (0x02 << 18)
+#define S3C2400_GPE9_nXDACK1   (0x02 << 18)
+#define S3C2400_GPE9_nXBACK    (0x03 << 18)
 #define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
 #define S3C2410_GPE10_INP      (0x00 << 20)
 #define S3C2410_GPE10_OUTP     (0x01 << 20)
 #define S3C2410_GPE10_SDDAT3   (0x02 << 20)
+#define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
 #define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
 #define S3C2410_GPE11_INP      (0x00 << 22)
 #define S3C2410_GPE11_OUTP     (0x01 << 22)
 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
+#define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
+#define S3C2400_GPE11_nXBREQ   (0x03 << 22)
 #define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
 #define S3C2410_GPE12_INP      (0x00 << 24)
@@ -503,7 +652,8 @@
 #define S3C2410_GPE_PUPDIS(x)  (1<<(x))
-/* Port F consists of 8 GPIO/Special function
+/* S3C2410:
+ * Port F consists of 8 GPIO/Special function
 *
 * GPIO / interrupt inputs
 *
@@ -511,100 +661,141 @@
 *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
 *
 * pull up works like all other ports.
+ *
+ * S3C2400:
+ * Port F consists of 7 GPIO/Special function
+ *
+ * GPIO/serial/misc pins
 */
 #define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
 #define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
 #define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
+#define S3C2400_GPFCON     S3C2410_GPIOREG(0x38)
+#define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
+#define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
 #define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
 #define S3C2410_GPF0_INP    (0x00 << 0)
 #define S3C2410_GPF0_OUTP   (0x01 << 0)
 #define S3C2410_GPF0_EINT0  (0x02 << 0)
+#define S3C2400_GPF0_RXD0   (0x02 << 0)
 #define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
 #define S3C2410_GPF1_INP    (0x00 << 2)
 #define S3C2410_GPF1_OUTP   (0x01 << 2)
 #define S3C2410_GPF1_EINT1  (0x02 << 2)
+#define S3C2400_GPF1_RXD1   (0x02 << 2)
+#define S3C2400_GPF1_IICSDA (0x03 << 2)
 #define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
 #define S3C2410_GPF2_INP    (0x00 << 4)
 #define S3C2410_GPF2_OUTP   (0x01 << 4)
 #define S3C2410_GPF2_EINT2  (0x02 << 4)
+#define S3C2400_GPF2_TXD0   (0x02 << 4)
 #define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
 #define S3C2410_GPF3_INP    (0x00 << 6)
 #define S3C2410_GPF3_OUTP   (0x01 << 6)
 #define S3C2410_GPF3_EINT3  (0x02 << 6)
+#define S3C2400_GPF3_TXD1   (0x02 << 6)
+#define S3C2400_GPF3_IICSCL (0x03 << 6)
 #define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
 #define S3C2410_GPF4_INP    (0x00 << 8)
 #define S3C2410_GPF4_OUTP   (0x01 << 8)
 #define S3C2410_GPF4_EINT4  (0x02 << 8)
+#define S3C2400_GPF4_nRTS0  (0x02 << 8)
+#define S3C2400_GPF4_nXBACK (0x03 << 8)
 #define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
 #define S3C2410_GPF5_INP    (0x00 << 10)
 #define S3C2410_GPF5_OUTP   (0x01 << 10)
 #define S3C2410_GPF5_EINT5  (0x02 << 10)
+#define S3C2400_GPF5_nCTS0  (0x02 << 10)
+#define S3C2400_GPF5_nXBREQ (0x03 << 10)
 #define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
 #define S3C2410_GPF6_INP    (0x00 << 12)
 #define S3C2410_GPF6_OUTP   (0x01 << 12)
 #define S3C2410_GPF6_EINT6  (0x02 << 12)
+#define S3C2400_GPF6_CLKOUT (0x02 << 12)
 #define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
 #define S3C2410_GPF7_INP    (0x00 << 14)
 #define S3C2410_GPF7_OUTP   (0x01 << 14)
 #define S3C2410_GPF7_EINT7  (0x02 << 14)
-/* Port G consists of 8 GPIO/IRQ/Special function
+#define S3C2410_GPF_PUPDIS(x)  (1<<(x))
+/* S3C2410:
+ * Port G consists of 8 GPIO/IRQ/Special function
 *
 * GPGCON has 2 bits for each of the input pins on port F
 *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 *
 * pull up works like all other ports.
+ *
+ * S3C2400:
+ * Port G consists of 10 GPIO/Special function
 */
 #define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
 #define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
 #define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
+#define S3C2400_GPGCON     S3C2410_GPIOREG(0x44)
+#define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
+#define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
 #define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
 #define S3C2410_GPG0_INP      (0x00 << 0)
 #define S3C2410_GPG0_OUTP     (0x01 << 0)
 #define S3C2410_GPG0_EINT8    (0x02 << 0)
+#define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
 #define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
 #define S3C2410_GPG1_INP      (0x00 << 2)
 #define S3C2410_GPG1_OUTP     (0x01 << 2)
 #define S3C2410_GPG1_EINT9    (0x02 << 2)
+#define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
 #define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
 #define S3C2410_GPG2_INP      (0x00 << 4)
 #define S3C2410_GPG2_OUTP     (0x01 << 4)
 #define S3C2410_GPG2_EINT10   (0x02 << 4)
+#define S3C2400_GPG2_CDCLK    (0x02 << 4)
 #define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
 #define S3C2410_GPG3_INP      (0x00 << 6)
 #define S3C2410_GPG3_OUTP     (0x01 << 6)
 #define S3C2410_GPG3_EINT11   (0x02 << 6)
+#define S3C2400_GPG3_I2SSDO   (0x02 << 6)
+#define S3C2400_GPG3_I2SSDI   (0x03 << 6)
 #define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
 #define S3C2410_GPG4_INP      (0x00 << 8)
 #define S3C2410_GPG4_OUTP     (0x01 << 8)
 #define S3C2410_GPG4_EINT12   (0x02 << 8)
+#define S3C2400_GPG4_MMCCLK   (0x02 << 8)
+#define S3C2400_GPG4_I2SSDI   (0x03 << 8)
 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
 #define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
 #define S3C2410_GPG5_INP      (0x00 << 10)
 #define S3C2410_GPG5_OUTP     (0x01 << 10)
 #define S3C2410_GPG5_EINT13   (0x02 << 10)
+#define S3C2400_GPG5_MMCCMD   (0x02 << 10)
+#define S3C2400_GPG5_IICSDA   (0x03 << 10)
 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
 #define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
 #define S3C2410_GPG6_INP      (0x00 << 12)
 #define S3C2410_GPG6_OUTP     (0x01 << 12)
 #define S3C2410_GPG6_EINT14   (0x02 << 12)
+#define S3C2400_GPG6_MMCDAT   (0x02 << 12)
+#define S3C2400_GPG6_IICSCL   (0x03 << 12)
 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
 #define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
@@ -612,16 +803,22 @@
 #define S3C2410_GPG7_OUTP     (0x01 << 14)
 #define S3C2410_GPG7_EINT15   (0x02 << 14)
 #define S3C2410_GPG7_SPICLK1  (0x03 << 14)
+#define S3C2400_GPG7_SPIMISO  (0x02 << 14)
+#define S3C2400_GPG7_IICSDA   (0x03 << 14)
 #define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
 #define S3C2410_GPG8_INP      (0x00 << 16)
 #define S3C2410_GPG8_OUTP     (0x01 << 16)
 #define S3C2410_GPG8_EINT16   (0x02 << 16)
+#define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
+#define S3C2400_GPG8_IICSCL   (0x03 << 16)
 #define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
 #define S3C2410_GPG9_INP      (0x00 << 18)
 #define S3C2410_GPG9_OUTP     (0x01 << 18)
 #define S3C2410_GPG9_EINT17   (0x02 << 18)
+#define S3C2400_GPG9_SPICLK   (0x02 << 18)
+#define S3C2400_GPG9_MMCCLK   (0x03 << 18)
 #define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
 #define S3C2410_GPG10_INP     (0x00 << 20)
@@ -731,19 +928,27 @@
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 /* miscellaneous control */
+#define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
 #define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
 /* see clock.h for dclk definitions */
 /* pullup control on databus */
-#define S3C2410_MISCCR_SPUCR_HEN    (0)
+#define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
 #define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
-#define S3C2410_MISCCR_SPUCR_LEN    (0)
+#define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
 #define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
-#define S3C2410_MISCCR_USBDEV       (0)
+#define S3C2400_MISCCR_SPUCR_LEN    (0<<0)
+#define S3C2400_MISCCR_SPUCR_LDIS   (1<<0)
+#define S3C2400_MISCCR_SPUCR_HEN    (0<<1)
+#define S3C2400_MISCCR_SPUCR_HDIS   (1<<1)
+#define S3C2400_MISCCR_HZ_STOPEN    (0<<2)
+#define S3C2400_MISCCR_HZ_STOPPREV  (1<<2)
+#define S3C2410_MISCCR_USBDEV       (0<<3)
 #define S3C2410_MISCCR_USBHOST      (1<<3)
 #define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
@@ -779,7 +984,7 @@
 *
 * Samsung datasheet p9-25
 */
+#define S3C2400_EXTINT0    S3C2410_GPIOREG(0x58)
 #define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
 #define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
 #define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
@@ -827,5 +1032,21 @@
 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
 #define S3C2410_GSTATUS2_PONRESET  (1<<0)
+/* open drain control register */
+#define S3C2400_OPENCR     S3C2410_GPIOREG(0x50)
+#define S3C2400_OPENCR_OPC_RXD1DIS  (0<<0)
+#define S3C2400_OPENCR_OPC_RXD1EN   (1<<0)
+#define S3C2400_OPENCR_OPC_TXD1DIS  (0<<1)
+#define S3C2400_OPENCR_OPC_TXD1EN   (1<<1)
+#define S3C2400_OPENCR_OPC_CMDDIS   (0<<2)
+#define S3C2400_OPENCR_OPC_CMDEN    (1<<2)
+#define S3C2400_OPENCR_OPC_DATDIS   (0<<3)
+#define S3C2400_OPENCR_OPC_DATEN    (1<<3)
+#define S3C2400_OPENCR_OPC_MISODIS  (0<<4)
+#define S3C2400_OPENCR_OPC_MISOEN   (1<<4)
+#define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
+#define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
 #endif  /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index fdd62e8cd6cb..7fdde9b91cb4 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -55,6 +55,7 @@
 #define S3C2410_IISMOD_16FS       (0<<0)
 #define S3C2410_IISMOD_32FS       (1<<0)
 #define S3C2410_IISMOD_48FS       (2<<0)
+#define S3C2410_IISMOD_FS_MASK    (3<<0)
 #define S3C2410_IISPSR          (0x08)
 #define S3C2410_IISPSR_INTMASK  (31<<5)
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index d7a4a8354fa9..ddd1578a7ee0 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -116,6 +116,8 @@ putstr(const char *ptr)
        }
 }
+#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
 /* CONFIG_S3C2410_BOOT_WATCHDOG
 *
 * Simple boot-time watchdog setup, to reboot the system if there is
@@ -126,8 +128,6 @@ putstr(const char *ptr)
 #define WDOG_COUNT (0xff00)
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
 static inline void arch_decomp_wdog(void)
 {
        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
@@ -145,6 +145,24 @@ static void arch_decomp_wdog_start(void)
 #define arch_decomp_wdog()
 #endif
+#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+        while(1);
+}
+#define arch_error arch_decomp_error
+#endif
 static void error(char *err);
 static void
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index 19c3b1e186bb..28711aaa4968 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -22,13 +22,6 @@
 /*
- * We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for 
- * in*()/out*() macros to be usable for all cases.
- */
-#define PCIO_BASE               0
-/*
 * SA1100 internal I/O mappings
 *
 * We have the following mapping:
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
index 7d969ffbd3bb..040ccde7a11e 100644
--- a/include/asm-arm/arch-sa1100/io.h
+++ b/include/asm-arm/arch-sa1100/io.h
@@ -16,7 +16,11 @@
 * We don't actually have real ISA nor PCI buses, but there is so many 
 * drivers out there that might just work if we fake them...
 */
-#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 8743ff5c1b23..018a9f0e3986 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -13,25 +13,15 @@
 /*
 * Physical DRAM offset is 0xc0000000 on the SA1100
 */
-#define PHYS_OFFSET     (0xc0000000UL)
+#define PHYS_OFFSET     UL(0xc0000000)
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_SA1111
-static inline void
+void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
-__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
-{
-        unsigned int sz = SZ_1M >> PAGE_SHIFT;
-        if (node != 0)
-                sz = 0;
-        size[1] = size[0] - sz;
-        size[0] = sz;
-}
 #define arch_adjust_zones(node, size, holes) \
-        __arch_adjust_zones(node, size, holes)
+        sa1111_adjust_zones(node, size, holes)
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_1M - 1)
diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h
index 6f52118ba1a4..0f0612f79b2b 100644
--- a/include/asm-arm/arch-sa1100/system.h
+++ b/include/asm-arm/arch-sa1100/system.h
@@ -4,6 +4,7 @@
 * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
 */
 #include <linux/config.h>
+#include <asm/hardware.h>
 static inline void arch_idle(void)
 {
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
index 5e6ed0038b2b..87ffa27f2962 100644
--- a/include/asm-arm/arch-shark/io.h
+++ b/include/asm-arm/arch-shark/io.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
+#include <asm/hardware.h>
 #define IO_SPACE_LIMIT 0xffffffff
 /*
diff --git a/include/asm-arm/arch-shark/memory.h b/include/asm-arm/arch-shark/memory.h
index 8ff956d25463..95a29b4bc5d0 100644
--- a/include/asm-arm/arch-shark/memory.h
+++ b/include/asm-arm/arch-shark/memory.h
@@ -15,7 +15,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x08000000UL)
+#define PHYS_OFFSET     UL(0x08000000)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h
index 9f895bf61494..47e904cf25c7 100644
--- a/include/asm-arm/arch-versatile/io.h
+++ b/include/asm-arm/arch-versatile/io.h
@@ -22,7 +22,11 @@
 #define IO_SPACE_LIMIT 0xffffffff
-#define __io(a)                 ((void __iomem *)(a))
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a) __io(a)
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h
index 7b8b7cc422fa..a9370976cc5e 100644
--- a/include/asm-arm/arch-versatile/memory.h
+++ b/include/asm-arm/arch-versatile/memory.h
@@ -23,7 +23,7 @@
 /*
 * Physical DRAM offset.
 */
-#define PHYS_OFFSET     (0x00000000UL)
+#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index 69a28f96bee2..f31ac92b6c7f 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -83,10 +83,13 @@
 * Save the current IRQ state and disable IRQs.  Note that this macro
 * assumes FIQs are enabled, and that the processor is in SVC mode.
 */
-        .macro  save_and_disable_irqs, oldcpsr, temp
+        .macro  save_and_disable_irqs, oldcpsr
        mrs     \oldcpsr, cpsr
-        mov     \temp, #PSR_I_BIT | MODE_SVC
+#if __LINUX_ARM_ARCH__ >= 6
-        msr     cpsr_c, \temp
+        cpsid   i
+#else
+        msr     cpsr_c, #PSR_I_BIT | MODE_SVC
+#endif
        .endm
 /*
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index 2885972b0855..d586f65c8228 100644
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -12,6 +12,7 @@
 #define __ASM_ARM_ATOMIC_H
 #include <linux/config.h>
+#include <linux/compiler.h>
 typedef struct { volatile int counter; } atomic_t;
@@ -80,6 +81,24 @@ static inline int atomic_sub_return(int i, atomic_t *v)
        return result;
 }
+static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
+{
+        unsigned long oldval, res;
+        do {
+                __asm__ __volatile__("@ atomic_cmpxchg\n"
+                "ldrex  %1, [%2]\n"
+                "mov    %0, #0\n"
+                "teq    %1, %3\n"
+                "strexeq %0, %4, [%2]\n"
+                    : "=&r" (res), "=&r" (oldval)
+                    : "r" (&ptr->counter), "Ir" (old), "r" (new)
+                    : "cc");
+        } while (res);
+        return oldval;
+}
 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 {
        unsigned long tmp, tmp2;
@@ -131,6 +150,20 @@ static inline int atomic_sub_return(int i, atomic_t *v)
        return val;
 }
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+        int ret;
+        unsigned long flags;
+        local_irq_save(flags);
+        ret = v->counter;
+        if (likely(ret == old))
+                v->counter = new;
+        local_irq_restore(flags);
+        return ret;
+}
 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 {
        unsigned long flags;
@@ -142,6 +175,17 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 #endif /* __LINUX_ARM_ARCH__ */
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
+                c = old;
+        return c != u;
+}
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 #define atomic_add(i, v)        (void) atomic_add_return(i, v)
 #define atomic_inc(v)           (void) atomic_add_return(1, v)
 #define atomic_sub(i, v)        (void) atomic_sub_return(i, v)
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index aad7aad026b3..7399d431edfe 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -19,6 +19,7 @@
 #ifdef __KERNEL__
+#include <linux/compiler.h>
 #include <asm/system.h>
 #define smp_mb__before_clear_bit()      mb()
@@ -347,7 +348,6 @@ static inline unsigned long __ffs(unsigned long word)
 * the clz instruction for much better code efficiency.
 */
-static __inline__ int generic_fls(int x);
 #define fls(x) \
        ( __builtin_constant_p(x) ? generic_fls(x) : \
          ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
diff --git a/include/asm-arm/cpu.h b/include/asm-arm/cpu.h
index fcbdd40cb667..751bc7462074 100644
--- a/include/asm-arm/cpu.h
+++ b/include/asm-arm/cpu.h
@@ -16,6 +16,7 @@
 struct cpuinfo_arm {
        struct cpu      cpu;
 #ifdef CONFIG_SMP
+        struct task_struct *idle;
        unsigned int    loops_per_jiffy;
 #endif
 };
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index d62ade4e4cbb..e3e8541ee63b 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -70,7 +70,7 @@ static inline int dma_mapping_error(dma_addr_t dma_addr)
 * device-viewed address.
 */
 extern void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
+dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
 /**
 * dma_free_coherent - free memory allocated by dma_alloc_coherent
@@ -117,7 +117,7 @@ int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
 * device-viewed address.
 */
 extern void *
-dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
+dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
 #define dma_free_writecombine(dev,size,cpu_addr,handle) \
        dma_free_coherent(dev,size,cpu_addr,handle)
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index a1696ba238d3..7da97a937548 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -124,6 +124,8 @@ do { \
        if (((ex).e_flags & EF_ARM_EABI_MASK) || \
            ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \
                set_thread_flag(TIF_USING_IWMMXT); \
+        else \
+                clear_thread_flag(TIF_USING_IWMMXT); \
 } while (0)
 #endif
diff --git a/include/asm-arm/hardirq.h b/include/asm-arm/hardirq.h
index e5ccb6b8ff83..1cbb173bf5b1 100644
--- a/include/asm-arm/hardirq.h
+++ b/include/asm-arm/hardirq.h
@@ -8,6 +8,7 @@
 typedef struct {
        unsigned int __softirq_pending;
+        unsigned int local_timer_irqs;
 } ____cacheline_aligned irq_cpustat_t;
 #include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h
index ce4cf5c1c05d..6b8d73dc1ab0 100644
--- a/include/asm-arm/hardware/amba_clcd.h
+++ b/include/asm-arm/hardware/amba_clcd.h
@@ -22,7 +22,7 @@
 #define CLCD_UBAS               0x00000010
 #define CLCD_LBAS               0x00000014
-#ifndef CONFIG_ARCH_VERSATILE
+#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
 #define CLCD_IENB               0x00000018
 #define CLCD_CNTL               0x0000001c
 #else
diff --git a/include/asm-arm/hardware/amba_serial.h b/include/asm-arm/hardware/amba_serial.h
index 71770aa6389f..dc726ffccebd 100644
--- a/include/asm-arm/hardware/amba_serial.h
+++ b/include/asm-arm/hardware/amba_serial.h
@@ -50,6 +50,11 @@
 #define UART011_ICR             0x44    /* Interrupt clear register. */
 #define UART011_DMACR           0x48    /* DMA control register. */
+#define UART011_DR_OE           (1 << 11)
+#define UART011_DR_BE           (1 << 10)
+#define UART011_DR_PE           (1 << 9)
+#define UART011_DR_FE           (1 << 8)
 #define UART01x_RSR_OE          0x08
 #define UART01x_RSR_BE          0x04
 #define UART01x_RSR_PE          0x02
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h
new file mode 100644
index 000000000000..9903f60c84b7
--- /dev/null
+++ b/include/asm-arm/hardware/arm_scu.h
@@ -0,0 +1,13 @@
+#ifndef ASMARM_HARDWARE_ARM_SCU_H
+#define ASMARM_HARDWARE_ARM_SCU_H
+/*
+ * SCU registers
+ */
+#define SCU_CTRL                0x00
+#define SCU_CONFIG              0x04
+#define SCU_CPU_STATUS          0x08
+#define SCU_INVALIDATE          0x0c
+#define SCU_FPGA_REVISION       0x10
+#endif
diff --git a/include/asm-arm/hardware/dec21285.h b/include/asm-arm/hardware/dec21285.h
index 9049f0ddaecf..6685e3fb97b1 100644
--- a/include/asm-arm/hardware/dec21285.h
+++ b/include/asm-arm/hardware/dec21285.h
@@ -20,7 +20,7 @@
 #include <linux/config.h>
 #ifndef __ASSEMBLY__
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #define DC21285_IO(x)           ((volatile unsigned long *)(ARMCSR_BASE+(x)))
 #else
 #define DC21285_IO(x)           (x)
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
index 527404b5a8df..d37bf7443264 100644
--- a/include/asm-arm/hardware/scoop.h
+++ b/include/asm-arm/hardware/scoop.h
@@ -38,6 +38,8 @@
 struct scoop_config {
        unsigned short io_out;
        unsigned short io_dir;
+        unsigned short suspend_clr;
+        unsigned short suspend_set;
 };
 /* Structure for linking scoop devices to PCMCIA sockets */
@@ -50,8 +52,14 @@ struct scoop_pcmcia_dev {
        unsigned char keep_rd;
 };
-extern int scoop_num;
+struct scoop_pcmcia_config {
-extern struct scoop_pcmcia_dev *scoop_devs;
+        struct scoop_pcmcia_dev *devs;
+        int num_devs;
+        void (*pcmcia_init)(void);
+        void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
+};
+extern struct scoop_pcmcia_config *platform_scoop_config;
 void reset_scoop(struct device *dev);
 unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index cfa71a0dffb6..ae69db4a1010 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -26,7 +26,6 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
 /*
 * ISA I/O bus memory addresses are 1:1 with the physical address.
@@ -56,6 +55,12 @@ extern void __raw_readsl(void __iomem *addr, void *data, int longlen);
 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
 /*
+ * Architecture ioremap implementation.
+ */
+extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
+extern void __iounmap(void __iomem *addr);
+/*
 * Bad read/write accesses...
 */
 extern void __readwrite_bug(const char *fn);
@@ -136,9 +141,9 @@ extern void __readwrite_bug(const char *fn);
 /*
 * String version of IO memory access ops:
 */
-extern void _memcpy_fromio(void *, void __iomem *, size_t);
+extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
-extern void _memcpy_toio(void __iomem *, const void *, size_t);
+extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
-extern void _memset_io(void __iomem *, int, size_t);
+extern void _memset_io(volatile void __iomem *, int, size_t);
 #define mmiowb()
@@ -257,18 +262,15 @@ out:
 * ioremap takes a PCI memory address, as specified in
 * Documentation/IO-mapping.txt.
 */
-extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
-extern void __iounmap(void __iomem *addr);
 #ifndef __arch_ioremap
-#define ioremap(cookie,size)            __ioremap(cookie,size,0,1)
+#define ioremap(cookie,size)            __ioremap(cookie,size,0)
-#define ioremap_nocache(cookie,size)    __ioremap(cookie,size,0,1)
+#define ioremap_nocache(cookie,size)    __ioremap(cookie,size,0)
-#define ioremap_cached(cookie,size)     __ioremap(cookie,size,L_PTE_CACHEABLE,1)
+#define ioremap_cached(cookie,size)     __ioremap(cookie,size,L_PTE_CACHEABLE)
 #define iounmap(cookie)                 __iounmap(cookie)
 #else
-#define ioremap(cookie,size)            __arch_ioremap((cookie),(size),0,1)
+#define ioremap(cookie,size)            __arch_ioremap((cookie),(size),0)
-#define ioremap_nocache(cookie,size)    __arch_ioremap((cookie),(size),0,1)
+#define ioremap_nocache(cookie,size)    __arch_ioremap((cookie),(size),0)
-#define ioremap_cached(cookie,size)     __arch_ioremap((cookie),(size),L_PTE_CACHEABLE,1)
+#define ioremap_cached(cookie,size)     __arch_ioremap((cookie),(size),L_PTE_CACHEABLE)
 #define iounmap(cookie)                 __arch_iounmap(cookie)
 #endif
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
index f97912fbb10f..59975ee43cf1 100644
--- a/include/asm-arm/irq.h
+++ b/include/asm-arm/irq.h
@@ -47,5 +47,6 @@ struct irqaction;
 struct pt_regs;
 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
+extern void migrate_irqs(void);
 #endif
diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h
index f08dc8447913..852220eecdbc 100644
--- a/include/asm-arm/locks.h
+++ b/include/asm-arm/locks.h
@@ -103,7 +103,7 @@
        ({                                      \
        smp_mb();                               \
        __asm__ __volatile__(                   \
-        "@ up_op_read\n"                        \
+        "@ up_op_write\n"                       \
 "1:     ldrex   lr, [%0]\n"                     \
 "       adds    lr, lr, %1\n"                   \
 "       strex   ip, lr, [%0]\n"                 \
@@ -231,7 +231,7 @@
 #define __up_op_write(ptr,wake)                 \
        ({                                      \
        __asm__ __volatile__(                   \
-        "@ up_op_read\n"                        \
+        "@ up_op_write\n"                       \
 "       mrs     ip, cpsr\n"                     \
 "       orr     lr, ip, #128\n"                 \
 "       msr     cpsr_c, lr\n"                   \
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index 4fa95084a8c0..eb262e078c46 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -48,10 +48,11 @@ struct machine_desc {
 * Set of macros to define architecture features.  This is built into
 * a table by the linker.
 */
-#define MACHINE_START(_type,_name)              \
+#define MACHINE_START(_type,_name)                      \
-const struct machine_desc __mach_desc_##_type   \
+static const struct machine_desc __mach_desc_##_type    \
+ __attribute_used__                                     \
 __attribute__((__section__(".arch.info.init"))) = {    \
-        .nr             = MACH_TYPE_##_type,    \
+        .nr             = MACH_TYPE_##_type,            \
        .name           = _name,
 #define MACHINE_END                             \
diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h
index a92887d4b2cb..05b029ef6371 100644
--- a/include/asm-arm/mach/flash.h
+++ b/include/asm-arm/mach/flash.h
@@ -11,22 +11,27 @@
 #define ASMARM_MACH_FLASH_H
 struct mtd_partition;
+struct mtd_info;
 /*
 * map_name:    the map probe function name
+ * name:        flash device name (eg, as used with mtdparts=)
 * width:       width of mapped device
 * init:        method called at driver/device initialisation
 * exit:        method called at driver/device removal
 * set_vpp:     method called to enable or disable VPP
+ * mmcontrol:   method called to enable or disable Sync. Burst Read in OneNAND
 * parts:       optional array of mtd_partitions for static partitioning
 * nr_parts:    number of mtd_partitions for static partitoning
 */
 struct flash_platform_data {
        const char      *map_name;
+        const char      *name;
        unsigned int    width;
        int             (*init)(void);
        void            (*exit)(void);
        void            (*set_vpp)(int on);
+        void            (*mmcontrol)(struct mtd_info *mtd, int sync_read);
        struct mtd_partition *parts;
        unsigned int    nr_parts;
 };
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index 9ac47cf8d2e4..b338936bde4f 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -11,7 +11,7 @@
 */
 struct map_desc {
        unsigned long virtual;
-        unsigned long physical;
+        unsigned long pfn;
        unsigned long length;
        unsigned int type;
 };
@@ -27,6 +27,9 @@ struct meminfo;
 #define MT_ROM                  6
 #define MT_IXP2000_DEVICE       7
+#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
+#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
 extern void create_memmap_holes(struct meminfo *);
 extern void memtable_init(struct meminfo *);
 extern void iotable_init(struct map_desc *, int);
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index a8a933a775db..a547ee598c6c 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -12,6 +12,16 @@
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
+/*
+ * Allow for constants defined here to be used from assembly code
+ * by prepending the UL suffix only with actual C code compilation.
+ */
+#ifndef __ASSEMBLY__
+#define UL(x) (x##UL)
+#else
+#define UL(x) (x)
+#endif
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <asm/arch/memory.h>
@@ -21,20 +31,20 @@
 * TASK_SIZE - the maximum size of a user space task.
 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
 */
-#define TASK_SIZE               (0xbf000000UL)
+#define TASK_SIZE               UL(0xbf000000)
-#define TASK_UNMAPPED_BASE      (0x40000000UL)
+#define TASK_UNMAPPED_BASE      UL(0x40000000)
 #endif
 /*
 * The maximum size of a 26-bit user space task.
 */
-#define TASK_SIZE_26            (0x04000000UL)
+#define TASK_SIZE_26            UL(0x04000000)
 /*
 * Page offset: 3GB
 */
 #ifndef PAGE_OFFSET
-#define PAGE_OFFSET             (0xc0000000UL)
+#define PAGE_OFFSET             UL(0xc0000000)
 #endif
 /*
@@ -58,6 +68,13 @@
 #error Top of user space clashes with start of module space
 #endif
+/*
+ * The XIP kernel gets mapped at the bottom of the module vm area.
+ * Since we use sections to map it, this macro replaces the physical address
+ * with its virtual address while keeping offset from the base section.
+ */
+#define XIP_VIRT_ADDR(physaddr)  (MODULE_START + ((physaddr) & 0x000fffff))
 #ifndef __ASSEMBLY__
 /*
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 4af9c411c617..81c59facea3b 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARM_MMU_CONTEXT_H
 #define __ASM_ARM_MMU_CONTEXT_H
+#include <linux/compiler.h>
+#include <asm/cacheflush.h>
 #include <asm/proc-fns.h>
 #if __LINUX_ARM_ARCH__ >= 6
@@ -86,7 +88,8 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
                cpu_set(cpu, next->cpu_vm_mask);
                check_context(next);
                cpu_switch_mm(next->pgd, next);
-                cpu_clear(cpu, prev->cpu_vm_mask);
+                if (cache_is_vivt())
+                        cpu_clear(cpu, prev->cpu_vm_mask);
        }
 }
diff --git a/include/asm-arm/numnodes.h b/include/asm-arm/numnodes.h
index 5d2a1034a02e..8df36818ebc9 100644
--- a/include/asm-arm/numnodes.h
+++ b/include/asm-arm/numnodes.h
@@ -17,6 +17,8 @@
 #ifndef __ASM_ARM_NUMNODES_H
 #define __ASM_ARM_NUMNODES_H
+#include <asm/memory.h>
 #ifndef NODES_SHIFT
 # define NODES_SHIFT    2       /* Normally, Max 4 Nodes */
 #endif
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 366bafbdfbb1..5a0d19b466b0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -397,9 +397,6 @@ static inline pte_t *pmd_page_kernel(pmd_t pmd)
 #define pgd_clear(pgdp)         do { } while (0)
 #define set_pgd(pgd,pgdp)       do { } while (0)
-#define page_pte_prot(page,prot)        mk_pte(page, prot)
-#define page_pte(page)          mk_pte(page, __pgprot(0))
 /* to find an entry in a page-table-directory */
 #define pgd_index(addr)         ((addr) >> PGDIR_SHIFT)
diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h
index 60f33e6eb800..d5dc624f452a 100644
--- a/include/asm-arm/semaphore.h
+++ b/include/asm-arm/semaphore.h
@@ -24,8 +24,6 @@ struct semaphore {
        .wait   = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
 }
-#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INIT(name,1)
 #define __DECLARE_SEMAPHORE_GENERIC(name,count) \
        struct semaphore name = __SEMAPHORE_INIT(name,count)
@@ -49,11 +47,6 @@ static inline void init_MUTEX_LOCKED(struct semaphore *sem)
        sema_init(sem, 0);
 }
-static inline int sema_count(struct semaphore *sem)
-{
-        return atomic_read(&sem->count);
-}
 /*
 * special register calling convention
 */
diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h
index 760f6e65af05..ced69161917b 100644
--- a/include/asm-arm/signal.h
+++ b/include/asm-arm/signal.h
@@ -115,7 +115,6 @@ typedef unsigned long sigset_t;
 #ifdef __KERNEL__
 #define SA_TIMER                0x40000000
-#define SA_IRQNOMASK            0x08000000
 #endif
 #include <asm-generic/signal.h>
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index dbb4d859c586..5a72e50ca9fc 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -37,6 +37,11 @@ struct seq_file;
 extern void show_ipi_list(struct seq_file *p);
 /*
+ * Called from assembly code, this handles an IPI.
+ */
+asmlinkage void do_IPI(struct pt_regs *regs);
+/*
 * Move global data into per-processor storage.
 */
 extern void smp_store_cpu_info(unsigned int cpuid);
@@ -47,12 +52,23 @@ extern void smp_store_cpu_info(unsigned int cpuid);
 extern void smp_cross_call(cpumask_t callmap);
 /*
+ * Broadcast a timer interrupt to the other CPUs.
+ */
+extern void smp_send_timer(void);
+/*
 * Boot a secondary CPU, and assign it the specified idle task.
 * This also gives us the initial stack to use for this CPU.
 */
 extern int boot_secondary(unsigned int cpu, struct task_struct *);
 /*
+ * Called from platform specific assembly code, this is the
+ * secondary CPU entry point.
+ */
+asmlinkage void secondary_start_kernel(void);
+/*
 * Perform platform specific initialisation of the specified CPU.
 */
 extern void platform_secondary_init(unsigned int cpu);
@@ -66,4 +82,52 @@ struct secondary_data {
 };
 extern struct secondary_data secondary_data;
+extern int __cpu_disable(void);
+extern int mach_cpu_disable(unsigned int cpu);
+extern void __cpu_die(unsigned int cpu);
+extern void cpu_die(void);
+extern void platform_cpu_die(unsigned int cpu);
+extern int platform_cpu_kill(unsigned int cpu);
+extern void platform_cpu_enable(unsigned int cpu);
+#ifdef CONFIG_LOCAL_TIMERS
+/*
+ * Setup a local timer interrupt for a CPU.
+ */
+extern void local_timer_setup(unsigned int cpu);
+/*
+ * Stop a local timer interrupt.
+ */
+extern void local_timer_stop(unsigned int cpu);
+/*
+ * Platform provides this to acknowledge a local timer IRQ
+ */
+extern int local_timer_ack(void);
+#else
+static inline void local_timer_setup(unsigned int cpu)
+{
+}
+static inline void local_timer_stop(unsigned int cpu)
+{
+}
+#endif
+/*
+ * show local interrupt info
+ */
+extern void show_local_irqs(struct seq_file *);
+/*
+ * Called from assembly, this is the local timer IRQ handler
+ */
+asmlinkage void do_local_timer(struct pt_regs *);
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index cb4906b45555..43ad4e55878c 100644
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -30,6 +30,9 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
        __asm__ __volatile__(
 "1:     ldrex   %0, [%1]\n"
 "       teq     %0, #0\n"
+#ifdef CONFIG_CPU_32v6K
+"       wfene\n"
+#endif
 "       strexeq %0, %2, [%1]\n"
 "       teqeq   %0, #0\n"
 "       bne     1b"
@@ -65,7 +68,11 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
        smp_mb();
        __asm__ __volatile__(
-"       str     %1, [%0]"
+"       str     %1, [%0]\n"
+#ifdef CONFIG_CPU_32v6K
+"       mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
+"       sev"
+#endif
        :
        : "r" (&lock->lock), "r" (0)
        : "cc");
@@ -80,13 +87,16 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 */
 #define rwlock_is_locked(x)     (*((volatile unsigned int *)(x)) != 0)
-static inline void __raw_write_lock(rwlock_t *rw)
+static inline void __raw_write_lock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
        __asm__ __volatile__(
 "1:     ldrex   %0, [%1]\n"
 "       teq     %0, #0\n"
+#ifdef CONFIG_CPU_32v6K
+"       wfene\n"
+#endif
 "       strexeq %0, %2, [%1]\n"
 "       teq     %0, #0\n"
 "       bne     1b"
@@ -97,7 +107,7 @@ static inline void __raw_write_lock(rwlock_t *rw)
        smp_mb();
 }
-static inline int __raw_write_trylock(rwlock_t *rw)
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
        unsigned long tmp;
@@ -122,7 +132,11 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
        smp_mb();
        __asm__ __volatile__(
-        "str    %1, [%0]"
+        "str    %1, [%0]\n"
+#ifdef CONFIG_CPU_32v6K
+"       mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
+"       sev\n"
+#endif
        :
        : "r" (&rw->lock), "r" (0)
        : "cc");
@@ -148,6 +162,9 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
 "1:     ldrex   %0, [%2]\n"
 "       adds    %0, %0, #1\n"
 "       strexpl %1, %0, [%2]\n"
+#ifdef CONFIG_CPU_32v6K
+"       wfemi\n"
+#endif
 "       rsbpls  %0, %1, #0\n"
 "       bmi     1b"
        : "=&r" (tmp), "=&r" (tmp2)
@@ -157,7 +174,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
        smp_mb();
 }
-static inline void __raw_read_unlock(rwlock_t *rw)
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
 {
        unsigned long tmp, tmp2;
@@ -169,6 +186,11 @@ static inline void __raw_read_unlock(rwlock_t *rw)
 "       strex   %1, %0, [%2]\n"
 "       teq     %1, #0\n"
 "       bne     1b"
+#ifdef CONFIG_CPU_32v6K
+"\n     cmp     %0, #0\n"
+"       mcreq   p15, 0, %0, c7, c10, 4\n"
+"       seveq"
+#endif
        : "=&r" (tmp), "=&r" (tmp2)
        : "r" (&rw->lock)
        : "cc");
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 8efa4ebdcacb..5621d61ebc07 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -93,8 +93,6 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                       struct pt_regs *),
                     int sig, const char *name);
-#include <asm/proc-fns.h>
 #define xchg(ptr,x) \
        ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
@@ -102,6 +100,8 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
 extern asmlinkage void __backtrace(void);
 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
+struct mm_struct;
 extern void show_pte(struct mm_struct *mm, unsigned long addr);
 extern void __show_regs(struct pt_regs *);
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 8252a4cd860f..7c98557b717f 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -12,6 +12,7 @@
 #ifdef __KERNEL__
+#include <linux/compiler.h>
 #include <asm/fpstate.h>
 #define THREAD_SIZE_ORDER       1
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
index 9bb325c54645..f49bfb78c221 100644
--- a/include/asm-arm/tlb.h
+++ b/include/asm-arm/tlb.h
@@ -27,11 +27,7 @@
 */
 struct mmu_gather {
        struct mm_struct        *mm;
-        unsigned int            freed;
        unsigned int            fullmm;
-        unsigned int            flushes;
-        unsigned int            avoided_flushes;
 };
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -39,11 +35,9 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        int cpu = smp_processor_id();
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-        struct mmu_gather *tlb = &per_cpu(mmu_gathers, cpu);
        tlb->mm = mm;
-        tlb->freed = 0;
        tlb->fullmm = full_mm_flush;
        return tlb;
@@ -52,24 +46,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        struct mm_struct *mm = tlb->mm;
-        unsigned long freed = tlb->freed;
-        int rss = get_mm_counter(mm, rss);
-        if (rss < freed)
-                freed = rss;
-        add_mm_counter(mm, rss, -freed);
        if (tlb->fullmm)
-                flush_tlb_mm(mm);
+                flush_tlb_mm(tlb->mm);
        /* keep the page table cache within bounds */
        check_pgt_cache();
-}
-static inline unsigned int tlb_is_full_mm(struct mmu_gather *tlb)
+        put_cpu_var(mmu_gathers);
-{
-        return tlb->fullmm;
 }
 #define tlb_remove_tlb_entry(tlb,ptep,address)  do { } while (0)
diff --git a/include/asm-arm/uaccess.h b/include/asm-arm/uaccess.h
index a2fdad0138b3..064f0f5e8e2b 100644
--- a/include/asm-arm/uaccess.h
+++ b/include/asm-arm/uaccess.h
@@ -100,7 +100,6 @@ static inline void set_fs (mm_segment_t fs)
 extern int __get_user_1(void *);
 extern int __get_user_2(void *);
 extern int __get_user_4(void *);
-extern int __get_user_8(void *);
 extern int __get_user_bad(void);
 #define __get_user_x(__r2,__p,__e,__s,__i...)                           \
@@ -114,7 +113,7 @@ extern int __get_user_bad(void);
 #define get_user(x,p)                                                   \
        ({                                                              \
                const register typeof(*(p)) __user *__p asm("r0") = (p);\
-                register typeof(*(p)) __r2 asm("r2");                   \
+                register unsigned int __r2 asm("r2");                   \
                register int __e asm("r0");                             \
                switch (sizeof(*(__p))) {                               \
                case 1:                                                 \
@@ -126,12 +125,9 @@ extern int __get_user_bad(void);
                case 4:                                                 \
                        __get_user_x(__r2, __p, __e, 4, "lr");          \
                        break;                                          \
-                case 8:                                                 \
-                        __get_user_x(__r2, __p, __e, 8, "lr");          \
-                        break;                                          \
                default: __e = __get_user_bad(); break;                 \
                }                                                       \
-                x = __r2;                                               \
+                x = (typeof(*(p))) __r2;                                \
                __e;                                                    \
        })
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index c49df635a80f..d626e70faded 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -544,7 +544,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
 asmlinkage int sys_fork(struct pt_regs *regs);
 asmlinkage int sys_vfork(struct pt_regs *regs);
 asmlinkage int sys_pipe(unsigned long *fildes);
-asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
 struct sigaction;
 asmlinkage long sys_rt_sigaction(int sig,
                                const struct sigaction __user *act,