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-rw-r--r--include/asm-arm/arch-omap/board-apollon.h2
-rw-r--r--include/asm-arm/arch-omap/board-h2.h3
-rw-r--r--include/asm-arm/arch-omap/board-h3.h2
-rw-r--r--include/asm-arm/arch-omap/board-sx1.h8
-rw-r--r--include/asm-arm/arch-omap/common.h11
-rw-r--r--include/asm-arm/arch-omap/cpu.h127
-rw-r--r--include/asm-arm/arch-omap/dma.h135
-rw-r--r--include/asm-arm/arch-omap/gpio.h4
-rw-r--r--include/asm-arm/arch-omap/irqs.h2
-rw-r--r--include/asm-arm/arch-omap/nand.h24
-rw-r--r--include/asm-arm/arch-orion/debug-macro.S9
-rw-r--r--include/asm-arm/arch-orion/entry-macro.S4
-rw-r--r--include/asm-arm/arch-orion/hardware.h13
-rw-r--r--include/asm-arm/arch-orion/orion.h102
-rw-r--r--include/asm-arm/arch-orion/uncompress.h14
-rw-r--r--include/asm-arm/arch-orion/vmalloc.h2
16 files changed, 356 insertions, 106 deletions
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h
index dcb587b311f1..547125a4695e 100644
--- a/include/asm-arm/arch-omap/board-apollon.h
+++ b/include/asm-arm/arch-omap/board-apollon.h
@@ -29,6 +29,8 @@
29#ifndef __ASM_ARCH_OMAP_APOLLON_H 29#ifndef __ASM_ARCH_OMAP_APOLLON_H
30#define __ASM_ARCH_OMAP_APOLLON_H 30#define __ASM_ARCH_OMAP_APOLLON_H
31 31
32extern void apollon_mmc_init(void);
33
32/* Placeholder for APOLLON specific defines */ 34/* Placeholder for APOLLON specific defines */
33#define APOLLON_ETHR_GPIO_IRQ 74 35#define APOLLON_ETHR_GPIO_IRQ 74
34 36
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
index b2888ef9e9b4..c322796d0d26 100644
--- a/include/asm-arm/arch-omap/board-h2.h
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -34,5 +34,8 @@
34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ 34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
35#define OMAP1610_ETHR_START 0x04000300 35#define OMAP1610_ETHR_START 0x04000300
36 36
37extern void h2_mmc_init(void);
38extern void h2_mmc_slot_cover_handler(void *arg, int state);
39
37#endif /* __ASM_ARCH_OMAP_H2_H */ 40#endif /* __ASM_ARCH_OMAP_H2_H */
38 41
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 761ea0a17897..1c2b55c61ca0 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -36,5 +36,7 @@
36 36
37#define NR_IRQS (MAXIRQNUM + 1) 37#define NR_IRQS (MAXIRQNUM + 1)
38 38
39extern void __init h3_mmc_init(void);
40extern void h3_mmc_slot_cover_handler(void *arg, int state);
39 41
40#endif /* __ASM_ARCH_OMAP_H3_H */ 42#endif /* __ASM_ARCH_OMAP_H3_H */
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h
index 2bb8dd6e2d14..355adbdaae33 100644
--- a/include/asm-arm/arch-omap/board-sx1.h
+++ b/include/asm-arm/arch-omap/board-sx1.h
@@ -41,6 +41,12 @@ int sx1_getkeylight(u8 *keylight);
41 41
42int sx1_setmmipower(u8 onoff); 42int sx1_setmmipower(u8 onoff);
43int sx1_setusbpower(u8 onoff); 43int sx1_setusbpower(u8 onoff);
44int sx1_setmmcpower(u8 onoff); 44int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
45int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
46
47/* MMC prototypes */
48
49extern void sx1_mmc_init(void);
50extern void sx1_mmc_slot_cover_handler(void *arg, int state);
45 51
46#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ 52#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 08d58abd8218..442aecbb8f44 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -27,10 +27,21 @@
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H 27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H 28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29 29
30#ifdef CONFIG_I2C_OMAP
31#include <linux/i2c.h>
32#endif
33
30struct sys_timer; 34struct sys_timer;
31 35
32extern void omap_map_common_io(void); 36extern void omap_map_common_io(void);
33extern struct sys_timer omap_timer; 37extern struct sys_timer omap_timer;
34extern void omap_serial_init(void); 38extern void omap_serial_init(void);
39#ifdef CONFIG_I2C_OMAP
40extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
41 struct i2c_board_info const *info,
42 unsigned len);
43#else
44#define omap_register_i2c_bus(a, b, c, d) 0
45#endif
35 46
36#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 47#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index ec7eb675d922..e8a4cf52778b 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -28,7 +28,7 @@
28 28
29extern unsigned int system_rev; 29extern unsigned int system_rev;
30 30
31#define omap2_cpu_rev() ((system_rev >> 8) & 0x0f) 31#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
32 32
33/* 33/*
34 * Test if multicore OMAP support is needed 34 * Test if multicore OMAP support is needed
@@ -61,12 +61,33 @@ extern unsigned int system_rev;
61# define OMAP_NAME omap16xx 61# define OMAP_NAME omap16xx
62# endif 62# endif
63#endif 63#endif
64#ifdef CONFIG_ARCH_OMAP24XX 64#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) 65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
66# error "OMAP1 and OMAP2 can't be selected at the same time" 66# error "OMAP1 and OMAP2 can't be selected at the same time"
67# endif
68#endif
69#ifdef CONFIG_ARCH_OMAP2420
70# ifdef OMAP_NAME
71# undef MULTI_OMAP2
72# define MULTI_OMAP2
67# else 73# else
74# define OMAP_NAME omap2420
75# endif
76#endif
77#ifdef CONFIG_ARCH_OMAP2430
78# ifdef OMAP_NAME
79# undef MULTI_OMAP2
80# define MULTI_OMAP2
81# else
82# define OMAP_NAME omap2430
83# endif
84#endif
85#ifdef CONFIG_ARCH_OMAP3430
86# ifdef OMAP_NAME
68# undef MULTI_OMAP2 87# undef MULTI_OMAP2
69# define OMAP_NAME omap24xx 88# define MULTI_OMAP2
89# else
90# define OMAP_NAME omap3430
70# endif 91# endif
71#endif 92#endif
72 93
@@ -79,8 +100,9 @@ extern unsigned int system_rev;
79 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 100 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
80 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 101 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
81 * cpu_is_omap243x(): True for OMAP2430 102 * cpu_is_omap243x(): True for OMAP2430
103 * cpu_is_omap343x(): True for OMAP3430
82 */ 104 */
83#define GET_OMAP_CLASS (system_rev & 0xff) 105#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff)
84 106
85#define IS_OMAP_CLASS(class, id) \ 107#define IS_OMAP_CLASS(class, id) \
86static inline int is_omap ##class (void) \ 108static inline int is_omap ##class (void) \
@@ -100,9 +122,11 @@ IS_OMAP_CLASS(7xx, 0x07)
100IS_OMAP_CLASS(15xx, 0x15) 122IS_OMAP_CLASS(15xx, 0x15)
101IS_OMAP_CLASS(16xx, 0x16) 123IS_OMAP_CLASS(16xx, 0x16)
102IS_OMAP_CLASS(24xx, 0x24) 124IS_OMAP_CLASS(24xx, 0x24)
125IS_OMAP_CLASS(34xx, 0x34)
103 126
104IS_OMAP_SUBCLASS(242x, 0x242) 127IS_OMAP_SUBCLASS(242x, 0x242)
105IS_OMAP_SUBCLASS(243x, 0x243) 128IS_OMAP_SUBCLASS(243x, 0x243)
129IS_OMAP_SUBCLASS(343x, 0x343)
106 130
107#define cpu_is_omap7xx() 0 131#define cpu_is_omap7xx() 0
108#define cpu_is_omap15xx() 0 132#define cpu_is_omap15xx() 0
@@ -110,6 +134,8 @@ IS_OMAP_SUBCLASS(243x, 0x243)
110#define cpu_is_omap24xx() 0 134#define cpu_is_omap24xx() 0
111#define cpu_is_omap242x() 0 135#define cpu_is_omap242x() 0
112#define cpu_is_omap243x() 0 136#define cpu_is_omap243x() 0
137#define cpu_is_omap34xx() 0
138#define cpu_is_omap343x() 0
113 139
114#if defined(MULTI_OMAP1) 140#if defined(MULTI_OMAP1)
115# if defined(CONFIG_ARCH_OMAP730) 141# if defined(CONFIG_ARCH_OMAP730)
@@ -137,14 +163,44 @@ IS_OMAP_SUBCLASS(243x, 0x243)
137# undef cpu_is_omap16xx 163# undef cpu_is_omap16xx
138# define cpu_is_omap16xx() 1 164# define cpu_is_omap16xx() 1
139# endif 165# endif
166#endif
167
168#if defined(MULTI_OMAP2)
140# if defined(CONFIG_ARCH_OMAP24XX) 169# if defined(CONFIG_ARCH_OMAP24XX)
141# undef cpu_is_omap24xx 170# undef cpu_is_omap24xx
142# undef cpu_is_omap242x 171# undef cpu_is_omap242x
143# undef cpu_is_omap243x 172# undef cpu_is_omap243x
144# define cpu_is_omap24xx() 1 173# define cpu_is_omap24xx() is_omap24xx()
145# define cpu_is_omap242x() is_omap242x() 174# define cpu_is_omap242x() is_omap242x()
146# define cpu_is_omap243x() is_omap243x() 175# define cpu_is_omap243x() is_omap243x()
147# endif 176# endif
177# if defined(CONFIG_ARCH_OMAP34XX)
178# undef cpu_is_omap34xx
179# undef cpu_is_omap343x
180# define cpu_is_omap34xx() is_omap34xx()
181# define cpu_is_omap343x() is_omap343x()
182# endif
183#else
184# if defined(CONFIG_ARCH_OMAP24XX)
185# undef cpu_is_omap24xx
186# define cpu_is_omap24xx() 1
187# endif
188# if defined(CONFIG_ARCH_OMAP2420)
189# undef cpu_is_omap242x
190# define cpu_is_omap242x() 1
191# endif
192# if defined(CONFIG_ARCH_OMAP2430)
193# undef cpu_is_omap243x
194# define cpu_is_omap243x() 1
195# endif
196# if defined(CONFIG_ARCH_OMAP34XX)
197# undef cpu_is_omap34xx
198# define cpu_is_omap34xx() 1
199# endif
200# if defined(CONFIG_ARCH_OMAP3430)
201# undef cpu_is_omap343x
202# define cpu_is_omap343x() 1
203# endif
148#endif 204#endif
149 205
150/* 206/*
@@ -162,6 +218,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
162 * cpu_is_omap2422(): True for OMAP2422 218 * cpu_is_omap2422(): True for OMAP2422
163 * cpu_is_omap2423(): True for OMAP2423 219 * cpu_is_omap2423(): True for OMAP2423
164 * cpu_is_omap2430(): True for OMAP2430 220 * cpu_is_omap2430(): True for OMAP2430
221 * cpu_is_omap3430(): True for OMAP3430
165 */ 222 */
166#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) 223#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff)
167 224
@@ -183,6 +240,7 @@ IS_OMAP_TYPE(2420, 0x2420)
183IS_OMAP_TYPE(2422, 0x2422) 240IS_OMAP_TYPE(2422, 0x2422)
184IS_OMAP_TYPE(2423, 0x2423) 241IS_OMAP_TYPE(2423, 0x2423)
185IS_OMAP_TYPE(2430, 0x2430) 242IS_OMAP_TYPE(2430, 0x2430)
243IS_OMAP_TYPE(3430, 0x3430)
186 244
187#define cpu_is_omap310() 0 245#define cpu_is_omap310() 0
188#define cpu_is_omap730() 0 246#define cpu_is_omap730() 0
@@ -196,6 +254,7 @@ IS_OMAP_TYPE(2430, 0x2430)
196#define cpu_is_omap2422() 0 254#define cpu_is_omap2422() 0
197#define cpu_is_omap2423() 0 255#define cpu_is_omap2423() 0
198#define cpu_is_omap2430() 0 256#define cpu_is_omap2430() 0
257#define cpu_is_omap3430() 0
199 258
200#if defined(MULTI_OMAP1) 259#if defined(MULTI_OMAP1)
201# if defined(CONFIG_ARCH_OMAP730) 260# if defined(CONFIG_ARCH_OMAP730)
@@ -244,9 +303,65 @@ IS_OMAP_TYPE(2430, 0x2430)
244# define cpu_is_omap2430() is_omap2430() 303# define cpu_is_omap2430() is_omap2430()
245#endif 304#endif
246 305
306#if defined(CONFIG_ARCH_OMAP34XX)
307# undef cpu_is_omap3430
308# define cpu_is_omap3430() is_omap3430()
309#endif
310
247/* Macros to detect if we have OMAP1 or OMAP2 */ 311/* Macros to detect if we have OMAP1 or OMAP2 */
248#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ 312#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \
249 cpu_is_omap16xx()) 313 cpu_is_omap16xx())
250#define cpu_class_is_omap2() cpu_is_omap24xx() 314#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx())
315
316#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
317/*
318 * Macros to detect silicon revision of OMAP2/3 processors.
319 * is_sil_rev_greater_than: true if passed cpu type & its rev is greater.
320 * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser.
321 * is_sil_rev_equal_to: true if passed cpu type & its rev is equal.
322 * get_sil_rev: return the silicon rev value.
323 */
324#define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16)
325#define get_sil_revision(rev) ((rev & 0x0000f000) >> 12)
326
327#define is_sil_rev_greater_than(rev) \
328 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
329 (get_sil_revision(system_rev) > get_sil_revision(rev)))
330
331#define is_sil_rev_less_than(rev) \
332 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
333 (get_sil_revision(system_rev) < get_sil_revision(rev)))
334
335#define is_sil_rev_equal_to(rev) \
336 ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
337 (get_sil_revision(system_rev) == get_sil_revision(rev)))
338
339#define get_sil_rev() \
340 get_sil_revision(system_rev)
341
342/* Various silicon macros defined here */
343#define OMAP2420_REV_ES1_0 0x24200000
344#define OMAP2420_REV_ES2_0 0x24201000
345#define OMAP2430_REV_ES1_0 0x24300000
346#define OMAP3430_REV_ES1_0 0x34300000
347#define OMAP3430_REV_ES2_0 0x34301000
348
349/*
350 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
351 */
352#define DEVICE_TYPE_TEST 0
353#define DEVICE_TYPE_EMU 1
354#define DEVICE_TYPE_SEC 2
355#define DEVICE_TYPE_GP 3
356#define DEVICE_TYPE_BAD 4
357
358#define get_device_type() ((system_rev & 0x700) >> 8)
359#define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST)
360#define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU)
361#define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC)
362#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
363#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
364
365#endif
251 366
252#endif 367#endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index f33b467fddb7..24acf090030d 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -45,22 +45,28 @@
45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
46 46
47/* Hardware registers for omap2 */ 47/* Hardware registers for omap2 */
48#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000) 48#if defined(CONFIG_ARCH_OMAP3)
49#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00) 49#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000)
50#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78) 50#else /* CONFIG_ARCH_OMAP2 */
51#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08) 51#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000)
52#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c) 52#endif
53#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10) 53
54#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14) 54#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00)
55#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18) 55#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78)
56#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c) 56#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08)
57#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20) 57#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c)
58#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24) 58#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10)
59#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28) 59#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14)
60#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64) 60#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18)
61#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c) 61#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c)
62#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70) 62#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20)
63#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74) 63#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24)
64#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28)
65#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c)
66#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64)
67#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c)
68#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70)
69#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74)
64 70
65#ifdef CONFIG_ARCH_OMAP1 71#ifdef CONFIG_ARCH_OMAP1
66 72
@@ -86,19 +92,19 @@
86#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ 92#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
87 93
88/* Common channel specific registers for omap2 */ 94/* Common channel specific registers for omap2 */
89#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80) 95#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
90#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84) 96#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
91#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88) 97#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
92#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c) 98#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
93#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90) 99#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
94#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94) 100#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
95#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98) 101#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
96#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4) 102#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
97#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8) 103#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
98#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac) 104#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
99#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0) 105#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
100#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4) 106#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
101#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8) 107#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
102 108
103#endif 109#endif
104 110
@@ -113,11 +119,11 @@
113#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) 119#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
114 120
115/* Channel specific registers only on omap2 */ 121/* Channel specific registers only on omap2 */
116#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c) 122#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
117#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0) 123#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
118#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc) 124#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
119#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0) 125#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
120#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4) 126#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
121 127
122/*----------------------------------------------------------------------------*/ 128/*----------------------------------------------------------------------------*/
123 129
@@ -297,6 +303,10 @@
297#define OMAP_DMA_SYNC_ELEMENT 0x00 303#define OMAP_DMA_SYNC_ELEMENT 0x00
298#define OMAP_DMA_SYNC_FRAME 0x01 304#define OMAP_DMA_SYNC_FRAME 0x01
299#define OMAP_DMA_SYNC_BLOCK 0x02 305#define OMAP_DMA_SYNC_BLOCK 0x02
306#define OMAP_DMA_SYNC_PACKET 0x03
307
308#define OMAP_DMA_SRC_SYNC 0x01
309#define OMAP_DMA_DST_SYNC 0x00
300 310
301#define OMAP_DMA_PORT_EMIFF 0x00 311#define OMAP_DMA_PORT_EMIFF 0x00
302#define OMAP_DMA_PORT_EMIFS 0x01 312#define OMAP_DMA_PORT_EMIFS 0x01
@@ -310,6 +320,29 @@
310#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 320#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
311#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 321#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
312 322
323#define DMA_DEFAULT_FIFO_DEPTH 0x10
324#define DMA_DEFAULT_ARB_RATE 0x01
325/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
326#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
327#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
328#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
329#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
330#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
331#define DMA_THREAD_FIFO_75 (0x01 << 14)
332#define DMA_THREAD_FIFO_25 (0x02 << 14)
333#define DMA_THREAD_FIFO_50 (0x03 << 14)
334
335/* Chaining modes*/
336#ifndef CONFIG_ARCH_OMAP1
337#define OMAP_DMA_STATIC_CHAIN 0x1
338#define OMAP_DMA_DYNAMIC_CHAIN 0x2
339#define OMAP_DMA_CHAIN_ACTIVE 0x1
340#define OMAP_DMA_CHAIN_INACTIVE 0x0
341#endif
342
343#define DMA_CH_PRIO_HIGH 0x1
344#define DMA_CH_PRIO_LOW 0x0 /* Def */
345
313/* LCD DMA block numbers */ 346/* LCD DMA block numbers */
314enum { 347enum {
315 OMAP_LCD_DMA_B1_TOP, 348 OMAP_LCD_DMA_B1_TOP,
@@ -359,6 +392,13 @@ struct omap_dma_channel_params {
359 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 392 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
360 393
361 int ie; /* interrupt enabled */ 394 int ie; /* interrupt enabled */
395
396 unsigned char read_prio;/* read priority */
397 unsigned char write_prio;/* write priority */
398
399#ifndef CONFIG_ARCH_OMAP1
400 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
401#endif
362}; 402};
363 403
364 404
@@ -409,6 +449,33 @@ extern dma_addr_t omap_get_dma_dst_pos(int lch);
409extern int omap_get_dma_src_addr_counter(int lch); 449extern int omap_get_dma_src_addr_counter(int lch);
410extern void omap_clear_dma(int lch); 450extern void omap_clear_dma(int lch);
411extern int omap_dma_running(void); 451extern int omap_dma_running(void);
452extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
453 int tparams);
454extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
455 unsigned char write_prio);
456
457/* Chaining APIs */
458#ifndef CONFIG_ARCH_OMAP1
459extern int omap_request_dma_chain(int dev_id, const char *dev_name,
460 void (*callback) (int chain_id, u16 ch_status,
461 void *data),
462 int *chain_id, int no_of_chans,
463 int chain_mode,
464 struct omap_dma_channel_params params);
465extern int omap_free_dma_chain(int chain_id);
466extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
467 int dest_start, int elem_count,
468 int frame_count, void *callbk_data);
469extern int omap_start_dma_chain_transfers(int chain_id);
470extern int omap_stop_dma_chain_transfers(int chain_id);
471extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
472extern int omap_get_dma_chain_dst_pos(int chain_id);
473extern int omap_get_dma_chain_src_pos(int chain_id);
474
475extern int omap_modify_dma_chain_params(int chain_id,
476 struct omap_dma_channel_params params);
477extern int omap_dma_chain_status(int chain_id);
478#endif
412 479
413/* LCD DMA functions */ 480/* LCD DMA functions */
414extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 481extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index 97b397dd7e87..164da09be095 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -62,6 +62,8 @@
62#define OMAP_MPUIO_LATCH 0x34 62#define OMAP_MPUIO_LATCH 0x34
63#endif 63#endif
64 64
65#define OMAP34XX_NR_GPIOS 6
66
65#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) 67#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
66#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) 68#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
67 69
@@ -75,6 +77,8 @@ extern void omap_free_gpio(int gpio);
75extern void omap_set_gpio_direction(int gpio, int is_input); 77extern void omap_set_gpio_direction(int gpio, int is_input);
76extern void omap_set_gpio_dataout(int gpio, int enable); 78extern void omap_set_gpio_dataout(int gpio, int enable);
77extern int omap_get_gpio_datain(int gpio); 79extern int omap_get_gpio_datain(int gpio);
80extern void omap_set_gpio_debounce(int gpio, int enable);
81extern void omap_set_gpio_debounce_time(int gpio, int enable);
78 82
79/*-------------------------------------------------------------------------*/ 83/*-------------------------------------------------------------------------*/
80 84
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 3ede58b51db2..87973654e625 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -263,6 +263,8 @@
263#define INT_24XX_GPTIMER10 46 263#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47 264#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48 265#define INT_24XX_GPTIMER12 48
266#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57
266#define INT_24XX_MCBSP1_IRQ_TX 59 268#define INT_24XX_MCBSP1_IRQ_TX 59
267#define INT_24XX_MCBSP1_IRQ_RX 60 269#define INT_24XX_MCBSP1_IRQ_RX 60
268#define INT_24XX_MCBSP2_IRQ_TX 62 270#define INT_24XX_MCBSP2_IRQ_TX 62
diff --git a/include/asm-arm/arch-omap/nand.h b/include/asm-arm/arch-omap/nand.h
new file mode 100644
index 000000000000..17ae26e35353
--- /dev/null
+++ b/include/asm-arm/arch-omap/nand.h
@@ -0,0 +1,24 @@
1/*
2 * include/asm-arm/arch-omap/nand.h
3 *
4 * Copyright (C) 2006 Micron Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/mtd/partitions.h>
12
13struct omap_nand_platform_data {
14 unsigned int options;
15 int cs;
16 int gpio_irq;
17 struct mtd_partition *parts;
18 int nr_parts;
19 int (*nand_setup)(void __iomem *);
20 int (*dev_ready)(struct omap_nand_platform_data *);
21 int dma_channel;
22 void __iomem *gpmc_cs_baseaddr;
23 void __iomem *gpmc_baseaddr;
24};
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
index e2a80641f214..2746220f5d85 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -8,9 +8,14 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9*/ 9*/
10 10
11#include <asm/arch/orion.h>
12
11 .macro addruart,rx 13 .macro addruart,rx
12 mov \rx, #0xf1000000 14 mrc p15, 0, \rx, c1, c0
13 orr \rx, \rx, #0x00012000 15 tst \rx, #1 @ MMU enabled?
16 ldreq \rx, =ORION_REGS_PHYS_BASE
17 ldrne \rx, =ORION_REGS_VIRT_BASE
18 orr \rx, \rx, #0x00012000
14 .endm 19 .endm
15 20
16#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
index b76075a7e44b..cda096b2acfd 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -3,8 +3,8 @@
3 * 3 *
4 * Low-level IRQ helper macros for Orion platforms 4 * Low-level IRQ helper macros for Orion platforms
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
index 8a12d213fbdc..65da374de735 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -4,7 +4,6 @@
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 *
8 */ 7 */
9 8
10#ifndef __ASM_ARCH_HARDWARE_H__ 9#ifndef __ASM_ARCH_HARDWARE_H__
@@ -12,13 +11,11 @@
12 11
13#include "orion.h" 12#include "orion.h"
14 13
15#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE 14#define pcibios_assign_all_busses() 1
16#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
17 15
18#define pcibios_assign_all_busses() 1 16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
19 19
20#define PCIBIOS_MIN_IO 0x1000
21#define PCIBIOS_MIN_MEM 0x01000000
22#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
23 20
24#endif /* _ASM_ARCH_HARDWARE_H */ 21#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
index f787f752e58c..673a418a7419 100644
--- a/include/asm-arm/arch-orion/orion.h
+++ b/include/asm-arm/arch-orion/orion.h
@@ -14,32 +14,40 @@
14#ifndef __ASM_ARCH_ORION_H__ 14#ifndef __ASM_ARCH_ORION_H__
15#define __ASM_ARCH_ORION_H__ 15#define __ASM_ARCH_ORION_H__
16 16
17/******************************************************************************* 17/*****************************************************************************
18 * Orion Address Map 18 * Orion Address Map
19 * Use the same mapping (1:1 virtual:physical) of internal registers and 19 *
20 * PCI system (PCI+PCIE) for all machines. 20 * virt phys size
21 * Each machine defines the rest of its mapping (e.g. device bus flashes) 21 * fdd00000 f1000000 1M on-chip peripheral registers
22 ******************************************************************************/ 22 * fde00000 f2000000 1M PCIe I/O space
23#define ORION_REGS_BASE 0xf1000000 23 * fdf00000 f2100000 1M PCI I/O space
24 * fe000000 f0000000 16M PCIe WA space (Orion-NAS only)
25 ****************************************************************************/
26#define ORION_REGS_PHYS_BASE 0xf1000000
27#define ORION_REGS_VIRT_BASE 0xfdd00000
24#define ORION_REGS_SIZE SZ_1M 28#define ORION_REGS_SIZE SZ_1M
25 29
26#define ORION_PCI_SYS_MEM_BASE 0xe0000000 30#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
27#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE 31#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
28#define ORION_PCIE_MEM_SIZE SZ_128M 32#define ORION_PCIE_IO_BUS_BASE 0x00000000
29#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
30#define ORION_PCI_MEM_SIZE SZ_128M
31
32#define ORION_PCI_SYS_IO_BASE 0xf2000000
33#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
34#define ORION_PCIE_IO_SIZE SZ_1M 33#define ORION_PCIE_IO_SIZE SZ_1M
35#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE) 34
36#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE) 35#define ORION_PCI_IO_PHYS_BASE 0xf2100000
36#define ORION_PCI_IO_VIRT_BASE 0xfdf00000
37#define ORION_PCI_IO_BUS_BASE 0x00100000
37#define ORION_PCI_IO_SIZE SZ_1M 38#define ORION_PCI_IO_SIZE SZ_1M
38#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE) 39
39/* Relevant only for Orion-NAS */ 40/* Relevant only for Orion-NAS */
40#define ORION_PCIE_WA_BASE 0xf0000000 41#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
42#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
41#define ORION_PCIE_WA_SIZE SZ_16M 43#define ORION_PCIE_WA_SIZE SZ_16M
42 44
45#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
46#define ORION_PCIE_MEM_SIZE SZ_128M
47
48#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
49#define ORION_PCI_MEM_SIZE SZ_128M
50
43/******************************************************************************* 51/*******************************************************************************
44 * Supported Devices & Revisions 52 * Supported Devices & Revisions
45 ******************************************************************************/ 53 ******************************************************************************/
@@ -57,25 +65,42 @@
57/******************************************************************************* 65/*******************************************************************************
58 * Orion Registers Map 66 * Orion Registers Map
59 ******************************************************************************/ 67 ******************************************************************************/
60#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000) 68#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
61#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000) 69#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
62#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000) 70
63#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000) 71#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
64#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000) 72#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
65#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000) 73#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
66#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000) 74#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
67#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000) 75#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
68#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000) 76#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
69 77#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
70#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x)) 78#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
71#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x)) 79
72#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x)) 80#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
73#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x)) 81#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
74#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x)) 82
75#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x)) 83#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
76#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x)) 84#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
77#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x)) 85
78#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x)) 86#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
87#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
88
89#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
90#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
91#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
92
93#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
94#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
95#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
96
97#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
98#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
99#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
100
101#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
102#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
103#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
79 104
80/******************************************************************************* 105/*******************************************************************************
81 * Device Bus Registers 106 * Device Bus Registers
@@ -100,9 +125,6 @@
100#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) 125#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
101#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) 126#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
102#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) 127#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
103#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
104#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
105#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
106#define GPIO_MAX 32 128#define GPIO_MAX 32
107 129
108/*************************************************************************** 130/***************************************************************************
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
index a1a222fb438c..59f44039909a 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -10,8 +10,8 @@
10 10
11#include <asm/arch/orion.h> 11#include <asm/arch/orion.h>
12 12
13#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14)) 13#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
14#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0)) 14#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
15 15
16#define LSR_THRE 0x20 16#define LSR_THRE 0x20
17 17
@@ -27,16 +27,6 @@ static void flush(void)
27{ 27{
28} 28}
29 29
30static void orion_early_putstr(const char *ptr)
31{
32 char c;
33 while ((c = *ptr++) != '\0') {
34 if (c == '\n')
35 putc('\r');
36 putc(c);
37 }
38}
39
40/* 30/*
41 * nothing to do 31 * nothing to do
42 */ 32 */
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h
index 23e2a102fe0c..9d580278d2bc 100644
--- a/include/asm-arm/arch-orion/vmalloc.h
+++ b/include/asm-arm/arch-orion/vmalloc.h
@@ -2,4 +2,4 @@
2 * include/asm-arm/arch-orion/vmalloc.h 2 * include/asm-arm/arch-orion/vmalloc.h
3 */ 3 */
4 4
5#define VMALLOC_END 0xf0000000 5#define VMALLOC_END 0xfd800000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 21:46:12 -0500