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-rw-r--r--include/asm-arm/arch-iop32x/debug-macro.S20
-rw-r--r--include/asm-arm/arch-iop32x/dma.h (renamed from include/asm-arm/arch-iop3xx/dma.h)4
-rw-r--r--include/asm-arm/arch-iop32x/entry-macro.S21
-rw-r--r--include/asm-arm/arch-iop32x/glantank.h13
-rw-r--r--include/asm-arm/arch-iop32x/hardware.h44
-rw-r--r--include/asm-arm/arch-iop32x/io.h (renamed from include/asm-arm/arch-iop3xx/io.h)11
-rw-r--r--include/asm-arm/arch-iop32x/iop32x.h28
-rw-r--r--include/asm-arm/arch-iop32x/iq31244.h (renamed from include/asm-arm/arch-iop3xx/iq31244.h)15
-rw-r--r--include/asm-arm/arch-iop32x/iq80321.h (renamed from include/asm-arm/arch-iop3xx/iq80321.h)15
-rw-r--r--include/asm-arm/arch-iop32x/irqs.h50
-rw-r--r--include/asm-arm/arch-iop32x/memory.h26
-rw-r--r--include/asm-arm/arch-iop32x/n2100.h19
-rw-r--r--include/asm-arm/arch-iop32x/system.h33
-rw-r--r--include/asm-arm/arch-iop32x/timex.h9
-rw-r--r--include/asm-arm/arch-iop32x/uncompress.h39
-rw-r--r--include/asm-arm/arch-iop32x/vmalloc.h5
-rw-r--r--include/asm-arm/arch-iop33x/debug-macro.S24
-rw-r--r--include/asm-arm/arch-iop33x/dma.h9
-rw-r--r--include/asm-arm/arch-iop33x/entry-macro.S22
-rw-r--r--include/asm-arm/arch-iop33x/hardware.h46
-rw-r--r--include/asm-arm/arch-iop33x/io.h21
-rw-r--r--include/asm-arm/arch-iop33x/iop33x.h33
-rw-r--r--include/asm-arm/arch-iop33x/iq80331.h (renamed from include/asm-arm/arch-iop3xx/iq80331.h)15
-rw-r--r--include/asm-arm/arch-iop33x/iq80332.h (renamed from include/asm-arm/arch-iop3xx/iq80332.h)15
-rw-r--r--include/asm-arm/arch-iop33x/irqs.h60
-rw-r--r--include/asm-arm/arch-iop33x/memory.h26
-rw-r--r--include/asm-arm/arch-iop33x/system.h22
-rw-r--r--include/asm-arm/arch-iop33x/timex.h9
-rw-r--r--include/asm-arm/arch-iop33x/uncompress.h37
-rw-r--r--include/asm-arm/arch-iop33x/vmalloc.h5
-rw-r--r--include/asm-arm/arch-iop3xx/debug-macro.S35
-rw-r--r--include/asm-arm/arch-iop3xx/entry-macro.S57
-rw-r--r--include/asm-arm/arch-iop3xx/hardware.h57
-rw-r--r--include/asm-arm/arch-iop3xx/iop321-irqs.h100
-rw-r--r--include/asm-arm/arch-iop3xx/iop321.h345
-rw-r--r--include/asm-arm/arch-iop3xx/iop331-irqs.h132
-rw-r--r--include/asm-arm/arch-iop3xx/iop331.h363
-rw-r--r--include/asm-arm/arch-iop3xx/irqs.h21
-rw-r--r--include/asm-arm/arch-iop3xx/memory.h38
-rw-r--r--include/asm-arm/arch-iop3xx/system.h35
-rw-r--r--include/asm-arm/arch-iop3xx/timex.h20
-rw-r--r--include/asm-arm/arch-iop3xx/uncompress.h48
-rw-r--r--include/asm-arm/arch-iop3xx/vmalloc.h16
-rw-r--r--include/asm-arm/arch-l7200/io.h8
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h66
-rw-r--r--include/asm-arm/arch-s3c2410/map.h5
-rw-r--r--include/asm-arm/arch-s3c2410/osiris-map.h18
-rw-r--r--include/asm-arm/arch-s3c2410/regs-ac97.h23
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h30
-rw-r--r--include/asm-arm/atomic.h16
-rw-r--r--include/asm-arm/bitops.h24
-rw-r--r--include/asm-arm/flat.h16
-rw-r--r--include/asm-arm/hardware/iop3xx.h301
-rw-r--r--include/asm-arm/io.h4
-rw-r--r--include/asm-arm/irqflags.h132
-rw-r--r--include/asm-arm/mach/pci.h10
-rw-r--r--include/asm-arm/page.h3
-rw-r--r--include/asm-arm/pgtable.h7
-rw-r--r--include/asm-arm/system.h133
-rw-r--r--include/asm-arm/tlbflush.h76
-rw-r--r--include/asm-arm/unaligned.h62
61 files changed, 1333 insertions, 1564 deletions
diff --git a/include/asm-arm/arch-iop32x/debug-macro.S b/include/asm-arm/arch-iop32x/debug-macro.S
new file mode 100644
index 000000000000..9022b6849e23
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-iop32x/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mov \rx, #0xfe000000 @ physical as well as virtual
16 orr \rx, \rx, #0x00800000 @ location of the UART
17 .endm
18
19#define UART_SHIFT 0
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop32x/dma.h
index 1e808db8af2a..e977a9ef3160 100644
--- a/include/asm-arm/arch-iop3xx/dma.h
+++ b/include/asm-arm/arch-iop32x/dma.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop3xx/dma.h 2 * include/asm-arm/arch-iop32x/dma.h
3 * 3 *
4 * Copyright (C) 2004 Intel Corp. 4 * Copyright (C) 2004 Intel Corp.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S
new file mode 100644
index 000000000000..1500cbbd2295
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/entry-macro.S
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-iop32x/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IOP32x-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <asm/arch/iop32x.h>
11
12 .macro disable_fiq
13 .endm
14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 ldr \base, =IOP3XX_REG_ADDR(0x07D8)
17 ldr \irqstat, [\base] @ Read IINTSRC
18 cmp \irqstat, #0
19 clzne \irqnr, \irqstat
20 rsbne \irqnr, \irqnr, #31
21 .endm
diff --git a/include/asm-arm/arch-iop32x/glantank.h b/include/asm-arm/arch-iop32x/glantank.h
new file mode 100644
index 000000000000..3b065618dd00
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/glantank.h
@@ -0,0 +1,13 @@
1/*
2 * include/asm/arch-iop32x/glantank.h
3 *
4 * IO-Data GLAN Tank board registers
5 */
6
7#ifndef __GLANTANK_H
8#define __GLANTANK_H
9
10#define GLANTANK_UART 0xfe800000 /* UART */
11
12
13#endif
diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h
new file mode 100644
index 000000000000..6556ed5eee31
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/hardware.h
@@ -0,0 +1,44 @@
1/*
2 * include/asm-arm/arch-iop32x/hardware.h
3 */
4
5#ifndef __HARDWARE_H
6#define __HARDWARE_H
7
8#include <asm/types.h>
9
10/*
11 * Note about PCI IO space mappings
12 *
13 * To make IO space accesses efficient, we store virtual addresses in
14 * the IO resources.
15 *
16 * The PCI IO space is located at virtual 0xfe000000 from physical
17 * 0x90000000. The PCI BARs must be programmed with physical addresses,
18 * but when we read them, we convert them to virtual addresses. See
19 * arch/arm/plat-iop/pci.c.
20 */
21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000
24
25#ifndef __ASSEMBLY__
26void iop32x_init_irq(void);
27#endif
28
29
30/*
31 * Generic chipset bits
32 */
33#include "iop32x.h"
34
35/*
36 * Board specific bits
37 */
38#include "glantank.h"
39#include "iq80321.h"
40#include "iq31244.h"
41#include "n2100.h"
42
43
44#endif
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop32x/io.h
index 36adbdf5055a..12d9ee02cde3 100644
--- a/include/asm-arm/arch-iop3xx/io.h
+++ b/include/asm-arm/arch-iop32x/io.h
@@ -1,21 +1,22 @@
1/* 1/*
2 * linux/include/asm-arm/arch-iop3xx/io.h 2 * include/asm-arm/arch-iop32x/io.h
3 * 3 *
4 * Copyright (C) 2001 MontaVista Software, Inc. 4 * Copyright (C) 2001 MontaVista Software, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARM_ARCH_IO_H 11#ifndef __IO_H
12#define __ASM_ARM_ARCH_IO_H 12#define __IO_H
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#define IO_SPACE_LIMIT 0xffffffff 16#define IO_SPACE_LIMIT 0xffffffff
17 17
18#define __io(p) ((void __iomem *)(p)) 18#define __io(p) ((void __iomem *)(p))
19#define __mem_pci(a) (a) 19#define __mem_pci(a) (a)
20 20
21
21#endif 22#endif
diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h
new file mode 100644
index 000000000000..4bbd85f3ed2a
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/iop32x.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-arm/arch-iop32x/iop32x.h
3 *
4 * Intel IOP32X Chip definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __IOP32X_H
16#define __IOP32X_H
17
18/*
19 * Peripherals that are shared between the iop32x and iop33x but
20 * located at different addresses.
21 */
22#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
23#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
24
25#include <asm/hardware/iop3xx.h>
26
27
28#endif
diff --git a/include/asm-arm/arch-iop3xx/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h
index 4177cfa8100f..fff4eafa1f6b 100644
--- a/include/asm-arm/arch-iop3xx/iq31244.h
+++ b/include/asm-arm/arch-iop32x/iq31244.h
@@ -1,15 +1,11 @@
1/* 1/*
2 * linux/include/asm/arch-iop3xx/iq31244.h 2 * include/asm-arm/arch-iop32x/iq31244.h
3 * 3 *
4 * Intel IQ31244 evaluation board registers 4 * Intel IQ31244 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ31244_H_ 7#ifndef __IQ31244_H
8#define _IQ31244_H_ 8#define __IQ31244_H
9
10#define IQ31244_FLASHBASE 0xf0000000 /* Flash */
11#define IQ31244_FLASHSIZE 0x00800000
12#define IQ31244_FLASHWIDTH 2
13 9
14#define IQ31244_UART 0xfe800000 /* UART #1 */ 10#define IQ31244_UART 0xfe800000 /* UART #1 */
15#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ 11#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
@@ -17,8 +13,5 @@
17#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ 13#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
18#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ 14#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
19 15
20#ifndef __ASSEMBLY__
21extern void iq31244_map_io(void);
22#endif
23 16
24#endif // _IQ31244_H_ 17#endif
diff --git a/include/asm-arm/arch-iop3xx/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h
index cb8725979ffa..eb69db9b9a06 100644
--- a/include/asm-arm/arch-iop3xx/iq80321.h
+++ b/include/asm-arm/arch-iop32x/iq80321.h
@@ -1,15 +1,11 @@
1/* 1/*
2 * linux/include/asm/arch-iop3xx/iq80321.h 2 * include/asm-arm/arch-iop32x/iq80321.h
3 * 3 *
4 * Intel IQ80321 evaluation board registers 4 * Intel IQ80321 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ80321_H_ 7#ifndef __IQ80321_H
8#define _IQ80321_H_ 8#define __IQ80321_H
9
10#define IQ80321_FLASHBASE 0xf0000000 /* Flash */
11#define IQ80321_FLASHSIZE 0x00800000
12#define IQ80321_FLASHWIDTH 1
13 9
14#define IQ80321_UART 0xfe800000 /* UART #1 */ 10#define IQ80321_UART 0xfe800000 /* UART #1 */
15#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ 11#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
@@ -17,8 +13,5 @@
17#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ 13#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
18#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ 14#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
19 15
20#ifndef __ASSEMBLY__
21extern void iq80321_map_io(void);
22#endif
23 16
24#endif // _IQ80321_H_ 17#endif
diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h
new file mode 100644
index 000000000000..bbaef873afce
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/irqs.h
@@ -0,0 +1,50 @@
1/*
2 * include/asm-arm/arch-iop32x/irqs.h
3 *
4 * Author: Rory Bolt <rorybolt@pacbell.net>
5 * Copyright: (C) 2002 Rory Bolt
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __IRQS_H
13#define __IRQS_H
14
15/*
16 * IOP80321 chipset interrupts
17 */
18#define IRQ_IOP32X_DMA0_EOT 0
19#define IRQ_IOP32X_DMA0_EOC 1
20#define IRQ_IOP32X_DMA1_EOT 2
21#define IRQ_IOP32X_DMA1_EOC 3
22#define IRQ_IOP32X_AA_EOT 6
23#define IRQ_IOP32X_AA_EOC 7
24#define IRQ_IOP32X_CORE_PMON 8
25#define IRQ_IOP32X_TIMER0 9
26#define IRQ_IOP32X_TIMER1 10
27#define IRQ_IOP32X_I2C_0 11
28#define IRQ_IOP32X_I2C_1 12
29#define IRQ_IOP32X_MESSAGING 13
30#define IRQ_IOP32X_ATU_BIST 14
31#define IRQ_IOP32X_PERFMON 15
32#define IRQ_IOP32X_CORE_PMU 16
33#define IRQ_IOP32X_BIU_ERR 17
34#define IRQ_IOP32X_ATU_ERR 18
35#define IRQ_IOP32X_MCU_ERR 19
36#define IRQ_IOP32X_DMA0_ERR 20
37#define IRQ_IOP32X_DMA1_ERR 21
38#define IRQ_IOP32X_AA_ERR 23
39#define IRQ_IOP32X_MSG_ERR 24
40#define IRQ_IOP32X_SSP 25
41#define IRQ_IOP32X_XINT0 27
42#define IRQ_IOP32X_XINT1 28
43#define IRQ_IOP32X_XINT2 29
44#define IRQ_IOP32X_XINT3 30
45#define IRQ_IOP32X_HPI 31
46
47#define NR_IRQS 32
48
49
50#endif
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
new file mode 100644
index 000000000000..764cd3f0d416
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/memory.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-iop32x/memory.h
3 */
4
5#ifndef __MEMORY_H
6#define __MEMORY_H
7
8#include <asm/hardware.h>
9
10/*
11 * Physical DRAM offset.
12 */
13#define PHYS_OFFSET UL(0xa0000000)
14
15/*
16 * Virtual view <-> PCI DMA view memory address translations
17 * virt_to_bus: Used to translate the virtual address to an
18 * address suitable to be passed to set_dma_addr
19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use.
21 */
22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
24
25
26#endif
diff --git a/include/asm-arm/arch-iop32x/n2100.h b/include/asm-arm/arch-iop32x/n2100.h
new file mode 100644
index 000000000000..fed31a648425
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/n2100.h
@@ -0,0 +1,19 @@
1/*
2 * include/asm/arch-iop32x/n2100.h
3 *
4 * Thecus N2100 board registers
5 */
6
7#ifndef __N2100_H
8#define __N2100_H
9
10#define N2100_UART 0xfe800000 /* UART */
11
12#define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0)
13#define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2)
14#define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3)
15#define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4)
16#define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5)
17
18
19#endif
diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h
new file mode 100644
index 000000000000..17b7eb7e9c0d
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/system.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-iop32x/system.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <asm/mach-types.h>
12
13static inline void arch_idle(void)
14{
15 cpu_do_idle();
16}
17
18static inline void arch_reset(char mode)
19{
20 local_irq_disable();
21
22 if (machine_is_n2100()) {
23 gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
24 gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
25 while (1)
26 ;
27 }
28
29 *IOP3XX_PCSR = 0x30;
30
31 /* Jump into ROM at address 0 */
32 cpu_reset(0);
33}
diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h
new file mode 100644
index 000000000000..9934b087311b
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/timex.h
@@ -0,0 +1,9 @@
1/*
2 * include/asm-arm/arch-iop32x/timex.h
3 *
4 * IOP32x architecture timex specifications
5 */
6
7#include <asm/hardware.h>
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
new file mode 100644
index 000000000000..e64f52bf2bce
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/uncompress.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-arm/arch-iop32x/uncompress.h
3 */
4
5#include <asm/types.h>
6#include <asm/mach-types.h>
7#include <linux/serial_reg.h>
8#include <asm/hardware.h>
9
10static volatile u8 *uart_base;
11
12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
13
14static inline void putc(char c)
15{
16 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
17 barrier();
18 uart_base[UART_TX] = c;
19}
20
21static inline void flush(void)
22{
23}
24
25static __inline__ void __arch_decomp_setup(unsigned long arch_id)
26{
27 if (machine_is_iq80321())
28 uart_base = (volatile u8 *)IQ80321_UART;
29 else if (machine_is_iq31244())
30 uart_base = (volatile u8 *)IQ31244_UART;
31 else
32 uart_base = (volatile u8 *)0xfe800000;
33}
34
35/*
36 * nothing to do
37 */
38#define arch_decomp_setup() __arch_decomp_setup(arch_id)
39#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop32x/vmalloc.h b/include/asm-arm/arch-iop32x/vmalloc.h
new file mode 100644
index 000000000000..0a70baa19517
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-iop32x/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
diff --git a/include/asm-arm/arch-iop33x/debug-macro.S b/include/asm-arm/arch-iop33x/debug-macro.S
new file mode 100644
index 000000000000..9e7132ebe6a7
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/debug-macro.S
@@ -0,0 +1,24 @@
1/*
2 * include/asm-arm/arch-iop33x/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical
18 movne \rx, #0xfe000000 @ virtual
19 orr \rx, \rx, #0x00ff0000
20 orr \rx, \rx, #0x0000f700
21 .endm
22
23#define UART_SHIFT 2
24#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop33x/dma.h b/include/asm-arm/arch-iop33x/dma.h
new file mode 100644
index 000000000000..b7775fdc5ad3
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/dma.h
@@ -0,0 +1,9 @@
1/*
2 * include/asm-arm/arch-iop33x/dma.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S
new file mode 100644
index 000000000000..92b791702e34
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/entry-macro.S
@@ -0,0 +1,22 @@
1/*
2 * include/asm-arm/arch-iop33x/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IOP33x-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <asm/arch/iop33x.h>
11
12 .macro disable_fiq
13 .endm
14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 ldr \base, =IOP3XX_REG_ADDR(0x07C8)
17 ldr \irqstat, [\base] @ Read IINTVEC
18 cmp \irqstat, #0
19 ldreq \irqstat, [\base] @ erratum 63 workaround
20 adds \irqnr, \irqstat, #1
21 movne \irqnr, \irqstat, lsr #2
22 .endm
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h
new file mode 100644
index 000000000000..0659cf94d040
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/hardware.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-arm/arch-iop33x/hardware.h
3 */
4
5#ifndef __HARDWARE_H
6#define __HARDWARE_H
7
8#include <asm/types.h>
9
10/*
11 * Note about PCI IO space mappings
12 *
13 * To make IO space accesses efficient, we store virtual addresses in
14 * the IO resources.
15 *
16 * The PCI IO space is located at virtual 0xfe000000 from physical
17 * 0x90000000. The PCI BARs must be programmed with physical addresses,
18 * but when we read them, we convert them to virtual addresses. See
19 * arch/arm/mach-iop3xx/iop3xx-pci.c
20 */
21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000
24
25#ifndef __ASSEMBLY__
26void iop33x_init_irq(void);
27
28extern struct platform_device iop33x_uart0_device;
29extern struct platform_device iop33x_uart1_device;
30#endif
31
32
33/*
34 * Generic chipset bits
35 *
36 */
37#include "iop33x.h"
38
39/*
40 * Board specific bits
41 */
42#include "iq80331.h"
43#include "iq80332.h"
44
45
46#endif
diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h
new file mode 100644
index 000000000000..c017402bab96
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/io.h
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-iop33x/io.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __IO_H
12#define __IO_H
13
14#include <asm/hardware.h>
15
16#define IO_SPACE_LIMIT 0xffffffff
17#define __io(p) ((void __iomem *)(p))
18#define __mem_pci(a) (a)
19
20
21#endif
diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h
new file mode 100644
index 000000000000..7ac6e93db5ff
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/iop33x.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-iop33x/iop33x.h
3 *
4 * Intel IOP33X Chip definitions
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __IOP33X_H
15#define __IOP33X_H
16
17/*
18 * Peripherals that are shared between the iop32x and iop33x but
19 * located at different addresses.
20 */
21#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
22#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
23
24#include <asm/hardware/iop3xx.h>
25
26/* UARTs */
27#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
28#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
29#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
30#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
31
32
33#endif
diff --git a/include/asm-arm/arch-iop3xx/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h
index 0668e78d483e..79b9302017ea 100644
--- a/include/asm-arm/arch-iop3xx/iq80331.h
+++ b/include/asm-arm/arch-iop33x/iq80331.h
@@ -1,23 +1,16 @@
1/* 1/*
2 * linux/include/asm/arch-iop3xx/iq80331.h 2 * include/asm-arm/arch-iop33x/iq80331.h
3 * 3 *
4 * Intel IQ80331 evaluation board registers 4 * Intel IQ80331 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ80331_H_ 7#ifndef __IQ80331_H
8#define _IQ80331_H_ 8#define __IQ80331_H
9
10#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
11#define IQ80331_FLASHSIZE 0x00800000
12#define IQ80331_FLASHWIDTH 1
13 9
14#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ 10#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
15#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ 11#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
16#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ 12#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
17#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ 13#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
18 14
19#ifndef __ASSEMBLY__
20extern void iq80331_map_io(void);
21#endif
22 15
23#endif // _IQ80331_H_ 16#endif
diff --git a/include/asm-arm/arch-iop3xx/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h
index e5fff1775d1a..053165629492 100644
--- a/include/asm-arm/arch-iop3xx/iq80332.h
+++ b/include/asm-arm/arch-iop33x/iq80332.h
@@ -1,23 +1,16 @@
1/* 1/*
2 * linux/include/asm/arch-iop3xx/iq80332.h 2 * include/asm-arm/arch-iop33x/iq80332.h
3 * 3 *
4 * Intel IQ80332 evaluation board registers 4 * Intel IQ80332 evaluation board registers
5 */ 5 */
6 6
7#ifndef _IQ80332_H_ 7#ifndef __IQ80332_H
8#define _IQ80332_H_ 8#define __IQ80332_H
9
10#define IQ80332_FLASHBASE 0xc0000000 /* Flash */
11#define IQ80332_FLASHSIZE 0x00800000
12#define IQ80332_FLASHWIDTH 1
13 9
14#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ 10#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
15#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ 11#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
16#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ 12#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
17#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ 13#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
18 14
19#ifndef __ASSEMBLY__
20extern void iq80332_map_io(void);
21#endif
22 15
23#endif // _IQ80332_H_ 16#endif
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h
new file mode 100644
index 000000000000..d045f8403396
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/irqs.h
@@ -0,0 +1,60 @@
1/*
2 * include/asm-arm/arch-iop33x/irqs.h
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright: (C) 2003 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __IRQS_H
13#define __IRQS_H
14
15/*
16 * IOP80331 chipset interrupts
17 */
18#define IRQ_IOP33X_DMA0_EOT 0
19#define IRQ_IOP33X_DMA0_EOC 1
20#define IRQ_IOP33X_DMA1_EOT 2
21#define IRQ_IOP33X_DMA1_EOC 3
22#define IRQ_IOP33X_AA_EOT 6
23#define IRQ_IOP33X_AA_EOC 7
24#define IRQ_IOP33X_TIMER0 8
25#define IRQ_IOP33X_TIMER1 9
26#define IRQ_IOP33X_I2C_0 10
27#define IRQ_IOP33X_I2C_1 11
28#define IRQ_IOP33X_MSG 12
29#define IRQ_IOP33X_MSGIBQ 13
30#define IRQ_IOP33X_ATU_BIST 14
31#define IRQ_IOP33X_PERFMON 15
32#define IRQ_IOP33X_CORE_PMU 16
33#define IRQ_IOP33X_XINT0 24
34#define IRQ_IOP33X_XINT1 25
35#define IRQ_IOP33X_XINT2 26
36#define IRQ_IOP33X_XINT3 27
37#define IRQ_IOP33X_XINT8 32
38#define IRQ_IOP33X_XINT9 33
39#define IRQ_IOP33X_XINT10 34
40#define IRQ_IOP33X_XINT11 35
41#define IRQ_IOP33X_XINT12 36
42#define IRQ_IOP33X_XINT13 37
43#define IRQ_IOP33X_XINT14 38
44#define IRQ_IOP33X_XINT15 39
45#define IRQ_IOP33X_UART0 51
46#define IRQ_IOP33X_UART1 52
47#define IRQ_IOP33X_PBIE 53
48#define IRQ_IOP33X_ATU_CRW 54
49#define IRQ_IOP33X_ATU_ERR 55
50#define IRQ_IOP33X_MCU_ERR 56
51#define IRQ_IOP33X_DMA0_ERR 57
52#define IRQ_IOP33X_DMA1_ERR 58
53#define IRQ_IOP33X_AA_ERR 60
54#define IRQ_IOP33X_MSG_ERR 62
55#define IRQ_IOP33X_HPI 63
56
57#define NR_IRQS 64
58
59
60#endif
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
new file mode 100644
index 000000000000..0d39139b241e
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/memory.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-iop33x/memory.h
3 */
4
5#ifndef __MEMORY_H
6#define __MEMORY_H
7
8#include <asm/hardware.h>
9
10/*
11 * Physical DRAM offset.
12 */
13#define PHYS_OFFSET UL(0x00000000)
14
15/*
16 * Virtual view <-> PCI DMA view memory address translations
17 * virt_to_bus: Used to translate the virtual address to an
18 * address suitable to be passed to set_dma_addr
19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use.
21 */
22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
24
25
26#endif
diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h
new file mode 100644
index 000000000000..00dd07ece262
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/system.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-arm/arch-iop33x/system.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16static inline void arch_reset(char mode)
17{
18 *IOP3XX_PCSR = 0x30;
19
20 /* Jump into ROM at address 0 */
21 cpu_reset(0);
22}
diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h
new file mode 100644
index 000000000000..fe3e1e369ff9
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/timex.h
@@ -0,0 +1,9 @@
1/*
2 * include/asm-arm/arch-iop33x/timex.h
3 *
4 * IOP3xx architecture timex specifications
5 */
6
7#include <asm/hardware.h>
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop33x/uncompress.h b/include/asm-arm/arch-iop33x/uncompress.h
new file mode 100644
index 000000000000..e17fbc05877b
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/uncompress.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-iop33x/uncompress.h
3 */
4
5#include <asm/types.h>
6#include <asm/mach-types.h>
7#include <linux/serial_reg.h>
8#include <asm/hardware.h>
9
10static volatile u32 *uart_base;
11
12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
13
14static inline void putc(char c)
15{
16 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
17 barrier();
18 uart_base[UART_TX] = c;
19}
20
21static inline void flush(void)
22{
23}
24
25static __inline__ void __arch_decomp_setup(unsigned long arch_id)
26{
27 if (machine_is_iq80331() || machine_is_iq80332())
28 uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
29 else
30 uart_base = (volatile u32 *)0xfe800000;
31}
32
33/*
34 * nothing to do
35 */
36#define arch_decomp_setup() __arch_decomp_setup(arch_id)
37#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop33x/vmalloc.h b/include/asm-arm/arch-iop33x/vmalloc.h
new file mode 100644
index 000000000000..66f545a7f4fc
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-iop33x/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S
deleted file mode 100644
index ce007e531994..000000000000
--- a/include/asm-arm/arch-iop3xx/debug-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/* linux/include/asm-arm/arch-iop3xx/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mov \rx, #0xfe000000 @ physical
16#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
17 orr \rx, \rx, #0x00800000 @ location of the UART
18#elif defined(CONFIG_ARCH_IOP331)
19 mrc p15, 0, \rx, c1, c0
20 tst \rx, #1 @ MMU enabled?
21 moveq \rx, #0x000fe000 @ Physical Base
22 movne \rx, #0
23 orr \rx, \rx, #0xfe000000
24 orr \rx, \rx, #0x00f00000 @ Virtual Base
25 orr \rx, \rx, #0x00001700 @ location of the UART
26#else
27#error Unknown IOP3XX implementation
28#endif
29 .endm
30
31#if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331)
32#define FLOW_CONTROL
33#endif
34#define UART_SHIFT 0
35#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S
deleted file mode 100644
index 926668c098a5..000000000000
--- a/include/asm-arm/arch-iop3xx/entry-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * include/asm-arm/arch-iop3xx/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IOP3xx-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <asm/arch/irqs.h>
11
12#if defined(CONFIG_ARCH_IOP321)
13 .macro disable_fiq
14 .endm
15
16 /*
17 * Note: only deal with normal interrupts, not FIQ
18 */
19 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
20 mov \irqnr, #0
21 mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
22 cmp \irqstat, #0
23 beq 1001f
24 clz \irqnr, \irqstat
25 mov \base, #31
26 subs \irqnr,\base,\irqnr
27 add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
281001:
29 .endm
30
31#elif defined(CONFIG_ARCH_IOP331)
32 .macro disable_fiq
33 .endm
34
35 /*
36 * Note: only deal with normal interrupts, not FIQ
37 */
38 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
39 mov \irqnr, #0
40 mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0
41 cmp \irqstat, #0
42 bne 1002f
43 mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1
44 cmp \irqstat, #0
45 beq 1001f
46 clz \irqnr, \irqstat
47 rsbs \irqnr,\irqnr,#31 @ recommend by RMK
48 add \irqnr,\irqnr,#IRQ_IOP331_XINT8
49 b 1001f
501002: clz \irqnr, \irqstat
51 rsbs \irqnr,\irqnr,#31 @ recommend by RMK
52 add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
531001:
54 .endm
55
56#endif
57
diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h
deleted file mode 100644
index 3b138171d086..000000000000
--- a/include/asm-arm/arch-iop3xx/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/hardware.h
3 */
4#ifndef __ASM_ARCH_HARDWARE_H
5#define __ASM_ARCH_HARDWARE_H
6
7#include <asm/types.h>
8
9/*
10 * Note about PCI IO space mappings
11 *
12 * To make IO space accesses efficient, we store virtual addresses in
13 * the IO resources.
14 *
15 * The PCI IO space is located at virtual 0xfe000000 from physical
16 * 0x90000000. The PCI BARs must be programmed with physical addresses,
17 * but when we read them, we convert them to virtual addresses. See
18 * arch/arm/mach-iop3xx/iop3xx-pci.c
19 */
20
21#define pcibios_assign_all_busses() 1
22
23
24/*
25 * The min PCI I/O and MEM space are dependent on what specific
26 * chipset/platform we are running on, so instead of hardcoding with
27 * #ifdefs, we just fill these in the platform level PCI init code.
28 */
29#ifndef __ASSEMBLY__
30extern unsigned long iop3xx_pcibios_min_io;
31extern unsigned long iop3xx_pcibios_min_mem;
32
33extern unsigned int processor_id;
34#endif
35
36/*
37 * We just set these to zero since they are really bogus anyways
38 */
39#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
40#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
41
42/*
43 * Generic chipset bits
44 *
45 */
46#include "iop321.h"
47#include "iop331.h"
48
49/*
50 * Board specific bits
51 */
52#include "iq80321.h"
53#include "iq31244.h"
54#include "iq80331.h"
55#include "iq80332.h"
56
57#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h
deleted file mode 100644
index 2fcc1654cb9d..000000000000
--- a/include/asm-arm/arch-iop3xx/iop321-irqs.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/irqs.h
3 *
4 * Author: Rory Bolt <rorybolt@pacbell.net>
5 * Copyright: (C) 2002 Rory Bolt
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#ifndef _IOP321_IRQS_H_
13#define _IOP321_IRQS_H_
14
15/*
16 * IOP80321 chipset interrupts
17 */
18#define IOP321_IRQ_OFS 0
19#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x))
20
21/*
22 * On IRQ or FIQ register
23 */
24#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0)
25#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1)
26#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2)
27#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3)
28#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4)
29#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5)
30#define IRQ_IOP321_AA_EOT IOP321_IRQ(6)
31#define IRQ_IOP321_AA_EOC IOP321_IRQ(7)
32#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8)
33#define IRQ_IOP321_TIMER0 IOP321_IRQ(9)
34#define IRQ_IOP321_TIMER1 IOP321_IRQ(10)
35#define IRQ_IOP321_I2C_0 IOP321_IRQ(11)
36#define IRQ_IOP321_I2C_1 IOP321_IRQ(12)
37#define IRQ_IOP321_MESSAGING IOP321_IRQ(13)
38#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14)
39#define IRQ_IOP321_PERFMON IOP321_IRQ(15)
40#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16)
41#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17)
42#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18)
43#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19)
44#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20)
45#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21)
46#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22)
47#define IRQ_IOP321_AA_ERR IOP321_IRQ(23)
48#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24)
49#define IRQ_IOP321_SSP IOP321_IRQ(25)
50#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26)
51#define IRQ_IOP321_XINT0 IOP321_IRQ(27)
52#define IRQ_IOP321_XINT1 IOP321_IRQ(28)
53#define IRQ_IOP321_XINT2 IOP321_IRQ(29)
54#define IRQ_IOP321_XINT3 IOP321_IRQ(30)
55#define IRQ_IOP321_HPI IOP321_IRQ(31)
56
57#define NR_IOP321_IRQS (IOP321_IRQ(31) + 1)
58
59#define NR_IRQS NR_IOP321_IRQS
60
61
62/*
63 * Interrupts available on the IQ80321 board
64 */
65
66/*
67 * On board devices
68 */
69#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0
70#define IRQ_IQ80321_UART IRQ_IOP321_XINT1
71
72/*
73 * PCI interrupts
74 */
75#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0
76#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1
77#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2
78#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3
79
80/*
81 * Interrupts on the IQ31244 board
82 */
83
84/*
85 * On board devices
86 */
87#define IRQ_IQ31244_UART IRQ_IOP321_XINT1
88#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0
89#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2
90#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3
91
92/*
93 * PCI interrupts
94 */
95#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0
96#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1
97#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2
98#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3
99
100#endif // _IOP321_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h
deleted file mode 100644
index f8df778a356f..000000000000
--- a/include/asm-arm/arch-iop3xx/iop321.h
+++ /dev/null
@@ -1,345 +0,0 @@
1/*
2 * linux/include/asm/arch-iop3xx/iop321.h
3 *
4 * Intel IOP321 Chip definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IOP321_HW_H_
16#define _IOP321_HW_H_
17
18
19/*
20 * This is needed for mixed drivers that need to work on all
21 * IOP3xx variants but behave slightly differently on each.
22 */
23#ifndef __ASSEMBLY__
24#ifdef CONFIG_ARCH_IOP321
25#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420))
26#else
27#define iop_is_321() 0
28#endif
29#endif
30
31/*
32 * IOP321 I/O and Mem space regions for PCI autoconfiguration
33 */
34#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
35#define IOP321_PCI_LOWER_IO_PA 0x90000000
36#define IOP321_PCI_LOWER_IO_VA 0xfe000000
37#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
38#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
39#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
40#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
41#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
42
43/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
44#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
45#define IOP321_PCI_LOWER_MEM_PA 0x80000000
46#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
47#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
48#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
49#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
50
51
52/*
53 * IOP321 chipset registers
54 */
55#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
56#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
57#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
58
59/* Reserved 0x00000000 through 0x000000FF */
60
61/* Address Translation Unit 0x00000100 through 0x000001FF */
62#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100)
63#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102)
64#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104)
65#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106)
66#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108)
67#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109)
68#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C)
69#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D)
70#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E)
71#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F)
72#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110)
73#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114)
74#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118)
75#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
76#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120)
77#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124)
78#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
79#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
80#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130)
81/* Reserved 0x00000134 through 0x0000013B */
82#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C)
83#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D)
84#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E)
85#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F)
86#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140)
87#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144)
88#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148)
89#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
90#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150)
91#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154)
92#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158)
93#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
94#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160)
95#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164)
96#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168)
97#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
98/* Reserved 0x00000170 through 0x00000177*/
99#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178)
100/* Reserved 0x0000017C through 0x0000017F*/
101#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180)
102#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184)
103#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188)
104#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
105#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190)
106#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194)
107#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198)
108#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
109/* Reserved 0x000001A0 through 0x000001A3*/
110#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
111/* Reserved 0x000001A8 through 0x000001AB*/
112#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
113/* Reserved 0x000001B0 through 0x000001BB*/
114#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
115#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0)
116#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1)
117#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
118#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
119/* Reserved 0x000001C6 through 0x000001DF */
120#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0)
121#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1)
122#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
123#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
124#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
125
126/* Messaging Unit 0x00000300 through 0x000003FF */
127
128/* Reserved 0x00000300 through 0x0000030c */
129#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310)
130#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314)
131#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318)
132#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
133#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320)
134#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324)
135#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328)
136#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
137#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330)
138#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334)
139/* Reserved 0x00000338 through 0x0000034F */
140#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350)
141#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354)
142/* Reserved 0x00000358 through 0x0000035C */
143#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360)
144#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364)
145#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368)
146#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
147#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370)
148#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374)
149#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
150#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
151#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
152
153#define IOP321_IIxR_MASK 0x7f /* masks all */
154#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */
155#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */
156#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */
157#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */
158#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */
159#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */
160#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */
161
162/* Reserved 0x00000384 through 0x000003FF */
163
164/* DMA Controller 0x00000400 through 0x000004FF */
165#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400)
166#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404)
167#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
168#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410)
169#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414)
170#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
171#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
172#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420)
173#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424)
174/* Reserved 0x00000428 through 0x0000043C */
175#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440)
176#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444)
177#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
178#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450)
179#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454)
180#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
181#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
182#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460)
183#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464)
184/* Reserved 0x00000468 through 0x000004FF */
185
186/* Memory controller 0x00000500 through 0x0005FF */
187
188/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
189#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680)
190#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684)
191#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688)
192#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
193#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690)
194#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694)
195#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698)
196#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
197#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
198#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
199#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
200#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
201#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
202#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
203#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
204/* Reserved 0x000006BC */
205#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
206/* Reserved 0x000006C4 through 0x000006DC */
207#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
208#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
209
210#define IOP321_PBCR_EN 0x1
211
212#define IOP321_PBISR_BOOR_ERR 0x1
213
214/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
215#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700)
216#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704)
217#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708)
218/* reserved 0x00000070c */
219#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710)
220/* PERC0 DOESN'T EXIST - index from 1! */
221#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710)
222
223#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */
224
225/* Internal arbitration unit 0x00000780 through 0x0007BF */
226#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
227#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
228#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
229
230/* General Purpose I/O Registers */
231#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
232#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
233#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
234
235/* Interrupt Controller */
236#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
237#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
238#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
239#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
240
241/* Timers */
242
243#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
244#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
245
246#ifdef CONFIG_ARCH_IQ80321
247#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
248#elif defined(CONFIG_ARCH_IQ31244)
249#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
250#endif
251
252#ifdef CONFIG_ARCH_EP80219
253#undef IOP321_TICK_RATE
254#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
255#endif
256
257#define IOP321_TMR_TC 0x01
258#define IOP321_TMR_EN 0x02
259#define IOP321_TMR_RELOAD 0x04
260#define IOP321_TMR_PRIVILEGED 0x09
261
262#define IOP321_TMR_RATIO_1_1 0x00
263#define IOP321_TMR_RATIO_4_1 0x10
264#define IOP321_TMR_RATIO_8_1 0x20
265#define IOP321_TMR_RATIO_16_1 0x30
266
267#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8)
268#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC)
269#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0)
270#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4)
271#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
272#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
273
274/* Application accelerator unit 0x00000800 - 0x000008FF */
275#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
276#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
277#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
278#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
279#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
280#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814)
281#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818)
282#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
283#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
284#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830)
285#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834)
286#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838)
287#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840)
288#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844)
289#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848)
290#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
291#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850)
292#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854)
293#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858)
294#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
295#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864)
296#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868)
297#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
298#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870)
299#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874)
300#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878)
301#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
302#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880)
303#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888)
304#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
305#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890)
306#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894)
307#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898)
308#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
309#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
310#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
311#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
312#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
313#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
314#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
315#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860)
316#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884)
317
318
319/* SSP serial port unit 0x00001600 - 0x0000167F */
320/* I2C bus interface unit 0x00001680 - 0x000016FF */
321#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680)
322#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684)
323#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688)
324#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C)
325/* Reserved 0x00001690 */
326#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694)
327/* Reserved 0x00001698 */
328/* Reserved 0x0000169C */
329#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0)
330#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4)
331#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8)
332#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC)
333#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4)
334/* Reserved 0x000016B8 through 0x000016FC */
335
336/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
337
338
339#ifndef __ASSEMBLY__
340extern void iop321_map_io(void);
341extern void iop321_init_irq(void);
342extern void iop321_time_init(void);
343#endif
344
345#endif // _IOP321_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331-irqs.h b/include/asm-arm/arch-iop3xx/iop331-irqs.h
deleted file mode 100644
index 7135ad7e335e..000000000000
--- a/include/asm-arm/arch-iop3xx/iop331-irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/irqs.h
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright: (C) 2003 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#ifndef _IOP331_IRQS_H_
13#define _IOP331_IRQS_H_
14
15/*
16 * IOP80331 chipset interrupts
17 */
18#define IOP331_IRQ_OFS 0
19#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x))
20
21/*
22 * On IRQ or FIQ register
23 */
24#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0)
25#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1)
26#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2)
27#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3)
28#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4)
29#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5)
30#define IRQ_IOP331_AA_EOT IOP331_IRQ(6)
31#define IRQ_IOP331_AA_EOC IOP331_IRQ(7)
32#define IRQ_IOP331_TIMER0 IOP331_IRQ(8)
33#define IRQ_IOP331_TIMER1 IOP331_IRQ(9)
34#define IRQ_IOP331_I2C_0 IOP331_IRQ(10)
35#define IRQ_IOP331_I2C_1 IOP331_IRQ(11)
36#define IRQ_IOP331_MSG IOP331_IRQ(12)
37#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13)
38#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14)
39#define IRQ_IOP331_PERFMON IOP331_IRQ(15)
40#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16)
41#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17)
42#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18)
43#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19)
44#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20)
45#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21)
46#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22)
47#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23)
48#define IRQ_IOP331_XINT0 IOP331_IRQ(24)
49#define IRQ_IOP331_XINT1 IOP331_IRQ(25)
50#define IRQ_IOP331_XINT2 IOP331_IRQ(26)
51#define IRQ_IOP331_XINT3 IOP331_IRQ(27)
52#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28)
53#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29)
54#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30)
55#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31)
56#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0
57#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1
58#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2
59#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3
60#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4
61#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5
62#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6
63#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7
64#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8
65#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9
66#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10
67#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11
68#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12
69#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13
70#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14
71#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15
72#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16
73#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17
74#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18
75#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19
76#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20
77#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21
78#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22
79#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23
80#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24
81#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25
82#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26
83#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27
84#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28
85#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29
86#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30
87#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31
88
89#define NR_IOP331_IRQS (IOP331_IRQ(63) + 1)
90
91#define NR_IRQS NR_IOP331_IRQS
92
93
94/*
95 * Interrupts available on the IQ80331 board
96 */
97
98/*
99 * On board devices
100 */
101#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0
102#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0
103#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1
104
105/*
106 * PCI interrupts
107 */
108#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0
109#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1
110#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
111#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
112
113/*
114 * Interrupts available on the IQ80332 board
115 */
116
117/*
118 * On board devices
119 */
120#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0
121#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0
122#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1
123
124/*
125 * PCI interrupts
126 */
127#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0
128#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1
129#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2
130#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3
131
132#endif // _IOP331_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h
deleted file mode 100644
index fbf0cc11bdd9..000000000000
--- a/include/asm-arm/arch-iop3xx/iop331.h
+++ /dev/null
@@ -1,363 +0,0 @@
1/*
2 * linux/include/asm/arch-iop3xx/iop331.h
3 *
4 * Intel IOP331 Chip definitions
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef _IOP331_HW_H_
15#define _IOP331_HW_H_
16
17
18/*
19 * This is needed for mixed drivers that need to work on all
20 * IOP3xx variants but behave slightly differently on each.
21 */
22#ifndef __ASSEMBLY__
23#ifdef CONFIG_ARCH_IOP331
24/*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */
25#define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010)
26#else
27#define iop_is_331() 0
28#endif
29#endif
30
31/*
32 * IOP331 I/O and Mem space regions for PCI autoconfiguration
33 */
34#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
35#define IOP331_PCI_LOWER_IO_PA 0x90000000
36#define IOP331_PCI_LOWER_IO_VA 0xfe000000
37#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
38#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
39#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
40#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
41#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
42
43/* this can be 128M if OMWTVR1 is set */
44#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
45/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */
46#define IOP331_PCI_LOWER_MEM_PA 0x80000000
47#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
48#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
49#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
50#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
51
52/*
53 * IOP331 chipset registers
54 */
55#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
56#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
57#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
58
59/* Reserved 0x00000000 through 0x000000FF */
60
61/* Address Translation Unit 0x00000100 through 0x000001FF */
62#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
63#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
64#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
65#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
66#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
67#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
68#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
69#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
70#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
71#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
72#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
73#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
74#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
75#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
76#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
77#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
78#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
79#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
80#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
81#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
82/* Reserved 0x00000138 through 0x0000013B */
83#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
84#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
85#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
86#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
87#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
88#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
89#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
90#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
91#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
92#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
93#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
94#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
95#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
96#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
97#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
98#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
99/* Reserved 0x00000170 through 0x00000177*/
100#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
101/* Reserved 0x0000017C through 0x0000017F*/
102#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
103#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
104#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
105#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
106#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
107#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
108#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
109#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
110/* Reserved 0x000001A0 through 0x000001A3*/
111#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
112/* Reserved 0x000001A8 through 0x000001AB*/
113#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
114/* Reserved 0x000001B0 through 0x000001BB*/
115#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
116#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
117#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
118#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
119#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
120#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
121#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
122#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
123/* Reserved 0x000001C6 through 0x000001CF */
124#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
125#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
126#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
127#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
128#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
129#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
130#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
131#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
132#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
133#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
134#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
135
136/* Messaging Unit 0x00000300 through 0x000003FF */
137
138/* Reserved 0x00000300 through 0x0000030c */
139#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310)
140#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314)
141#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318)
142#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
143#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320)
144#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324)
145#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328)
146#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
147#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330)
148#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334)
149/* Reserved 0x00000338 through 0x0000034F */
150#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350)
151#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354)
152/* Reserved 0x00000358 through 0x0000035C */
153#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360)
154#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364)
155#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368)
156#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
157#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370)
158#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374)
159#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378)
160#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
161#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380)
162/* Reserved 0x00000384 through 0x000003FF */
163
164/* DMA Controller 0x00000400 through 0x000004FF */
165#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400)
166#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404)
167#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
168#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410)
169#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414)
170#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
171#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
172#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420)
173#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424)
174/* Reserved 0x00000428 through 0x0000043C */
175#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440)
176#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444)
177#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
178#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450)
179#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454)
180#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
181#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
182#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460)
183#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464)
184/* Reserved 0x00000468 through 0x000004FF */
185
186/* Memory controller 0x00000500 through 0x0005FF */
187
188/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
189#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680)
190#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684)
191#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688)
192#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
193#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690)
194#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694)
195#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698)
196#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
197#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
198#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
199#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
200#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
201#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
202#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
203#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
204/* Reserved 0x000006BC */
205#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
206/* Reserved 0x000006C4 through 0x000006DC */
207#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
208#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
209
210#define IOP331_PBCR_EN 0x1
211
212#define IOP331_PBISR_BOOR_ERR 0x1
213
214
215
216/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
217/* Internal arbitration unit 0x00000780 through 0x0007BF */
218
219/* Interrupt Controller */
220#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790)
221#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794)
222#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798)
223#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
224#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
225#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
226#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
227#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
228#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
229#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
230#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
231#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
232#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
233#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
234#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
235#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
236
237
238/* Timers */
239
240#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
241#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
242
243#define IOP331_TMR_TC 0x01
244#define IOP331_TMR_EN 0x02
245#define IOP331_TMR_RELOAD 0x04
246#define IOP331_TMR_PRIVILEGED 0x09
247
248#define IOP331_TMR_RATIO_1_1 0x00
249#define IOP331_TMR_RATIO_4_1 0x10
250#define IOP331_TMR_RATIO_8_1 0x20
251#define IOP331_TMR_RATIO_16_1 0x30
252
253#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
254#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
255#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
256#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
257#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
258#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
259
260#if defined(CONFIG_ARCH_IOP331)
261#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */
262#endif
263
264#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
265#undef IOP331_TICK_RATE
266#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */
267#endif
268
269/* Application accelerator unit 0x00000800 - 0x000008FF */
270#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
271#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
272#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808)
273#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
274#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810)
275#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814)
276#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818)
277#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
278#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
279#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830)
280#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834)
281#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838)
282#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840)
283#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844)
284#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848)
285#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
286#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850)
287#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854)
288#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858)
289#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
290#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864)
291#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868)
292#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
293#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870)
294#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874)
295#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878)
296#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
297#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880)
298#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888)
299#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
300#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890)
301#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894)
302#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898)
303#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
304#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
305#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
306#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820)
307#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824)
308#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828)
309#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
310#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860)
311#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884)
312
313
314#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
315#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
316/* SSP serial port unit 0x00001600 - 0x0000167F */
317
318/* I2C bus interface unit 0x00001680 - 0x000016FF */
319/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
320
321#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680)
322#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684)
323#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688)
324#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
325/* Reserved 0x00001690 */
326#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694)
327/* Reserved 0x00001698 */
328/* Reserved 0x0000169C */
329#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
330#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
331#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
332#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
333#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
334/* Reserved 0x000016B8 through 0x000016FF */
335
336/* 0x00001700 through 0x0000172C UART 0 */
337
338/* Reserved 0x00001730 through 0x0000173F */
339
340/* 0x00001740 through 0x0000176C UART 1 */
341
342#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
343#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
344#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
345#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
346
347/* Reserved 0x00001770 through 0x0000177F */
348
349/* General Purpose I/O Registers */
350#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780)
351#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784)
352#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788)
353
354/* Reserved 0x0000178c through 0x000019ff */
355
356
357#ifndef __ASSEMBLY__
358extern void iop331_map_io(void);
359extern void iop331_init_irq(void);
360extern void iop331_time_init(void);
361#endif
362
363#endif // _IOP331_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h
deleted file mode 100644
index b2c03f4c269c..000000000000
--- a/include/asm-arm/arch-iop3xx/irqs.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/irqs.h
3 *
4 * Copyright: (C) 2001-2003 MontaVista Software Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/*
13 * Chipset-specific bits
14 */
15#ifdef CONFIG_ARCH_IOP321
16#include "iop321-irqs.h"
17#endif
18
19#ifdef CONFIG_ARCH_IOP331
20#include "iop331-irqs.h"
21#endif
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
deleted file mode 100644
index e43ebd984745..000000000000
--- a/include/asm-arm/arch-iop3xx/memory.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#include <asm/hardware.h>
9
10/*
11 * Physical DRAM offset.
12 */
13#ifndef CONFIG_ARCH_IOP331
14#define PHYS_OFFSET UL(0xa0000000)
15#else
16#define PHYS_OFFSET UL(0x00000000)
17#endif
18
19/*
20 * Virtual view <-> PCI DMA view memory address translations
21 * virt_to_bus: Used to translate the virtual address to an
22 * address suitable to be passed to set_dma_addr
23 * bus_to_virt: Used to convert an address for DMA operations
24 * to an address that the kernel can use.
25 */
26#if defined(CONFIG_ARCH_IOP321)
27
28#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
29#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
30
31#elif defined(CONFIG_ARCH_IOP331)
32
33#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0))
34#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2)))
35
36#endif
37
38#endif
diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h
deleted file mode 100644
index af6ae8cd36c9..000000000000
--- a/include/asm-arm/arch-iop3xx/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/system.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16
17static inline void arch_reset(char mode)
18{
19#ifdef CONFIG_ARCH_IOP321
20 *IOP321_PCSR = 0x30;
21#endif
22
23#ifdef CONFIG_ARCH_IOP331
24 *IOP331_PCSR = 0x30;
25#endif
26
27 if ( 1 && mode == 's') {
28 /* Jump into ROM at address 0 */
29 cpu_reset(0);
30 } else {
31 /* No on-chip reset capability */
32 cpu_reset(0);
33 }
34}
35
diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h
deleted file mode 100644
index 14ca8d0f7b29..000000000000
--- a/include/asm-arm/arch-iop3xx/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/timex.h
3 *
4 * IOP3xx architecture timex specifications
5 */
6#include <asm/hardware.h>
7
8#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
9
10#define CLOCK_TICK_RATE IOP321_TICK_RATE
11
12#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332)
13
14#define CLOCK_TICK_RATE IOP331_TICK_RATE
15
16#else
17
18#error "No IOP3xx timex information for this architecture"
19
20#endif
diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h
deleted file mode 100644
index fbdd5af644fe..000000000000
--- a/include/asm-arm/arch-iop3xx/uncompress.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/uncompress.h
3 */
4#include <asm/types.h>
5#include <asm/mach-types.h>
6#include <linux/serial_reg.h>
7#include <asm/hardware.h>
8
9#ifdef CONFIG_ARCH_IOP321
10#define UTYPE unsigned char *
11#elif defined(CONFIG_ARCH_IOP331)
12#define UTYPE u32 *
13#else
14#error "Missing IOP3xx arch type def"
15#endif
16
17static volatile UTYPE uart_base;
18
19#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
20
21static inline void putc(char c)
22{
23 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
24 barrier();
25 *uart_base = c;
26}
27
28static inline void flush(void)
29{
30}
31
32static __inline__ void __arch_decomp_setup(unsigned long arch_id)
33{
34 if(machine_is_iq80321())
35 uart_base = (volatile UTYPE)IQ80321_UART;
36 else if(machine_is_iq31244())
37 uart_base = (volatile UTYPE)IQ31244_UART;
38 else if(machine_is_iq80331() || machine_is_iq80332())
39 uart_base = (volatile UTYPE)IOP331_UART0_PHYS;
40 else
41 uart_base = (volatile UTYPE)0xfe800000;
42}
43
44/*
45 * nothing to do
46 */
47#define arch_decomp_setup() __arch_decomp_setup(arch_id)
48#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h
deleted file mode 100644
index 0f2f6847f93c..000000000000
--- a/include/asm-arm/arch-iop3xx/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/vmalloc.h
3 */
4
5/*
6 * Just any arbitrary offset to the start of the vmalloc VM area: the
7 * current 8MB value just means that there will be a 8MB "hole" after the
8 * physical memory until the kernel virtual memory starts. That means that
9 * any out-of-bounds memory accesses will hopefully be caught.
10 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
11 * area for the same reason. ;)
12 */
13//#define VMALLOC_END (0xe8000000)
14/* increase usable physical RAM to ~992M per RMK */
15#define VMALLOC_END (0xfe000000)
16
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index cd080d8384d9..d744d97c18a5 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -31,9 +31,9 @@
31static inline unsigned int __arch_getw(unsigned long a) 31static inline unsigned int __arch_getw(unsigned long a)
32{ 32{
33 unsigned int value; 33 unsigned int value;
34 __asm__ __volatile__("ldr%?h %0, [%1, #0] @ getw" 34 __asm__ __volatile__("ldrh %0, [%1, #0] @ getw"
35 : "=&r" (value) 35 : "=&r" (value)
36 : "r" (a)); 36 : "r" (a) : "cc");
37 return value; 37 return value;
38} 38}
39 39
@@ -42,8 +42,8 @@ static inline unsigned int __arch_getw(unsigned long a)
42 42
43static inline void __arch_putw(unsigned int value, unsigned long a) 43static inline void __arch_putw(unsigned int value, unsigned long a)
44{ 44{
45 __asm__ __volatile__("str%?h %0, [%1, #0] @ putw" 45 __asm__ __volatile__("strh %0, [%1, #0] @ putw"
46 : : "r" (value), "r" (a)); 46 : : "r" (value), "r" (a) : "cc");
47} 47}
48 48
49/* 49/*
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 3661e465b0a5..7ac224836971 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -23,6 +23,39 @@
23#define MAX_DMA_ADDRESS 0x40000000 23#define MAX_DMA_ADDRESS 0x40000000
24#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 24#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
25 25
26/* We use `virtual` dma channels to hide the fact we have only a limited
27 * number of DMA channels, and not of all of them (dependant on the device)
28 * can be attached to any DMA source. We therefore let the DMA core handle
29 * the allocation of hardware channels to clients.
30*/
31
32enum dma_ch {
33 DMACH_XD0,
34 DMACH_XD1,
35 DMACH_SDI,
36 DMACH_SPI0,
37 DMACH_SPI1,
38 DMACH_UART0,
39 DMACH_UART1,
40 DMACH_UART2,
41 DMACH_TIMER,
42 DMACH_I2S_IN,
43 DMACH_I2S_OUT,
44 DMACH_PCM_IN,
45 DMACH_PCM_OUT,
46 DMACH_MIC_IN,
47 DMACH_USB_EP1,
48 DMACH_USB_EP2,
49 DMACH_USB_EP3,
50 DMACH_USB_EP4,
51 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
52 DMACH_UART1_SRC2,
53 DMACH_UART2_SRC2,
54 DMACH_MAX, /* the end entry */
55};
56
57#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
58
26/* we have 4 dma channels */ 59/* we have 4 dma channels */
27#define S3C2410_DMA_CHANNELS (4) 60#define S3C2410_DMA_CHANNELS (4)
28 61
@@ -149,6 +182,8 @@ struct s3c2410_dma_stats {
149 unsigned long timeout_failed; 182 unsigned long timeout_failed;
150}; 183};
151 184
185struct s3c2410_dma_map;
186
152/* struct s3c2410_dma_chan 187/* struct s3c2410_dma_chan
153 * 188 *
154 * full state information for each DMA channel 189 * full state information for each DMA channel
@@ -174,6 +209,8 @@ struct s3c2410_dma_chan {
174 unsigned long load_timeout; 209 unsigned long load_timeout;
175 unsigned int flags; /* channel flags */ 210 unsigned int flags; /* channel flags */
176 211
212 struct s3c24xx_dma_map *map; /* channel hw maps */
213
177 /* channel's hardware position and configuration */ 214 /* channel's hardware position and configuration */
178 void __iomem *regs; /* channels registers */ 215 void __iomem *regs; /* channels registers */
179 void __iomem *addr_reg; /* data address register */ 216 void __iomem *addr_reg; /* data address register */
@@ -283,6 +320,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
283#define S3C2410_DMA_DCSRC (0x18) 320#define S3C2410_DMA_DCSRC (0x18)
284#define S3C2410_DMA_DCDST (0x1C) 321#define S3C2410_DMA_DCDST (0x1C)
285#define S3C2410_DMA_DMASKTRIG (0x20) 322#define S3C2410_DMA_DMASKTRIG (0x20)
323#define S3C2412_DMA_DMAREQSEL (0x24)
286 324
287#define S3C2410_DISRCC_INC (1<<0) 325#define S3C2410_DISRCC_INC (1<<0)
288#define S3C2410_DISRCC_APB (1<<1) 326#define S3C2410_DISRCC_APB (1<<1)
@@ -349,4 +387,32 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
349#define S3C2440_DCON_CH3_PCMOUT (6<<24) 387#define S3C2440_DCON_CH3_PCMOUT (6<<24)
350#endif 388#endif
351 389
390#ifdef CONFIG_CPU_S3C2412
391
392#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
393
394#define S3C2412_DMAREQSEL_HW (1)
395
396#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
397#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
398#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
399#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
400#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
401#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
402#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
403#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
404#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
405#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
406#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
407#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
408#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
409#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
410#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
411#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
412#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
413#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
414#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
415#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
416
417#endif
352#endif /* __ASM_ARCH_DMA_H */ 418#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 27ba0ac3fdd5..7895042d176b 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -160,6 +160,11 @@
160#define S3C2440_PA_CAMIF (0x4F000000) 160#define S3C2440_PA_CAMIF (0x4F000000)
161#define S3C2440_SZ_CAMIF SZ_1M 161#define S3C2440_SZ_CAMIF SZ_1M
162 162
163/* AC97 */
164
165#define S3C2440_PA_AC97 (0x5B000000)
166#define S3C2440_SZ_AC97 SZ_1M
167
163/* ISA style IO, for each machine to sort out mappings for, if it 168/* ISA style IO, for each machine to sort out mappings for, if it
164 * implements it. We reserve two 16M regions for ISA. 169 * implements it. We reserve two 16M regions for ISA.
165 */ 170 */
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h
index e2d406218ae5..a14164dfa525 100644
--- a/include/asm-arm/arch-s3c2410/osiris-map.h
+++ b/include/asm-arm/arch-s3c2410/osiris-map.h
@@ -18,22 +18,22 @@
18 18
19/* start peripherals off after the S3C2410 */ 19/* start peripherals off after the S3C2410 */
20 20
21#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x05000000)) 21#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000))
22 22
23#define OSIRIS_PA_CPLD (S3C2410_CS1 | (3<<25)) 23#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26))
24 24
25/* we put the CPLD registers next, to get them out of the way */ 25/* we put the CPLD registers next, to get them out of the way */
26 26
27#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) /* 0x01300000 */ 27#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000)
28#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD) 28#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD)
29 29
30#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) /* 0x01400000 */ 30#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000)
31#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<24)) 31#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23))
32 32
33#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) /* 0x01500000 */ 33#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000)
34#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<24)) 34#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
35 35
36#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) /* 0x01600000 */ 36#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000)
37#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<24)) 37#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23))
38 38
39#endif /* __ASM_ARCH_OSIRISMAP_H */ 39#endif /* __ASM_ARCH_OSIRISMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/arch-s3c2410/regs-ac97.h
new file mode 100644
index 000000000000..bdd6a4f93d7f
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-ac97.h
@@ -0,0 +1,23 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
2 *
3 * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 AC97 Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_AC97_H
14#define __ASM_ARCH_REGS_AC97_H __FILE__
15
16#define S3C_AC97_GLBCTRL (0x00)
17#define S3C_AC97_GLBSTAT (0x04)
18#define S3C_AC97_CODEC_CMD (0x08)
19#define S3C_AC97_PCM_ADDR (0x10)
20#define S3C_AC97_PCM_DATA (0x18)
21#define S3C_AC97_MIC_DATA (0x1C)
22
23#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b306d6e3135d..6d7881c8cfc8 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -63,6 +63,8 @@
63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) 63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) 64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
65 65
66/* LDCCON4 changes for STN mode on the S3C2412 */
67
66#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) 68#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
67#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) 69#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
68#define S3C2410_LCDCON4_WLH(x) ((x) << 0) 70#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
@@ -113,10 +115,38 @@
113#define S3C2410_LCDINT_FRSYNC (1<<1) 115#define S3C2410_LCDINT_FRSYNC (1<<1)
114#define S3C2410_LCDINT_FICNT (1<<0) 116#define S3C2410_LCDINT_FICNT (1<<0)
115 117
118/* s3c2442 extra stn registers */
119
120#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
121#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
122#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
123#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
124
116#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) 125#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
117 126
118#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) 127#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
119 128
129/* S3C2412 registers */
130
131#define S3C2412_TPAL S3C2410_LCDREG(0x20)
132
133#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
134#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
135#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
136
137#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
138
139#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
140#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
141#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
142#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
143
144#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
145#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
146#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
147
148#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
149
120#endif /* ___ASM_ARCH_REGS_LCD_H */ 150#endif /* ___ASM_ARCH_REGS_LCD_H */
121 151
122 152
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index 4b0ce3e7de9a..ea88aa6bfc78 100644
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -128,10 +128,10 @@ static inline int atomic_add_return(int i, atomic_t *v)
128 unsigned long flags; 128 unsigned long flags;
129 int val; 129 int val;
130 130
131 local_irq_save(flags); 131 raw_local_irq_save(flags);
132 val = v->counter; 132 val = v->counter;
133 v->counter = val += i; 133 v->counter = val += i;
134 local_irq_restore(flags); 134 raw_local_irq_restore(flags);
135 135
136 return val; 136 return val;
137} 137}
@@ -141,10 +141,10 @@ static inline int atomic_sub_return(int i, atomic_t *v)
141 unsigned long flags; 141 unsigned long flags;
142 int val; 142 int val;
143 143
144 local_irq_save(flags); 144 raw_local_irq_save(flags);
145 val = v->counter; 145 val = v->counter;
146 v->counter = val -= i; 146 v->counter = val -= i;
147 local_irq_restore(flags); 147 raw_local_irq_restore(flags);
148 148
149 return val; 149 return val;
150} 150}
@@ -154,11 +154,11 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
154 int ret; 154 int ret;
155 unsigned long flags; 155 unsigned long flags;
156 156
157 local_irq_save(flags); 157 raw_local_irq_save(flags);
158 ret = v->counter; 158 ret = v->counter;
159 if (likely(ret == old)) 159 if (likely(ret == old))
160 v->counter = new; 160 v->counter = new;
161 local_irq_restore(flags); 161 raw_local_irq_restore(flags);
162 162
163 return ret; 163 return ret;
164} 164}
@@ -167,9 +167,9 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
167{ 167{
168 unsigned long flags; 168 unsigned long flags;
169 169
170 local_irq_save(flags); 170 raw_local_irq_save(flags);
171 *addr &= ~mask; 171 *addr &= ~mask;
172 local_irq_restore(flags); 172 raw_local_irq_restore(flags);
173} 173}
174 174
175#endif /* __LINUX_ARM_ARCH__ */ 175#endif /* __LINUX_ARM_ARCH__ */
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 0ac54b1a8bad..b41831b6432f 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -37,9 +37,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *
37 37
38 p += bit >> 5; 38 p += bit >> 5;
39 39
40 local_irq_save(flags); 40 raw_local_irq_save(flags);
41 *p |= mask; 41 *p |= mask;
42 local_irq_restore(flags); 42 raw_local_irq_restore(flags);
43} 43}
44 44
45static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p) 45static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
@@ -49,9 +49,9 @@ static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long
49 49
50 p += bit >> 5; 50 p += bit >> 5;
51 51
52 local_irq_save(flags); 52 raw_local_irq_save(flags);
53 *p &= ~mask; 53 *p &= ~mask;
54 local_irq_restore(flags); 54 raw_local_irq_restore(flags);
55} 55}
56 56
57static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p) 57static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
@@ -61,9 +61,9 @@ static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned lon
61 61
62 p += bit >> 5; 62 p += bit >> 5;
63 63
64 local_irq_save(flags); 64 raw_local_irq_save(flags);
65 *p ^= mask; 65 *p ^= mask;
66 local_irq_restore(flags); 66 raw_local_irq_restore(flags);
67} 67}
68 68
69static inline int 69static inline int
@@ -75,10 +75,10 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
75 75
76 p += bit >> 5; 76 p += bit >> 5;
77 77
78 local_irq_save(flags); 78 raw_local_irq_save(flags);
79 res = *p; 79 res = *p;
80 *p = res | mask; 80 *p = res | mask;
81 local_irq_restore(flags); 81 raw_local_irq_restore(flags);
82 82
83 return res & mask; 83 return res & mask;
84} 84}
@@ -92,10 +92,10 @@ ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
92 92
93 p += bit >> 5; 93 p += bit >> 5;
94 94
95 local_irq_save(flags); 95 raw_local_irq_save(flags);
96 res = *p; 96 res = *p;
97 *p = res & ~mask; 97 *p = res & ~mask;
98 local_irq_restore(flags); 98 raw_local_irq_restore(flags);
99 99
100 return res & mask; 100 return res & mask;
101} 101}
@@ -109,10 +109,10 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
109 109
110 p += bit >> 5; 110 p += bit >> 5;
111 111
112 local_irq_save(flags); 112 raw_local_irq_save(flags);
113 res = *p; 113 res = *p;
114 *p = res ^ mask; 114 *p = res ^ mask;
115 local_irq_restore(flags); 115 raw_local_irq_restore(flags);
116 116
117 return res & mask; 117 return res & mask;
118} 118}
diff --git a/include/asm-arm/flat.h b/include/asm-arm/flat.h
new file mode 100644
index 000000000000..966946478589
--- /dev/null
+++ b/include/asm-arm/flat.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-arm/flat.h -- uClinux flat-format executables
3 */
4
5#ifndef __ARM_FLAT_H__
6#define __ARM_FLAT_H__
7
8#define flat_stack_align(sp) /* nothing needed */
9#define flat_argvp_envp_on_stack() 1
10#define flat_old_ram_flag(flags) (flags)
11#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
12#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp)
13#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
14#define flat_get_relocate_addr(rel) (rel)
15
16#endif /* __ARM_FLAT_H__ */
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
new file mode 100644
index 000000000000..1018a7486ab7
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -0,0 +1,301 @@
1/*
2 * include/asm-arm/hardware/iop3xx.h
3 *
4 * Intel IOP32X and IOP33X register definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __IOP3XX_H
16#define __IOP3XX_H
17
18/*
19 * IOP3XX GPIO handling
20 */
21#define GPIO_IN 0
22#define GPIO_OUT 1
23#define GPIO_LOW 0
24#define GPIO_HIGH 1
25#define IOP3XX_GPIO_LINE(x) (x)
26
27#ifndef __ASSEMBLY__
28extern void gpio_line_config(int line, int direction);
29extern int gpio_line_get(int line);
30extern void gpio_line_set(int line, int value);
31#endif
32
33
34/*
35 * IOP3XX processor registers
36 */
37#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
38#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
39#define IOP3XX_PERIPHERAL_SIZE 0x00002000
40#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
41
42/* Address Translation Unit */
43#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
44#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
45#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
46#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
47#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
48#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
49#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
50#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
51#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
52#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
53#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
54#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
55#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
56#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
57#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
58#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
59#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
60#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
61#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
62#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
63#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
64#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
65#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
66#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
67#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
68#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
69#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
70#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
71#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
72#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
73#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
74#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
75#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
76#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
77#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
78#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
79#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
80#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
81#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
82#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
83#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
84#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
85#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
86#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
87#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
88#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
89#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
90#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
91#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
92#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
93#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
94#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
95#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
96#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
97#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
98#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
99
100/* Messaging Unit */
101#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
102#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
103#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
104#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
105#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
106#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
107#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
108#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
109#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
110#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
111#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
112#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
113#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
114#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
115#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
116#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
117#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
118#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
119#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
120#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
121#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
122
123/* DMA Controller */
124#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
125#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
126#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
127#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
128#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
129#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
130#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
131#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
132#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
133#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
134#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
135#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
136#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
137#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
138#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
139#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
140#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
141#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
142
143/* Peripheral bus interface */
144#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
145#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
146#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
147#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
148#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
149#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
150#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
151#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
152#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
153#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
154#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
155#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
156#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
157#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
158#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
159#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
160#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
161
162/* Peripheral performance monitoring unit */
163#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
164#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
165#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
166#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
167/* PERCR0 DOESN'T EXIST - index from 1! */
168#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
169
170/* General Purpose I/O */
171#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
172#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
173#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x000c)
174
175/* Timers */
176#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
177#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
178#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
179#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
180#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
181#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
182#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
183#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
184#define IOP3XX_TMR_TC 0x01
185#define IOP3XX_TMR_EN 0x02
186#define IOP3XX_TMR_RELOAD 0x04
187#define IOP3XX_TMR_PRIVILEGED 0x09
188#define IOP3XX_TMR_RATIO_1_1 0x00
189#define IOP3XX_TMR_RATIO_4_1 0x10
190#define IOP3XX_TMR_RATIO_8_1 0x20
191#define IOP3XX_TMR_RATIO_16_1 0x30
192
193/* Application accelerator unit */
194#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
195#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
196#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
197#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
198#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
199#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
200#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
201#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
202#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
203#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
204#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
205#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
206#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
207#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
208#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
209#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
210#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
211#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
212#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
213#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
214#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
215#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
216#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
217#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
218#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
219#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
220#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
221#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
222#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
223#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
224#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
225#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
226#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
227#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
228#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
229#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
230#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
231#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
232#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
233#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
234#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
235#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
236
237/* I2C bus interface unit */
238#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
239#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
240#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
241#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
242#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
243#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
244#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
245#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
246#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
247#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
248
249
250/*
251 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
252 */
253#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
254#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
255#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
256
257#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
258#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
259#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
260#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
261
262
263#ifndef __ASSEMBLY__
264void iop3xx_map_io(void);
265void iop3xx_init_time(unsigned long);
266unsigned long iop3xx_gettimeoffset(void);
267
268extern struct platform_device iop3xx_i2c0_device;
269extern struct platform_device iop3xx_i2c1_device;
270
271extern inline void iop3xx_cp6_enable(void)
272{
273 u32 temp;
274
275 asm volatile (
276 "mrc p15, 0, %0, c15, c1, 0\n\t"
277 "orr %0, %0, #(1 << 6)\n\t"
278 "mcr p15, 0, %0, c15, c1, 0\n\t"
279 "mrc p15, 0, %0, c15, c1, 0\n\t"
280 "mov %0, %0\n\t"
281 "sub pc, pc, #4\n\t"
282 : "=r" (temp) );
283}
284
285extern inline void iop3xx_cp6_disable(void)
286{
287 u32 temp;
288
289 asm volatile (
290 "mrc p15, 0, %0, c15, c1, 0\n\t"
291 "bic %0, %0, #(1 << 6)\n\t"
292 "mcr p15, 0, %0, c15, c1, 0\n\t"
293 "mrc p15, 0, %0, c15, c1, 0\n\t"
294 "mov %0, %0\n\t"
295 "sub pc, pc, #4\n\t"
296 : "=r" (temp) );
297}
298#endif
299
300
301#endif
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index bf7b9dea30f1..8076a85c3675 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -280,6 +280,10 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
280#define BIOVEC_MERGEABLE(vec1, vec2) \ 280#define BIOVEC_MERGEABLE(vec1, vec2) \
281 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) 281 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
282 282
283#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
284extern int valid_phys_addr_range(unsigned long addr, size_t size);
285extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
286
283/* 287/*
284 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 288 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
285 * access 289 * access
diff --git a/include/asm-arm/irqflags.h b/include/asm-arm/irqflags.h
new file mode 100644
index 000000000000..6d09974e6646
--- /dev/null
+++ b/include/asm-arm/irqflags.h
@@ -0,0 +1,132 @@
1#ifndef __ASM_ARM_IRQFLAGS_H
2#define __ASM_ARM_IRQFLAGS_H
3
4#ifdef __KERNEL__
5
6#include <asm/ptrace.h>
7
8/*
9 * CPU interrupt mask handling.
10 */
11#if __LINUX_ARM_ARCH__ >= 6
12
13#define raw_local_irq_save(x) \
14 ({ \
15 __asm__ __volatile__( \
16 "mrs %0, cpsr @ local_irq_save\n" \
17 "cpsid i" \
18 : "=r" (x) : : "memory", "cc"); \
19 })
20
21#define raw_local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
22#define raw_local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
23#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
24#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
25
26#else
27
28/*
29 * Save the current interrupt enable state & disable IRQs
30 */
31#define raw_local_irq_save(x) \
32 ({ \
33 unsigned long temp; \
34 (void) (&temp == &x); \
35 __asm__ __volatile__( \
36 "mrs %0, cpsr @ local_irq_save\n" \
37" orr %1, %0, #128\n" \
38" msr cpsr_c, %1" \
39 : "=r" (x), "=r" (temp) \
40 : \
41 : "memory", "cc"); \
42 })
43
44/*
45 * Enable IRQs
46 */
47#define raw_local_irq_enable() \
48 ({ \
49 unsigned long temp; \
50 __asm__ __volatile__( \
51 "mrs %0, cpsr @ local_irq_enable\n" \
52" bic %0, %0, #128\n" \
53" msr cpsr_c, %0" \
54 : "=r" (temp) \
55 : \
56 : "memory", "cc"); \
57 })
58
59/*
60 * Disable IRQs
61 */
62#define raw_local_irq_disable() \
63 ({ \
64 unsigned long temp; \
65 __asm__ __volatile__( \
66 "mrs %0, cpsr @ local_irq_disable\n" \
67" orr %0, %0, #128\n" \
68" msr cpsr_c, %0" \
69 : "=r" (temp) \
70 : \
71 : "memory", "cc"); \
72 })
73
74/*
75 * Enable FIQs
76 */
77#define local_fiq_enable() \
78 ({ \
79 unsigned long temp; \
80 __asm__ __volatile__( \
81 "mrs %0, cpsr @ stf\n" \
82" bic %0, %0, #64\n" \
83" msr cpsr_c, %0" \
84 : "=r" (temp) \
85 : \
86 : "memory", "cc"); \
87 })
88
89/*
90 * Disable FIQs
91 */
92#define local_fiq_disable() \
93 ({ \
94 unsigned long temp; \
95 __asm__ __volatile__( \
96 "mrs %0, cpsr @ clf\n" \
97" orr %0, %0, #64\n" \
98" msr cpsr_c, %0" \
99 : "=r" (temp) \
100 : \
101 : "memory", "cc"); \
102 })
103
104#endif
105
106/*
107 * Save the current interrupt enable state.
108 */
109#define raw_local_save_flags(x) \
110 ({ \
111 __asm__ __volatile__( \
112 "mrs %0, cpsr @ local_save_flags" \
113 : "=r" (x) : : "memory", "cc"); \
114 })
115
116/*
117 * restore saved IRQ & FIQ state
118 */
119#define raw_local_irq_restore(x) \
120 __asm__ __volatile__( \
121 "msr cpsr_c, %0 @ local_irq_restore\n" \
122 : \
123 : "r" (x) \
124 : "memory", "cc")
125
126#define raw_irqs_disabled_flags(flags) \
127({ \
128 (int)((flags) & PSR_I_BIT); \
129})
130
131#endif
132#endif
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
index 923e0ca66200..24621c49a0c7 100644
--- a/include/asm-arm/mach/pci.h
+++ b/include/asm-arm/mach/pci.h
@@ -52,13 +52,9 @@ void pci_common_init(struct hw_pci *);
52/* 52/*
53 * PCI controllers 53 * PCI controllers
54 */ 54 */
55extern int iop321_setup(int nr, struct pci_sys_data *); 55extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
56extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *); 56extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
57extern void iop321_init(void); 57extern void iop3xx_pci_preinit(void);
58
59extern int iop331_setup(int nr, struct pci_sys_data *);
60extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
61extern void iop331_init(void);
62 58
63extern int dc21285_setup(int nr, struct pci_sys_data *); 59extern int dc21285_setup(int nr, struct pci_sys_data *);
64extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); 60extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 02bd3ee935b0..7e85db77d99b 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -174,9 +174,6 @@ typedef unsigned long pgprot_t;
174 174
175#endif /* STRICT_MM_TYPECHECKS */ 175#endif /* STRICT_MM_TYPECHECKS */
176 176
177/* the upper-most page table pointer */
178extern pmd_t *top_pmd;
179
180#endif /* CONFIG_MMU */ 177#endif /* CONFIG_MMU */
181 178
182#include <asm/memory.h> 179#include <asm/memory.h>
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 8d3919c6458c..38b2b55688e2 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -136,6 +136,13 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
136#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR) 136#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
137 137
138/* 138/*
139 * section address mask and size definitions.
140 */
141#define SECTION_SHIFT 20
142#define SECTION_SIZE (1UL << SECTION_SHIFT)
143#define SECTION_MASK (~(SECTION_SIZE-1))
144
145/*
139 * ARMv6 supersection address mask and size definitions. 146 * ARMv6 supersection address mask and size definitions.
140 */ 147 */
141#define SUPERSECTION_SHIFT 24 148#define SUPERSECTION_SHIFT 24
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 0947cbf9b69a..c19c5b009f71 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -207,130 +207,7 @@ static inline void sched_cacheflush(void)
207{ 207{
208} 208}
209 209
210/* 210#include <linux/irqflags.h>
211 * CPU interrupt mask handling.
212 */
213#if __LINUX_ARM_ARCH__ >= 6
214
215#define local_irq_save(x) \
216 ({ \
217 __asm__ __volatile__( \
218 "mrs %0, cpsr @ local_irq_save\n" \
219 "cpsid i" \
220 : "=r" (x) : : "memory", "cc"); \
221 })
222
223#define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
224#define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
225#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
226#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
227
228#else
229
230/*
231 * Save the current interrupt enable state & disable IRQs
232 */
233#define local_irq_save(x) \
234 ({ \
235 unsigned long temp; \
236 (void) (&temp == &x); \
237 __asm__ __volatile__( \
238 "mrs %0, cpsr @ local_irq_save\n" \
239" orr %1, %0, #128\n" \
240" msr cpsr_c, %1" \
241 : "=r" (x), "=r" (temp) \
242 : \
243 : "memory", "cc"); \
244 })
245
246/*
247 * Enable IRQs
248 */
249#define local_irq_enable() \
250 ({ \
251 unsigned long temp; \
252 __asm__ __volatile__( \
253 "mrs %0, cpsr @ local_irq_enable\n" \
254" bic %0, %0, #128\n" \
255" msr cpsr_c, %0" \
256 : "=r" (temp) \
257 : \
258 : "memory", "cc"); \
259 })
260
261/*
262 * Disable IRQs
263 */
264#define local_irq_disable() \
265 ({ \
266 unsigned long temp; \
267 __asm__ __volatile__( \
268 "mrs %0, cpsr @ local_irq_disable\n" \
269" orr %0, %0, #128\n" \
270" msr cpsr_c, %0" \
271 : "=r" (temp) \
272 : \
273 : "memory", "cc"); \
274 })
275
276/*
277 * Enable FIQs
278 */
279#define local_fiq_enable() \
280 ({ \
281 unsigned long temp; \
282 __asm__ __volatile__( \
283 "mrs %0, cpsr @ stf\n" \
284" bic %0, %0, #64\n" \
285" msr cpsr_c, %0" \
286 : "=r" (temp) \
287 : \
288 : "memory", "cc"); \
289 })
290
291/*
292 * Disable FIQs
293 */
294#define local_fiq_disable() \
295 ({ \
296 unsigned long temp; \
297 __asm__ __volatile__( \
298 "mrs %0, cpsr @ clf\n" \
299" orr %0, %0, #64\n" \
300" msr cpsr_c, %0" \
301 : "=r" (temp) \
302 : \
303 : "memory", "cc"); \
304 })
305
306#endif
307
308/*
309 * Save the current interrupt enable state.
310 */
311#define local_save_flags(x) \
312 ({ \
313 __asm__ __volatile__( \
314 "mrs %0, cpsr @ local_save_flags" \
315 : "=r" (x) : : "memory", "cc"); \
316 })
317
318/*
319 * restore saved IRQ & FIQ state
320 */
321#define local_irq_restore(x) \
322 __asm__ __volatile__( \
323 "msr cpsr_c, %0 @ local_irq_restore\n" \
324 : \
325 : "r" (x) \
326 : "memory", "cc")
327
328#define irqs_disabled() \
329({ \
330 unsigned long flags; \
331 local_save_flags(flags); \
332 (int)(flags & PSR_I_BIT); \
333})
334 211
335#ifdef CONFIG_SMP 212#ifdef CONFIG_SMP
336 213
@@ -405,17 +282,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
405#error SMP is not supported on this platform 282#error SMP is not supported on this platform
406#endif 283#endif
407 case 1: 284 case 1:
408 local_irq_save(flags); 285 raw_local_irq_save(flags);
409 ret = *(volatile unsigned char *)ptr; 286 ret = *(volatile unsigned char *)ptr;
410 *(volatile unsigned char *)ptr = x; 287 *(volatile unsigned char *)ptr = x;
411 local_irq_restore(flags); 288 raw_local_irq_restore(flags);
412 break; 289 break;
413 290
414 case 4: 291 case 4:
415 local_irq_save(flags); 292 raw_local_irq_save(flags);
416 ret = *(volatile unsigned long *)ptr; 293 ret = *(volatile unsigned long *)ptr;
417 *(volatile unsigned long *)ptr = x; 294 *(volatile unsigned long *)ptr = x;
418 local_irq_restore(flags); 295 raw_local_irq_restore(flags);
419 break; 296 break;
420#else 297#else
421 case 1: 298 case 1:
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index d97fc76189a5..cd10a0b5f8ae 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -247,16 +247,16 @@ static inline void local_flush_tlb_all(void)
247 const unsigned int __tlb_flag = __cpu_tlb_flags; 247 const unsigned int __tlb_flag = __cpu_tlb_flags;
248 248
249 if (tlb_flag(TLB_WB)) 249 if (tlb_flag(TLB_WB))
250 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); 250 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
251 251
252 if (tlb_flag(TLB_V3_FULL)) 252 if (tlb_flag(TLB_V3_FULL))
253 asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero)); 253 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
254 if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL)) 254 if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
255 asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero)); 255 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
256 if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL)) 256 if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
257 asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero)); 257 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
258 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) 258 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
259 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); 259 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
260} 260}
261 261
262static inline void local_flush_tlb_mm(struct mm_struct *mm) 262static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -266,25 +266,25 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
266 const unsigned int __tlb_flag = __cpu_tlb_flags; 266 const unsigned int __tlb_flag = __cpu_tlb_flags;
267 267
268 if (tlb_flag(TLB_WB)) 268 if (tlb_flag(TLB_WB))
269 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); 269 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
270 270
271 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { 271 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
272 if (tlb_flag(TLB_V3_FULL)) 272 if (tlb_flag(TLB_V3_FULL))
273 asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero)); 273 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
274 if (tlb_flag(TLB_V4_U_FULL)) 274 if (tlb_flag(TLB_V4_U_FULL))
275 asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero)); 275 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
276 if (tlb_flag(TLB_V4_D_FULL)) 276 if (tlb_flag(TLB_V4_D_FULL))
277 asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero)); 277 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
278 if (tlb_flag(TLB_V4_I_FULL)) 278 if (tlb_flag(TLB_V4_I_FULL))
279 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); 279 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
280 } 280 }
281 281
282 if (tlb_flag(TLB_V6_U_ASID)) 282 if (tlb_flag(TLB_V6_U_ASID))
283 asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid)); 283 asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
284 if (tlb_flag(TLB_V6_D_ASID)) 284 if (tlb_flag(TLB_V6_D_ASID))
285 asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid)); 285 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
286 if (tlb_flag(TLB_V6_I_ASID)) 286 if (tlb_flag(TLB_V6_I_ASID))
287 asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid)); 287 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
288} 288}
289 289
290static inline void 290static inline void
@@ -296,27 +296,27 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
296 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); 296 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
297 297
298 if (tlb_flag(TLB_WB)) 298 if (tlb_flag(TLB_WB))
299 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); 299 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero));
300 300
301 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 301 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
302 if (tlb_flag(TLB_V3_PAGE)) 302 if (tlb_flag(TLB_V3_PAGE))
303 asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr)); 303 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
304 if (tlb_flag(TLB_V4_U_PAGE)) 304 if (tlb_flag(TLB_V4_U_PAGE))
305 asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr)); 305 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
306 if (tlb_flag(TLB_V4_D_PAGE)) 306 if (tlb_flag(TLB_V4_D_PAGE))
307 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr)); 307 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
308 if (tlb_flag(TLB_V4_I_PAGE)) 308 if (tlb_flag(TLB_V4_I_PAGE))
309 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); 309 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
310 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 310 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
311 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); 311 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
312 } 312 }
313 313
314 if (tlb_flag(TLB_V6_U_PAGE)) 314 if (tlb_flag(TLB_V6_U_PAGE))
315 asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr)); 315 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
316 if (tlb_flag(TLB_V6_D_PAGE)) 316 if (tlb_flag(TLB_V6_D_PAGE))
317 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr)); 317 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
318 if (tlb_flag(TLB_V6_I_PAGE)) 318 if (tlb_flag(TLB_V6_I_PAGE))
319 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); 319 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
320} 320}
321 321
322static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 322static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -327,31 +327,31 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
327 kaddr &= PAGE_MASK; 327 kaddr &= PAGE_MASK;
328 328
329 if (tlb_flag(TLB_WB)) 329 if (tlb_flag(TLB_WB))
330 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); 330 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
331 331
332 if (tlb_flag(TLB_V3_PAGE)) 332 if (tlb_flag(TLB_V3_PAGE))
333 asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr)); 333 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
334 if (tlb_flag(TLB_V4_U_PAGE)) 334 if (tlb_flag(TLB_V4_U_PAGE))
335 asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr)); 335 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
336 if (tlb_flag(TLB_V4_D_PAGE)) 336 if (tlb_flag(TLB_V4_D_PAGE))
337 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr)); 337 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
338 if (tlb_flag(TLB_V4_I_PAGE)) 338 if (tlb_flag(TLB_V4_I_PAGE))
339 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr)); 339 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
340 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 340 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
341 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); 341 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
342 342
343 if (tlb_flag(TLB_V6_U_PAGE)) 343 if (tlb_flag(TLB_V6_U_PAGE))
344 asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr)); 344 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
345 if (tlb_flag(TLB_V6_D_PAGE)) 345 if (tlb_flag(TLB_V6_D_PAGE))
346 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr)); 346 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
347 if (tlb_flag(TLB_V6_I_PAGE)) 347 if (tlb_flag(TLB_V6_I_PAGE))
348 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr)); 348 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
349 349
350 /* The ARM ARM states that the completion of a TLB maintenance 350 /* The ARM ARM states that the completion of a TLB maintenance
351 * operation is only guaranteed by a DSB instruction 351 * operation is only guaranteed by a DSB instruction
352 */ 352 */
353 if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE)) 353 if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
354 asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); 354 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
355} 355}
356 356
357/* 357/*
@@ -373,11 +373,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
373 const unsigned int __tlb_flag = __cpu_tlb_flags; 373 const unsigned int __tlb_flag = __cpu_tlb_flags;
374 374
375 if (tlb_flag(TLB_DCLEAN)) 375 if (tlb_flag(TLB_DCLEAN))
376 asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd" 376 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
377 : : "r" (pmd)); 377 : : "r" (pmd) : "cc");
378 if (tlb_flag(TLB_WB)) 378 if (tlb_flag(TLB_WB))
379 asm("mcr%? p15, 0, %0, c7, c10, 4 @ flush_pmd" 379 asm("mcr p15, 0, %0, c7, c10, 4 @ flush_pmd"
380 : : "r" (zero)); 380 : : "r" (zero) : "cc");
381} 381}
382 382
383static inline void clean_pmd_entry(pmd_t *pmd) 383static inline void clean_pmd_entry(pmd_t *pmd)
@@ -385,8 +385,8 @@ static inline void clean_pmd_entry(pmd_t *pmd)
385 const unsigned int __tlb_flag = __cpu_tlb_flags; 385 const unsigned int __tlb_flag = __cpu_tlb_flags;
386 386
387 if (tlb_flag(TLB_DCLEAN)) 387 if (tlb_flag(TLB_DCLEAN))
388 asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd" 388 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
389 : : "r" (pmd)); 389 : : "r" (pmd) : "cc");
390} 390}
391 391
392#undef tlb_flag 392#undef tlb_flag
diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h
index 1b39c2f322c9..795b9e5b9e6a 100644
--- a/include/asm-arm/unaligned.h
+++ b/include/asm-arm/unaligned.h
@@ -3,7 +3,7 @@
3 3
4#include <asm/types.h> 4#include <asm/types.h>
5 5
6extern int __bug_unaligned_x(void *ptr); 6extern int __bug_unaligned_x(const void *ptr);
7 7
8/* 8/*
9 * What is the most efficient way of loading/storing an unaligned value? 9 * What is the most efficient way of loading/storing an unaligned value?
@@ -51,44 +51,32 @@ extern int __bug_unaligned_x(void *ptr);
51#define __get_unaligned_4_be(__p) \ 51#define __get_unaligned_4_be(__p) \
52 (__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3]) 52 (__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3])
53 53
54#define __get_unaligned_le(ptr) \ 54#define __get_unaligned_8_le(__p) \
55 ({ \ 55 ((unsigned long long)__get_unaligned_4_le((__p+4)) << 32 | \
56 __typeof__(*(ptr)) __v; \ 56 __get_unaligned_4_le(__p))
57 __u8 *__p = (__u8 *)(ptr); \ 57
58 switch (sizeof(*(ptr))) { \ 58#define __get_unaligned_8_be(__p) \
59 case 1: __v = *(ptr); break; \ 59 ((unsigned long long)__get_unaligned_4_be(__p) << 32 | \
60 case 2: __v = __get_unaligned_2_le(__p); break; \ 60 __get_unaligned_4_be((__p+4)))
61 case 4: __v = __get_unaligned_4_le(__p); break; \ 61
62 case 8: { \ 62#define __get_unaligned_le(ptr) \
63 unsigned int __v1, __v2; \ 63 ({ \
64 __v2 = __get_unaligned_4_le((__p+4)); \ 64 const __u8 *__p = (const __u8 *)(ptr); \
65 __v1 = __get_unaligned_4_le(__p); \ 65 __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \
66 __v = ((unsigned long long)__v2 << 32 | __v1); \ 66 __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_le(__p), \
67 } \ 67 __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_le(__p), \
68 break; \ 68 __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_le(__p), \
69 default: __v = __bug_unaligned_x(__p); break; \ 69 (void)__bug_unaligned_x(__p))))); \
70 } \
71 __v; \
72 }) 70 })
73 71
74#define __get_unaligned_be(ptr) \ 72#define __get_unaligned_be(ptr) \
75 ({ \ 73 ({ \
76 __typeof__(*(ptr)) __v; \ 74 const __u8 *__p = (const __u8 *)(ptr); \
77 __u8 *__p = (__u8 *)(ptr); \ 75 __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \
78 switch (sizeof(*(ptr))) { \ 76 __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_be(__p), \
79 case 1: __v = *(ptr); break; \ 77 __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_be(__p), \
80 case 2: __v = __get_unaligned_2_be(__p); break; \ 78 __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_be(__p), \
81 case 4: __v = __get_unaligned_4_be(__p); break; \ 79 (void)__bug_unaligned_x(__p))))); \
82 case 8: { \
83 unsigned int __v1, __v2; \
84 __v2 = __get_unaligned_4_be(__p); \
85 __v1 = __get_unaligned_4_be((__p+4)); \
86 __v = ((unsigned long long)__v2 << 32 | __v1); \
87 } \
88 break; \
89 default: __v = __bug_unaligned_x(__p); break; \
90 } \
91 __v; \
92 }) 80 })
93 81
94 82
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 02:04:36 -0500