116 files changed, 2719 insertions, 820 deletions
diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
new file mode 100644
index 000000000000..0e9b7e18af05
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/aaec2000.h
@@ -0,0 +1,151 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/aaec2000.h
+ *
+ *  AAEC-2000 registers definition
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_AAEC2000_H
+#define __ASM_ARCH_AAEC2000_H
+#ifndef __ASM_ARCH_HARDWARE_H
+#error You must include hardware.h not this file
+#endif /* __ASM_ARCH_HARDWARE_H */
+/* Interrupt controller */
+#define IRQ_BASE        __REG(0x80000500)
+#define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
+#define IRQ_INTRSR      __REG(0x80000504)       /* Int Raw (unmasked) Status */
+#define IRQ_INTENS      __REG(0x80000508)       /* Int Enable Set */
+#define IRQ_INTENC      __REG(0x8000050c)       /* Int Enable Clear */
+/* UART 1 */
+#define UART1_BASE      __REG(0x80000600)
+#define UART1_DR        __REG(0x80000600) /* Data/FIFO Register */
+#define UART1_LCR       __REG(0x80000604) /* Link Control Register */
+#define UART1_BRCR      __REG(0x80000608) /* Baud Rate Control Register */
+#define UART1_CR        __REG(0x8000060c) /* Control Register */
+#define UART1_SR        __REG(0x80000610) /* Status Register */
+#define UART1_INT       __REG(0x80000614) /* Interrupt Status Register */
+#define UART1_INTM      __REG(0x80000618) /* Interrupt Mask Register */
+#define UART1_INTRES    __REG(0x8000061c) /* Int Result (masked status) Register */
+/* UART 2 */
+#define UART2_BASE      __REG(0x80000700)
+#define UART2_DR        __REG(0x80000700) /* Data/FIFO Register */
+#define UART2_LCR       __REG(0x80000704) /* Link Control Register */
+#define UART2_BRCR      __REG(0x80000708) /* Baud Rate Control Register */
+#define UART2_CR        __REG(0x8000070c) /* Control Register */
+#define UART2_SR        __REG(0x80000710) /* Status Register */
+#define UART2_INT       __REG(0x80000714) /* Interrupt Status Register */
+#define UART2_INTM      __REG(0x80000718) /* Interrupt Mask Register */
+#define UART2_INTRES    __REG(0x8000071c) /* Int Result (masked status) Register */
+/* UART 3 */
+#define UART3_BASE      __REG(0x80000800)
+#define UART3_DR        __REG(0x80000800) /* Data/FIFO Register */
+#define UART3_LCR       __REG(0x80000804) /* Link Control Register */
+#define UART3_BRCR      __REG(0x80000808) /* Baud Rate Control Register */
+#define UART3_CR        __REG(0x8000080c) /* Control Register */
+#define UART3_SR        __REG(0x80000810) /* Status Register */
+#define UART3_INT       __REG(0x80000814) /* Interrupt Status Register */
+#define UART3_INTM      __REG(0x80000818) /* Interrupt Mask Register */
+#define UART3_INTRES    __REG(0x8000081c) /* Int Result (masked status) Register */
+/* These are used in some places */
+#define _UART1_BASE __PREG(UART1_BASE)
+#define _UART2_BASE __PREG(UART2_BASE)
+#define _UART3_BASE __PREG(UART3_BASE)
+/* UART Registers Offsets */
+#define UART_DR         0x00
+#define UART_LCR        0x04
+#define UART_BRCR       0x08
+#define UART_CR         0x0c
+#define UART_SR         0x10
+#define UART_INT        0x14
+#define UART_INTM       0x18
+#define UART_INTRES     0x1c
+/* UART_LCR Bitmask */
+#define UART_LCR_BRK    (1 << 0) /* Send Break */
+#define UART_LCR_PEN    (1 << 1) /* Parity Enable */
+#define UART_LCR_EP     (1 << 2) /* Even/Odd Parity */
+#define UART_LCR_S2     (1 << 3) /* One/Two Stop bits */
+#define UART_LCR_FIFO   (1 << 4) /* FIFO Enable */
+#define UART_LCR_WL5    (0 << 5) /* Word Length - 5 bits */
+#define UART_LCR_WL6    (1 << 5) /* Word Length - 6 bits */
+#define UART_LCR_WL7    (1 << 6) /* Word Length - 7 bits */
+#define UART_LCR_WL8    (1 << 7) /* Word Length - 8 bits */
+/* UART_CR Bitmask */
+#define UART_CR_EN      (1 << 0) /* UART Enable */
+#define UART_CR_SIR     (1 << 1) /* IrDA SIR Enable */
+#define UART_CR_SIRLP   (1 << 2) /* Low Power IrDA Enable */
+#define UART_CR_RXP     (1 << 3) /* Receive Pin Polarity */
+#define UART_CR_TXP     (1 << 4) /* Transmit Pin Polarity */
+#define UART_CR_MXP     (1 << 5) /* Modem Pin Polarity */
+#define UART_CR_LOOP    (1 << 6) /* Loopback Mode */
+/* UART_SR Bitmask */
+#define UART_SR_CTS     (1 << 0) /* Clear To Send Status */
+#define UART_SR_DSR     (1 << 1) /* Data Set Ready Status */
+#define UART_SR_DCD     (1 << 2) /* Data Carrier Detect Status */
+#define UART_SR_TxBSY   (1 << 3) /* Transmitter Busy Status */
+#define UART_SR_RxFE    (1 << 4) /* Receive FIFO Empty Status */
+#define UART_SR_TxFF    (1 << 5) /* Transmit FIFO Full Status */
+#define UART_SR_RxFF    (1 << 6) /* Receive FIFO Full Status */
+#define UART_SR_TxFE    (1 << 7) /* Transmit FIFO Empty Status */
+/* UART_INT Bitmask */
+#define UART_INT_RIS    (1 << 0) /* Rx Interrupt */
+#define UART_INT_TIS    (1 << 1) /* Tx Interrupt */
+#define UART_INT_MIS    (1 << 2) /* Modem Interrupt */
+#define UART_INT_RTIS   (1 << 3) /* Receive Timeout Interrupt */
+/* Timer 1 */
+#define TIMER1_BASE     __REG(0x80000c00)
+#define TIMER1_LOAD     __REG(0x80000c00)       /* Timer 1 Load Register */
+#define TIMER1_VAL      __REG(0x80000c04)       /* Timer 1 Value Register */
+#define TIMER1_CTRL     __REG(0x80000c08)       /* Timer 1 Control Register */
+#define TIMER1_CLEAR    __REG(0x80000c0c)       /* Timer 1 Clear Register */
+/* Timer 2 */
+#define TIMER2_BASE     __REG(0x80000d00)
+#define TIMER2_LOAD     __REG(0x80000d00)       /* Timer 2 Load Register */
+#define TIMER2_VAL      __REG(0x80000d04)       /* Timer 2 Value Register */
+#define TIMER2_CTRL     __REG(0x80000d08)       /* Timer 2 Control Register */
+#define TIMER2_CLEAR    __REG(0x80000d0c)       /* Timer 2 Clear Register */
+/* Timer 3 */
+#define TIMER3_BASE     __REG(0x80000e00)
+#define TIMER3_LOAD     __REG(0x80000e00)       /* Timer 3 Load Register */
+#define TIMER3_VAL      __REG(0x80000e04)       /* Timer 3 Value Register */
+#define TIMER3_CTRL     __REG(0x80000e08)       /* Timer 3 Control Register */
+#define TIMER3_CLEAR    __REG(0x80000e0c)       /* Timer 3 Clear Register */
+/* Timer Control register bits */
+#define TIMER_CTRL_ENABLE       (1 << 7) /* Enable (Start° Timer */
+#define TIMER_CTRL_PERIODIC     (1 << 6) /* Periodic Running Mode */
+#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
+#define TIMER_CTRL_CLKSEL_508K  (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
+#define TIMER_CTRL_CLKSEL_2K    (0 << 3) /* 2KHz Clock Select (Timer 1, 2)*/
+/* Power and State Control */
+#define POWER_BASE      __REG(0x80000400)
+#define POWER_PWRSR     __REG(0x80000400) /* Power Status Register */
+#define POWER_PWRCNT    __REG(0x80000404) /* Power/Clock control */
+#define POWER_HALT      __REG(0x80000408) /* Power Idle Mode */
+#define POWER_STDBY     __REG(0x8000040c) /* Power Standby Mode */
+#define POWER_BLEOI     __REG(0x80000410) /* Battery Low End of Interrupt */
+#define POWER_MCEOI     __REG(0x80000414) /* Media Changed EoI */
+#define POWER_TEOI      __REG(0x80000418) /* Tick EoI */
+#define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
+#define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
+#endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/include/asm-arm/arch-aaec2000/debug-macro.S b/include/asm-arm/arch-aaec2000/debug-macro.S
new file mode 100644
index 000000000000..e4f1fa539a74
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/debug-macro.S
@@ -0,0 +1,36 @@
+/*  linux/include/asm-arm/arch-aaec2000/debug-macro.S
+ *
+ *  Debugging macro include header
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x80000000                @ physical
+                movne   \rx, #io_p2v(0x80000000)        @ virtual
+                orr     \rx, \rx, #0x00000800
+                .endm
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0]
+                .endm
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x10]
+                tst     \rd, #(1 << 7)
+                beq     1002b
+                .endm
+                .macro  waituart,rd,rx
+#if 0
+1001:           ldr     \rd, [\rx, #0x10]
+                tst     \rd, #(1 << 5)
+                beq     1001b
+#endif
+                .endm
diff --git a/include/asm-arm/arch-aaec2000/dma.h b/include/asm-arm/arch-aaec2000/dma.h
new file mode 100644
index 000000000000..28c890b4a1d3
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/dma.h
@@ -0,0 +1,17 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/dma.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0
+#endif
diff --git a/include/asm-arm/arch-aaec2000/entry-macro.S b/include/asm-arm/arch-aaec2000/entry-macro.S
new file mode 100644
index 000000000000..df31313ab07e
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/entry-macro.S
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/entry-macro.S
+ *
+ *  Low-level IRQ helper for aaec-2000 based platforms
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #0xf8000000
+                add     r4, r4, #0x00000500
+                mov     \base, r4
+                ldr     \irqstat, [\base, #0]
+                cmp     \irqstat, #0
+                bne     1001f
+                ldr     \irqnr, =NR_IRQS+1
+                b       1003f
+1001:           mov     \irqnr, #0
+1002:           ands    \tmp, \irqstat, #1
+                mov     \irqstat, \irqstat, LSR #1
+                add     \irqnr, \irqnr, #1
+                beq     1002b
+                sub     \irqnr, \irqnr, #1
+1003:
+                .endm
diff --git a/include/asm-arm/arch-aaec2000/hardware.h b/include/asm-arm/arch-aaec2000/hardware.h
new file mode 100644
index 000000000000..4c37219e030e
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/hardware.h
@@ -0,0 +1,49 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/hardware.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <linux/config.h>
+/* The kernel is loaded at physical address 0xf8000000.
+ * We map the IO space a bit after
+ */
+#define PIO_APB_BASE    0x80000000
+#define VIO_APB_BASE    0xf8000000
+#define IO_APB_LENGTH   0x2000
+#define PIO_AHB_BASE    0x80002000
+#define VIO_AHB_BASE    0xf8002000
+#define IO_AHB_LENGTH   0x2000
+#define VIO_BASE    VIO_APB_BASE
+#define PIO_BASE    PIO_APB_BASE
+#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE )
+#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE )
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+/* FIXME: Is it needed to optimize this a la pxa ?? */
+#define __REG(x)    (*((volatile u32 *)io_p2v(x)))
+#define __PREG(x)   (io_v2p((u32)&(x)))
+#else /* __ASSEMBLY__ */
+#define __REG(x)    io_p2v(x)
+#define __PREG(x)   io_v2p(x)
+#endif
+#include "aaec2000.h"
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
new file mode 100644
index 000000000000..c58a8d10425a
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/io.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/io.h
+ *
+ *  Copied from asm/arch/sa1100/io.h
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-aaec2000/irqs.h b/include/asm-arm/arch-aaec2000/irqs.h
new file mode 100644
index 000000000000..de252220e806
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/irqs.h
@@ -0,0 +1,46 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/irqs.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#define INT_GPIOF0_FIQ  0  /* External GPIO Port F O Fast Interrupt Input */
+#define INT_BL_FIQ      1  /* Battery Low Fast Interrupt */
+#define INT_WE_FIQ      2  /* Watchdog Expired Fast Interrupt */
+#define INT_MV_FIQ      3  /* Media Changed Interrupt */
+#define INT_SC          4  /* Sound Codec Interrupt */
+#define INT_GPIO1       5  /* GPIO Port F Configurable Int 1 */
+#define INT_GPIO2       6  /* GPIO Port F Configurable Int 2 */
+#define INT_GPIO3       7  /* GPIO Port F Configurable Int 3 */
+#define INT_TMR1_OFL    8  /* Timer 1 Overflow Interrupt */
+#define INT_TMR2_OFL    9  /* Timer 2 Overflow Interrupt */
+#define INT_RTC_CM      10 /* RTC Compare Match Interrupt */
+#define INT_TICK        11 /* 64Hz Tick Interrupt */
+#define INT_UART1       12 /* UART1 Interrupt */
+#define INT_UART2       13 /* UART2 & Modem State Changed Interrupt */
+#define INT_LCD         14 /* LCD Interrupt */
+#define INT_SSI         15 /* SSI End of Transfer Interrupt */
+#define INT_UART3       16 /* UART3 Interrupt */
+#define INT_SCI         17 /* SCI Interrupt */
+#define INT_AAC         18 /* Advanced Audio Codec Interrupt */
+#define INT_MMC         19 /* MMC Interrupt */
+#define INT_USB         20 /* USB Interrupt */
+#define INT_DMA         21 /* DMA Interrupt */
+#define INT_TMR3_UOFL   22 /* Timer 3 Underflow Interrupt */
+#define INT_GPIO4       23 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO5       24 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO6       25 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO7       26 /* GPIO Port F Configurable Int 4 */
+#define INT_BMI         27 /* BMI Interrupt */
+#define NR_IRQS         (INT_BMI + 1)
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
new file mode 100644
index 000000000000..681b6a6171a1
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -0,0 +1,73 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/memory.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#include <linux/config.h>
+#define PHYS_OFFSET     (0xf0000000UL)
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * The nodes are the followings:
+ *
+ *   node 0: 0xf000.0000 - 0xf3ff.ffff
+ *   node 1: 0xf400.0000 - 0xf7ff.ffff
+ *   node 2: 0xf800.0000 - 0xfbff.ffff
+ *   node 3: 0xfc00.0000 - 0xffff.ffff
+ */
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn) \
+        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+/*
+ *  Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ *  and returns the index corresponding to the appropriate page in the
+ *  node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
+#define NODE_MAX_MEM_SHIFT      26
+#define NODE_MAX_MEM_SIZE       (1 << NODE_MAX_MEM_SHIFT)
+#else
+#define PFN_TO_NID(addr)        (0)
+#endif /* CONFIG_DISCONTIGMEM */
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-aaec2000/param.h b/include/asm-arm/arch-aaec2000/param.h
new file mode 100644
index 000000000000..139936c2faf2
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/param.h
@@ -0,0 +1,15 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/param.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+#endif /* __ASM_ARCH_PARAM_H */
diff --git a/include/asm-arm/arch-aaec2000/system.h b/include/asm-arm/arch-aaec2000/system.h
new file mode 100644
index 000000000000..08de97b407a8
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/system.h
@@ -0,0 +1,24 @@
+/*
+ *  linux/include/asm-arm/arch-aaed2000/system.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/include/asm-arm/arch-aaec2000/timex.h b/include/asm-arm/arch-aaec2000/timex.h
new file mode 100644
index 000000000000..f5708b38fb7f
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/timex.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/timex.h
+ *
+ *  AAEC-2000 Architecture timex specification
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+#define CLOCK_TICK_RATE         508000
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-aaec2000/uncompress.h b/include/asm-arm/arch-aaec2000/uncompress.h
new file mode 100644
index 000000000000..fff0c94b75c4
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/uncompress.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+#include "hardware.h"
+#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
+static void putstr( const char *s )
+{
+        unsigned long serial_port;
+        do {
+                serial_port = _UART3_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                serial_port = _UART1_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                serial_port = _UART2_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                return;
+        } while (0);
+        for (; *s; s++) {
+                /* wait for space in the UART's transmitter */
+                while ((UART(UART_SR) & UART_SR_TxFF));
+                /* send the character out. */
+                UART(UART_DR) = *s;
+                /* if a LF, also do CR... */
+                if (*s == 10) {
+                        while ((UART(UART_SR) & UART_SR_TxFF));
+                        UART(UART_DR) = 13;
+                }
+        }
+}
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-aaec2000/vmalloc.h b/include/asm-arm/arch-aaec2000/vmalloc.h
new file mode 100644
index 000000000000..ecb991e2e4ff
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/vmalloc.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+#define VMALLOC_END             (PAGE_OFFSET + 0x10000000)
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h
index 2346d454ab9c..7dbc7bbba65d 100644
--- a/include/asm-arm/arch-imx/imxfb.h
+++ b/include/asm-arm/arch-imx/imxfb.h
@@ -25,6 +25,7 @@ struct imxfb_mach_info {
        u_int           pcr;
        u_int           pwmr;
        u_int           lscr1;
+        u_int           dmacr;
        u_char * fixed_screen_cpu;
        dma_addr_t fixed_screen_dma;
diff --git a/include/asm-arm/arch-integrator/platform.h b/include/asm-arm/arch-integrator/platform.h
index bd364f5a99bc..96ad3d2a66d1 100644
--- a/include/asm-arm/arch-integrator/platform.h
+++ b/include/asm-arm/arch-integrator/platform.h
@@ -293,7 +293,11 @@
 #define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
+#if defined(CONFIG_ARCH_INTEGRATOR_AP)
 #define INTEGRATOR_GPIO_BASE            0x1B000000       /*  GPIO */
+#elif defined(CONFIG_ARCH_INTEGRATOR_CP)
+#define INTEGRATOR_GPIO_BASE            0xC9000000       /*  GPIO */
+#endif
 /* ------------------------------------------------------------------------
 *  KMI keyboard/mouse definitions
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
new file mode 100644
index 000000000000..0ec7093f7c37
--- /dev/null
+++ b/include/asm-arm/arch-integrator/smp.h
@@ -0,0 +1,19 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+#include <linux/config.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#define hard_smp_processor_id()                         \
+        ({                                              \
+                unsigned int cpunum;                    \
+                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
+                        : "=r" (cpunum));               \
+                cpunum &= 0x0F;                         \
+        })
+extern void secondary_scan_irqs(void);
+#endif
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h
index 84634af5cc64..03cbbe1fd9d8 100644
--- a/include/asm-arm/arch-ixp2000/gpio.h
+++ b/include/asm-arm/arch-ixp2000/gpio.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-ixp2000/ixp2000-gpio.h
+ * include/asm-arm/arch-ixp2000/gpio.h
 *
 * Copyright (C) 2002 Intel Corporation.
 *
@@ -16,26 +16,18 @@
 * Use this instead of directly setting the GPIO registers.
 * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
 */
-#ifndef _ASM_ARCH_IXP2000_GPIO_H_
+#ifndef __ASM_ARCH_GPIO_H
-#define _ASM_ARCH_IXP2000_GPIO_H_
+#define __ASM_ARCH_GPIO_H
 #ifndef __ASSEMBLY__
-#define GPIO_OUT                        0x0
-#define GPIO_IN                         0x80
+#define GPIO_IN                         0
+#define GPIO_OUT                        1
 #define IXP2000_GPIO_LOW                0
 #define IXP2000_GPIO_HIGH               1
-#define GPIO_NO_EDGES                   0
+extern void gpio_line_config(int line, int direction);
-#define GPIO_FALLING_EDGE               1
-#define GPIO_RISING_EDGE                2
-#define GPIO_BOTH_EDGES                 3
-#define GPIO_LEVEL_LOW                  4
-#define GPIO_LEVEL_HIGH                 8
-extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
-extern void set_GPIO_IRQ_level(int gpio_nr, int level);
-extern void gpio_line_config(int line, int style);
 static inline int gpio_line_get(int line)
 {
@@ -45,11 +37,12 @@ static inline int gpio_line_get(int line)
 static inline void gpio_line_set(int line, int value)
 {
        if (value == IXP2000_GPIO_HIGH) {
-                ixp_reg_write(IXP2000_GPIO_POSR, BIT(line));
+                ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
-        } else if (value == IXP2000_GPIO_LOW)
+        } else if (value == IXP2000_GPIO_LOW) {
-                ixp_reg_write(IXP2000_GPIO_POCR, BIT(line));
+                ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
+        }
 }
 #endif /* !__ASSEMBLY__ */
-#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
+#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 083462668e18..3241cd6f0778 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -17,18 +17,23 @@
 #define IO_SPACE_LIMIT          0xffffffff
 #define __mem_pci(a)            (a)
-#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
 /*
- * The IXP2400 before revision B0 asserts byte lanes for PCI I/O
+ * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
 * transactions the other way round (MEM transactions don't have this
- * issue), so we need to override the standard functions.  B0 and later
+ * issue), so if we want to support those models, we need to override
- * have a bit that can be set to 1 to get the 'proper' behavior, but
+ * the standard I/O functions.
- * since that isn't available on the A? revisions we just keep doing
+ *
- * things manually.
+ * B0 and later have a bit that can be set to 1 to get the proper
+ * behavior for I/O transactions, which then allows us to use the
+ * standard I/O functions.  This is what we do if the user does not
+ * explicitly ask for support for pre-B0.
 */
-#define alignb(addr)            (void __iomem *)((unsigned long)addr ^ 3)
+#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
-#define alignw(addr)            (void __iomem *)((unsigned long)addr ^ 2)
+#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#define alignb(addr)            (void __iomem *)((unsigned long)(addr) ^ 3)
+#define alignw(addr)            (void __iomem *)((unsigned long)(addr) ^ 2)
 #define outb(v,p)               __raw_writeb((v),alignb(___io(p)))
 #define outw(v,p)               __raw_writew((v),alignw(___io(p)))
@@ -48,6 +53,81 @@
 #define insw(p,d,l)             __raw_readsw(alignw(___io(p)),d,l)
 #define insl(p,d,l)             __raw_readsl(___io(p),d,l)
+#define __is_io_address(p)      ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
+#define ioread8(p)                                              \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readb(alignb(p));           \
+                } else {                                        \
+                        __v = __raw_readb(p);                   \
+                }                                               \
+                                                                \
+                __v;                                            \
+        })                                                      \
+#define ioread16(p)                                             \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readw(alignw(p));           \
+                } else {                                        \
+                        __v = le16_to_cpu(__raw_readw(p));      \
+                }                                               \
+                                                                \
+                __v;                                            \
+        })
+#define ioread32(p)                                             \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readl(p);                   \
+                } else {                                        \
+                        __v = le32_to_cpu(__raw_readl(p));      \
+                }                                               \
+                                                                \
+                 __v;                                           \
+        })
+#define iowrite8(v,p)                                           \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writeb((v), alignb(p));           \
+                } else {                                        \
+                        __raw_writeb((v), p);                   \
+                }                                               \
+        })
+#define iowrite16(v,p)                                          \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writew((v), alignw(p));           \
+                } else {                                        \
+                        __raw_writew(cpu_to_le16(v), p);        \
+                }                                               \
+        })
+#define iowrite32(v,p)                                          \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writel((v), p);                   \
+                } else {                                        \
+                        __raw_writel(cpu_to_le32(v), p);        \
+                }                                               \
+        })
+#define ioport_map(port, nr)    ___io(port)
+#define ioport_unmap(addr)
+#else
+#define __io(p)                 ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#endif
 #ifdef CONFIG_ARCH_IXDP2X01
 /*
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h
index 3a398dfbf125..229381c64283 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x00.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h
@@ -21,8 +21,8 @@
 * On board CPLD memory map
 */
 #define IXDP2X00_PHYS_CPLD_BASE         0xc7000000
-#define IXDP2X00_VIRT_CPLD_BASE         0xfafff000
+#define IXDP2X00_VIRT_CPLD_BASE         0xfe000000
-#define IXDP2X00_CPLD_SIZE              0x00001000
+#define IXDP2X00_CPLD_SIZE              0x00100000
 #define IXDP2X00_CPLD_REG(x)    \
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b3a1bcda8d01..b768009c3a51 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -18,8 +18,8 @@
 #define __IXDP2X01_H__
 #define IXDP2X01_PHYS_CPLD_BASE         0xc6024000
-#define IXDP2X01_VIRT_CPLD_BASE         0xfafff000
+#define IXDP2X01_VIRT_CPLD_BASE         0xfe000000
-#define IXDP2X01_CPLD_REGION_SIZE       0x00001000
+#define IXDP2X01_CPLD_REGION_SIZE       0x00100000
 #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
 #define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 6c56708d0ff0..75623f81ef75 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -18,6 +18,21 @@
 #ifndef _IXP2000_REGS_H_
 #define _IXP2000_REGS_H_
+/*
+ * IXP2000 linux memory map:
+ *
+ * virt         phys            size
+ * fb000000     db000000        16M             PCI CFG1
+ * fc000000     da000000        16M             PCI CFG0
+ * fd000000     d8000000        16M             PCI I/O
+ * fe[0-7]00000                 8M              per-platform mappings
+ * feb00000     c8000000        1M              MSF
+ * fec00000     df000000        1M              PCI CSRs
+ * fed00000     de000000        1M              PCI CREG
+ * fee00000     d6000000        1M              INTCTL
+ * fef00000     c0000000        1M              CAP
+ */
 /* 
 * Static I/O regions.
 *
@@ -71,6 +86,10 @@
 #define IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
 #define IXP2000_PCI_CSR_SIZE            0x00100000
+#define IXP2000_MSF_PHYS_BASE           0xc8000000
+#define IXP2000_MSF_VIRT_BASE           0xfeb00000
+#define IXP2000_MSF_SIZE                0x00100000
 #define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
 #define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
 #define IXP2000_PCI_IO_SIZE             0x01000000
@@ -241,7 +260,7 @@
 #define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
 #define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
 #define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
-#define PCI_CONTROL_PNR                 (1 << 17)       /* PCI Not Reset bit */
+#define PCI_CONTROL_IEE                 (1 << 17)       /* I/O cycle Endian swap Enable */
 #define IXP2000_PCI_RST_REL             (1 << 2)
 #define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
@@ -363,6 +382,7 @@
 #define IXP2000_MIN_REV_MASK            0x0000000F
 #define IXP2000_PROD_ID_MASK            0xFFFFFFFF
+#define IXP2000_PRODUCT_ID              GLOBAL_REG(0x00)
 #define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
 #define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
 #define IXP2000_RESET0                  GLOBAL_REG(0x0c)
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index 901bba6d02b4..c0caf3e3e6fd 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -115,6 +115,7 @@ static inline unsigned int ixp2000_is_pcimaster(void)
 }
 void ixp2000_map_io(void);
+void ixp2000_uart_init(void);
 void ixp2000_init_irq(void);
 void ixp2000_init_time(unsigned long);
 unsigned long ixp2000_gettimeoffset(void);
@@ -138,30 +139,10 @@ struct ixp2000_flash_data {
        unsigned long (*bank_setup)(unsigned long);
 };
-/*
- * GPIO helper functions
- */
-#define GPIO_IN         0
-#define GPIO_OUT        1
-extern void gpio_line_config(int line, int style);
-static inline int gpio_line_get(int line)
-{
-        return (((*IXP2000_GPIO_PLR) >> line) & 1);
-}
-static inline void gpio_line_set(int line, int value)
-{
-        if (value) 
-                ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
-        else 
-                ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
-}
 struct ixp2000_i2c_pins {
        unsigned long sda_pin;
        unsigned long scl_pin;
 };
 #endif /*  !__ASSEMBLY__ */
diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h
index 473dff4ec561..275136963a0c 100644
--- a/include/asm-arm/arch-ixp2000/vmalloc.h
+++ b/include/asm-arm/arch-ixp2000/vmalloc.h
@@ -17,4 +17,4 @@
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
 */
-#define VMALLOC_END         0xfaffefff
+#define VMALLOC_END         0xfb000000
diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S
index 4499ae8e4b44..2e23651e217f 100644
--- a/include/asm-arm/arch-ixp4xx/debug-macro.S
+++ b/include/asm-arm/arch-ixp4xx/debug-macro.S
@@ -15,6 +15,7 @@
                tst     \rx, #1                 @ MMU enabled?
                moveq   \rx, #0xc8000000
                movne   \rx, #0xff000000
+                orrne   \rx, \rx, #0x00b00000
                add     \rx,\rx,#3              @ Uart regs are at off set of 3 if
                                                @ byte writes used - Big Endian.
                .endm
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index c27b9d3079a7..e350dcb544e8 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -3,7 +3,7 @@
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 *
- * Copyright (C) 2002-2004  MontaVista Software, Inc.
+ * Copyright (C) 2002-2005  MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -383,6 +383,198 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
                *vaddr++ = inl(io_addr);
 }
+#define PIO_OFFSET      0x10000UL
+#define PIO_MASK        0x0ffffUL
+#define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
+                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
+static inline unsigned int
+__ixp4xx_ioread8(void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return (unsigned int)__raw_readb(port);
+#else
+                return (unsigned int)__ixp4xx_readb(port);
+#endif
+}
+static inline void
+__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insb(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsb(addr, vaddr, count);
+#else
+                __ixp4xx_readsb(port, vaddr, count);
+#endif
+}
+static inline unsigned int
+__ixp4xx_ioread16(void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return le16_to_cpu(__raw_readw((u32)port));
+#else
+                return (unsigned int)__ixp4xx_readw((u32)port);
+#endif
+}
+static inline void
+__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insw(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsw(addr, vaddr, count);
+#else
+                __ixp4xx_readsw(port, vaddr, count);
+#endif
+}
+static inline unsigned int
+__ixp4xx_ioread32(void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
+        else {
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return le32_to_cpu(__raw_readl((u32)port));
+#else
+                return (unsigned int)__ixp4xx_readl((u32)port);
+#endif
+        }
+}
+static inline void
+__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insl(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsl(addr, vaddr, count);
+#else
+                __ixp4xx_readsl(port, vaddr, count);
+#endif
+}
+static inline void
+__ixp4xx_iowrite8(u8 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outb(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writeb(value, port);
+#else
+                __ixp4xx_writeb(value, port);
+#endif
+}
+static inline void
+__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesb(addr, vaddr, count);
+#else
+                __ixp4xx_writesb(port, vaddr, count);
+#endif
+}
+static inline void
+__ixp4xx_iowrite16(u16 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outw(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writew(cpu_to_le16(value), addr);
+#else
+                __ixp4xx_writew(value, port);
+#endif
+}
+static inline void
+__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesw(addr, vaddr, count);
+#else
+                __ixp4xx_writesw(port, vaddr, count);
+#endif
+}
+static inline void
+__ixp4xx_iowrite32(u32 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outl(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writel(cpu_to_le32(value), port);
+#else
+                __ixp4xx_writel(value, port);
+#endif
+}
+static inline void
+__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesl(addr, vaddr, count);
+#else
+                __ixp4xx_writesl(port, vaddr, count);
+#endif
+}
+#define ioread8(p)                      __ixp4xx_ioread8(p)
+#define ioread16(p)                     __ixp4xx_ioread16(p)
+#define ioread32(p)                     __ixp4xx_ioread32(p)
+#define ioread8_rep(p, v, c)            __ixp4xx_ioread8_rep(p, v, c)
+#define ioread16_rep(p, v, c)           __ixp4xx_ioread16_rep(p, v, c)
+#define ioread32_rep(p, v, c)           __ixp4xx_ioread32_rep(p, v, c)
+#define iowrite8(v,p)                   __ixp4xx_iowrite8(v,p)
+#define iowrite16(v,p)                  __ixp4xx_iowrite16(v,p)
+#define iowrite32(v,p)                  __ixp4xx_iowrite32(v,p)
+#define iowrite8_rep(p, v, c)           __ixp4xx_iowrite8_rep(p, v, c)
+#define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
+#define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
+#define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
+#define ioport_unmap(addr)
 #endif  //  __ASM_ARM_ARCH_IO_H
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 8eeb1db6309d..004696a95bdb 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -69,6 +69,16 @@
 #define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBF2000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE   (0x0000C000)
+/*
+ * Debug UART
+ *
+ * This is basically a remap of UART1 into a region that is section
+ * aligned so that it * can be used with the low-level debug code.
+ */
+#define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
+#define IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
+#define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
 #define IXP4XX_EXP_CS0_OFFSET   0x00
 #define IXP4XX_EXP_CS1_OFFSET   0x04
 #define IXP4XX_EXP_CS2_OFFSET   0x08
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 3a626c03ea26..d13ee7f78c70 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -83,17 +83,6 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 #define IXP4XX_GPIO_OUT                 0x1
 #define IXP4XX_GPIO_IN                  0x2
-#define IXP4XX_GPIO_INTSTYLE_MASK       0x7C  /* Bits [6:2] define interrupt style */
-/* 
- * GPIO interrupt types.
- */
-#define IXP4XX_GPIO_ACTIVE_HIGH         0x4 /* Default */
-#define IXP4XX_GPIO_ACTIVE_LOW          0x8
-#define IXP4XX_GPIO_RISING_EDGE         0x10
-#define IXP4XX_GPIO_FALLING_EDGE        0x20
-#define IXP4XX_GPIO_TRANSITIONAL        0x40
 /* GPIO signal types */
 #define IXP4XX_GPIO_LOW                 0
 #define IXP4XX_GPIO_HIGH                1
@@ -102,7 +91,13 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 #define IXP4XX_GPIO_CLK_0               14
 #define IXP4XX_GPIO_CLK_1               15
-extern void gpio_line_config(u8 line, u32 style);
+static inline void gpio_line_config(u8 line, u32 direction)
+{
+        if (direction == IXP4XX_GPIO_OUT)
+                *IXP4XX_GPIO_GPOER |= (1 << line);
+        else
+                *IXP4XX_GPIO_GPOER &= ~(1 << line);
+}
 static inline void gpio_line_get(u8 line, int *value)
 {
diff --git a/include/asm-arm/arch-ixp4xx/timex.h b/include/asm-arm/arch-ixp4xx/timex.h
index 38c9d77d3727..3745e35cc030 100644
--- a/include/asm-arm/arch-ixp4xx/timex.h
+++ b/include/asm-arm/arch-ixp4xx/timex.h
@@ -7,7 +7,9 @@
 /*
 * We use IXP425 General purpose timer for our timer needs, it runs at 
- * 66.66... MHz
+ * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
+ * timer register ignores the bottom 2 bits of the LATCH value.
 */
-#define CLOCK_TICK_RATE (66666666)
+#define FREQ 66666666
+#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
index 60f002b72983..39ca5a31aeea 100644
--- a/include/asm-arm/arch-omap/board-h2.h
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -34,11 +34,6 @@
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE             SZ_32M
-#define OMAP_NOR_FLASH_START1           0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2           0x0A000000 /* CS2B */
 /* Samsung NAND flash at CS2B or CS3(NAND Boot) */
 #define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
 #define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index e4d1cd231731..1b12c1dcc2fa 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,11 +30,6 @@
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
 #define OMAP1710_ETHR_START             0x04000300
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE             SZ_32M
-#define OMAP_NOR_FLASH_START1           0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2           0x0A000000 /* CS2B */
 /* Samsung NAND flash at CS2B or CS3(NAND Boot) */
 #define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
 #define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
index 79138dcfb4ac..d64ee9211eed 100644
--- a/include/asm-arm/arch-omap/board-h4.h
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -30,6 +30,9 @@
 #define __ASM_ARCH_OMAP_H4_H
 /* Placeholder for H4 specific defines */
+/* GPMC CS1 */
+#define OMAP24XX_ETHR_START             0x08000300
+#define OMAP24XX_ETHR_GPIO_IRQ          92
 #endif /*  __ASM_ARCH_OMAP_H4_H */
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 0f1abaefe4de..79574e0ed13d 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,31 +36,6 @@
 #define OMAP1510P1_EMIFS_PRI_VALUE              0x00
 #define OMAP1510P1_EMIFF_PRI_VALUE              0x00
-/*
- * These definitions define an area of FLASH set aside
- * for the use of MTD/JFFS2. This is the area of flash
- * that a JFFS2 filesystem will reside which is mounted
- * at boot with the "root=/dev/mtdblock/0 rw"
- * command line option. The flash address used here must
- * fall within the legal range defined by rrload for storing
- * the filesystem component. This address will be sufficiently
- * deep into the overall flash range to avoid the other
- * components also stored in flash such as the bootloader,
- * the bootloader params, and the kernel.
- * The SW2 settings for the map below are:
- * 1 off, 2 off, 3 on, 4 off.
- */
-/* Intel flash_0, partitioned as expected by rrload */
-#define OMAP_FLASH_0_BASE       0xD8000000
-#define OMAP_FLASH_0_START      0x00000000
-#define OMAP_FLASH_0_SIZE       SZ_16M
-/* Intel flash_1, used for cramfs or other flash file systems */
-#define OMAP_FLASH_1_BASE       0xD9000000
-#define OMAP_FLASH_1_START      0x01000000
-#define OMAP_FLASH_1_SIZE       SZ_16M
 #define NR_FPGA_IRQS            24
 #define NR_IRQS                 IH_BOARD_BASE + NR_FPGA_IRQS
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
index aaa49a0fbd21..2b1a8a4fe44e 100644
--- a/include/asm-arm/arch-omap/board-osk.h
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -32,10 +32,5 @@
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
 #define OMAP_OSK_ETHR_START             0x04800300
-/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
-#define OMAP_OSK_NOR_FLASH_BASE         0xD8000000
-#define OMAP_OSK_NOR_FLASH_SIZE         SZ_32M
-#define OMAP_OSK_NOR_FLASH_START        0x00000000
 #endif /*  __ASM_ARCH_OMAP_OSK_H */
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index 0c224cc74fe4..691e52a52b43 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,23 +36,14 @@
 #define OMAP_SDRAM_DEVICE               D256M_1X16_4B
 #endif
-/*
- * These definitions define an area of FLASH set aside
- * for the use of MTD/JFFS2. This is the area of flash
- * that a JFFS2 filesystem will reside which is mounted
- * at boot with the "root=/dev/mtdblock/0 rw"
- * command line option.
- */
-/* Intel flash_0, partitioned as expected by rrload */
-#define OMAP_FLASH_0_BASE       0xD8000000      /* VA */
-#define OMAP_FLASH_0_START      0x00000000      /* PA */
-#define OMAP_FLASH_0_SIZE       SZ_32M
 #define MAXIRQNUM               IH_BOARD_BASE
 #define MAXFIQNUM               MAXIRQNUM
 #define MAXSWINUM               MAXIRQNUM
 #define NR_IRQS                 (MAXIRQNUM + 1)
+/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
+#define OMAP_NAND_FLASH_START1     0x0A000000 /* CS2B */
+#define OMAP_NAND_FLASH_START2     0x0C000000 /* CS3 */
 #endif
diff --git a/include/asm-arm/arch-omap/board-voiceblue.h b/include/asm-arm/arch-omap/board-voiceblue.h
index 33977b8956fb..ed6d346ee123 100644
--- a/include/asm-arm/arch-omap/board-voiceblue.h
+++ b/include/asm-arm/arch-omap/board-voiceblue.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_VOICEBLUE_H
 #define __ASM_ARCH_VOICEBLUE_H
-#if (EXTERNAL_MAX_NR_PORTS < 4)
-#undef EXTERNAL_MAX_NR_PORTS
-#define EXTERNAL_MAX_NR_PORTS   4
-#endif
 extern void voiceblue_wdt_enable(void);
 extern void voiceblue_wdt_disable(void);
 extern void voiceblue_wdt_ping(void);
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index 1cefd60b6f2a..a0040cd86639 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -16,10 +16,11 @@
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
 #define OMAP_TAG_MMC            0x4f02
-#define OMAP_TAG_UART           0x4f03
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 #define OMAP_TAG_USB            0x4f04
 #define OMAP_TAG_LCD            0x4f05
 #define OMAP_TAG_GPIO_SWITCH    0x4f06
+#define OMAP_TAG_UART           0x4f07
 #define OMAP_TAG_BOOT_REASON    0x4f80
 #define OMAP_TAG_FLASH_PART     0x4f81
@@ -29,13 +30,26 @@ struct omap_clock_config {
        u8 system_clock_type;
 };
+struct omap_mmc_conf {
+        unsigned enabled:1;
+        /* nomux means "standard" muxing is wrong on this board, and that
+         * board-specific code handled it before common init logic.
+         */
+        unsigned nomux:1;
+        /* switch pin can be for card detect (default) or card cover */
+        unsigned cover:1;
+        /* 4 wire signaling is optional, and is only used for SD/SDIO */
+        unsigned wire4:1;
+        s16 power_pin;
+        s16 switch_pin;
+        s16 wp_pin;
+};
 struct omap_mmc_config {
-        u8 mmc_blocks;
+        struct omap_mmc_conf mmc[2];
-        s16 mmc1_power_pin, mmc2_power_pin;
-        s16 mmc1_switch_pin, mmc2_switch_pin;
 };
-struct omap_uart_config {
+struct omap_serial_console_config {
        u8 console_uart;
        u32 console_speed;
 };
@@ -82,7 +96,8 @@ struct omap_lcd_config {
 */
 #define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
 #define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT            0x0002
 struct omap_gpio_switch_config {
        char name[12];
        u16 gpio;
@@ -99,6 +114,10 @@ struct omap_boot_reason_config {
        char reason_str[12];
 };
+struct omap_uart_config {
+        /* Bit field of UARTs present; bit 0 --> UART1 */
+        unsigned int enabled_uarts;
+};
 struct omap_board_config_entry {
        u16 tag;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
new file mode 100644
index 000000000000..2a676b4f13b5
--- /dev/null
+++ b/include/asm-arm/arch-omap/common.h
@@ -0,0 +1,36 @@
+/*
+ * linux/include/asm-arm/arch-omap/common.h
+ *
+ * Header for code common to all OMAP machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
+#define __ARCH_ARM_MACH_OMAP_COMMON_H
+struct sys_timer;
+extern void omap_map_common_io(void);
+extern struct sys_timer omap_timer;
+extern void omap_serial_init(int ports[]);
+#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8786713ee5c..1119e2b53e72 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -38,146 +38,179 @@ extern unsigned int system_rev;
 /*
 * Test if multicore OMAP support is needed
 */
-#undef MULTI_OMAP
+#undef MULTI_OMAP1
+#undef MULTI_OMAP2
 #undef OMAP_NAME
 #ifdef CONFIG_ARCH_OMAP730
 # ifdef OMAP_NAME
-#  undef  MULTI_OMAP
+#  undef  MULTI_OMAP1
-#  define MULTI_OMAP
+#  define MULTI_OMAP1
 # else
 #  define OMAP_NAME omap730
 # endif
 #endif
 #ifdef CONFIG_ARCH_OMAP1510
 # ifdef OMAP_NAME
-#  undef  MULTI_OMAP
+#  undef  MULTI_OMAP1
-#  define MULTI_OMAP
+#  define MULTI_OMAP1
 # else
 #  define OMAP_NAME omap1510
 # endif
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 # ifdef OMAP_NAME
-#  undef  MULTI_OMAP
+#  undef  MULTI_OMAP1
-#  define MULTI_OMAP
+#  define MULTI_OMAP1
 # else
-#  define OMAP_NAME omap1610
+#  define OMAP_NAME omap16xx
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP16XX
+#ifdef CONFIG_ARCH_OMAP24XX
-# ifdef OMAP_NAME
+# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
-#  undef  MULTI_OMAP
+#  error "OMAP1 and OMAP2 can't be selected at the same time"
-#  define MULTI_OMAP
 # else
-#  define OMAP_NAME omap1710
+#  undef  MULTI_OMAP2
+#  define OMAP_NAME omap24xx
 # endif
 #endif
 /*
- * Generate various OMAP cpu specific macros, and cpu class
+ * Macros to group OMAP into cpu classes.
- * specific macros
+ * These can be used in most places.
+ * cpu_is_omap7xx():    True for OMAP730
+ * cpu_is_omap15xx():   True for OMAP1510 and OMAP5910
+ * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
+ * cpu_is_omap24xx():   True for OMAP2420
 */
-#define GET_OMAP_TYPE   ((system_rev >> 24) & 0xff)
 #define GET_OMAP_CLASS  (system_rev & 0xff)
-#define IS_OMAP_TYPE(type, id)                          \
-static inline int is_omap ##type (void)                 \
-{                                                       \
-        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
-}
 #define IS_OMAP_CLASS(class, id)                        \
 static inline int is_omap ##class (void)                \
 {                                                       \
        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
 }
-IS_OMAP_TYPE(730, 0x07)
-IS_OMAP_TYPE(1510, 0x15)
-IS_OMAP_TYPE(1610, 0x16)
-IS_OMAP_TYPE(5912, 0x16)
-IS_OMAP_TYPE(1710, 0x17)
-IS_OMAP_TYPE(2420, 0x24)
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
-/*
+#define cpu_is_omap7xx()                0
- * Macros to group OMAP types into cpu classes.
+#define cpu_is_omap15xx()               0
- * These can be used in most places.
+#define cpu_is_omap16xx()               0
- * cpu_is_omap15xx():   True for 1510 and 5910
+#define cpu_is_omap24xx()               0
- * cpu_is_omap16xx():   True for 1610, 5912 and 1710
- */
+#if defined(MULTI_OMAP1)
-#if defined(MULTI_OMAP)
+# if defined(CONFIG_ARCH_OMAP730)
-# define cpu_is_omap7xx()               is_omap7xx()
+#  undef  cpu_is_omap7xx
-# define cpu_is_omap15xx()              is_omap15xx()
+#  define cpu_is_omap7xx()              is_omap7xx()
-# if !(defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP730))
+# endif
-#  define cpu_is_omap16xx()             1
+# if defined(CONFIG_ARCH_OMAP1510)
-# else
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             is_omap15xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
 #  define cpu_is_omap16xx()             is_omap16xx()
 # endif
 #else
 # if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
 #  define cpu_is_omap7xx()              1
-# else
-#  define cpu_is_omap7xx()              0
 # endif
 # if defined(CONFIG_ARCH_OMAP1510)
+#  undef  cpu_is_omap15xx
 #  define cpu_is_omap15xx()             1
-# else
-#  define cpu_is_omap15xx()             0
 # endif
 # if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
 #  define cpu_is_omap16xx()             1
-# else
+# endif
-#  define cpu_is_omap16xx()             0
+# if defined(CONFIG_ARCH_OMAP24XX)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             1
 # endif
 #endif
-#if defined(MULTI_OMAP)
+/*
-# define cpu_is_omap730()               is_omap730()
+ * Macros to detect individual cpu types.
-# define cpu_is_omap1510()              is_omap1510()
+ * These are only rarely needed.
-# define cpu_is_omap1610()              is_omap1610()
+ * cpu_is_omap730():    True for OMAP730
-# define cpu_is_omap5912()              is_omap5912()
+ * cpu_is_omap1510():   True for OMAP1510
-# define cpu_is_omap1710()              is_omap1710()
+ * cpu_is_omap1610():   True for OMAP1610
+ * cpu_is_omap1611():   True for OMAP1611
+ * cpu_is_omap5912():   True for OMAP5912
+ * cpu_is_omap1621():   True for OMAP1621
+ * cpu_is_omap1710():   True for OMAP1710
+ * cpu_is_omap2420():   True for OMAP2420
+ */
+#define GET_OMAP_TYPE   ((system_rev >> 16) & 0xffff)
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+IS_OMAP_TYPE(730, 0x0730)
+IS_OMAP_TYPE(1510, 0x1510)
+IS_OMAP_TYPE(1610, 0x1610)
+IS_OMAP_TYPE(1611, 0x1611)
+IS_OMAP_TYPE(5912, 0x1611)
+IS_OMAP_TYPE(1621, 0x1621)
+IS_OMAP_TYPE(1710, 0x1710)
+IS_OMAP_TYPE(2420, 0x2420)
+#define cpu_is_omap730()                0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap5912()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+#define cpu_is_omap2420()               0
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap730
+#  define cpu_is_omap730()              is_omap730()
+# endif
+# if defined(CONFIG_ARCH_OMAP1510)
+#  undef  cpu_is_omap1510
+#  define cpu_is_omap1510()             is_omap1510()
+# endif
 #else
 # if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap730
 #  define cpu_is_omap730()              1
-# else
-#  define cpu_is_omap730()              0
 # endif
 # if defined(CONFIG_ARCH_OMAP1510)
+#  undef  cpu_is_omap1510
 #  define cpu_is_omap1510()             1
-# else
-#  define cpu_is_omap1510()             0
 # endif
-# if defined(CONFIG_ARCH_OMAP16XX)
+#endif
-#  define cpu_is_omap1610()             1
-# else
+/*
-#  define cpu_is_omap1610()             0
+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
-# endif
+ * between 1611B/5912 and 1710.
-# if defined(CONFIG_ARCH_OMAP16XX)
+ */
-#  define cpu_is_omap5912()             1
+#if defined(CONFIG_ARCH_OMAP16XX)
-# else
+# undef  cpu_is_omap1610
-#  define cpu_is_omap5912()             0
+# undef  cpu_is_omap1611
-# endif
+# undef  cpu_is_omap5912
-# if defined(CONFIG_ARCH_OMAP16XX)
+# undef  cpu_is_omap1621
+# undef  cpu_is_omap1710
 # define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap1611()              is_omap1611()
 # define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1621()              is_omap1621()
 # define cpu_is_omap1710()              is_omap1710()
-# else
+#endif
-# define cpu_is_omap1610()              0
-# define cpu_is_omap5912()              0
+#if defined(CONFIG_ARCH_OMAP2420)
-# define cpu_is_omap1710()              0
+#  undef  cpu_is_omap2420
-# endif
-# if defined(CONFIG_ARCH_OMAP2420)
 #  define cpu_is_omap2420()             1
-# else
-#  define cpu_is_omap2420()             0
-# endif
 #endif
 #endif
diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S
index 83bb458afd0b..ca4f577f9675 100644
--- a/include/asm-arm/arch-omap/debug-macro.S
+++ b/include/asm-arm/arch-omap/debug-macro.S
@@ -14,6 +14,7 @@
                .macro  addruart,rx
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
+#ifdef CONFIG_ARCH_OMAP1
                moveq   \rx, #0xff000000        @ physical base address
                movne   \rx, #0xfe000000        @ virtual base
                orr     \rx, \rx, #0x00fb0000
@@ -23,6 +24,18 @@
 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
                orr     \rx, \rx, #0x00000800   @ UART 2 & 3
 #endif
+#elif  CONFIG_ARCH_OMAP2
+                moveq   \rx, #0x48000000        @ physical base address
+                movne   \rx, #0xd8000000        @ virtual base
+                orr     \rx, \rx, #0x0006a000
+#ifdef CONFIG_OMAP_LL_DEBUG_UART2
+                add     \rx, \rx, #0x00002000   @ UART 2
+#endif
+#ifdef CONFIG_OMAP_LL_DEBUG_UART3
+                add     \rx, \rx, #0x00004000   @ UART 3
+#endif
+#endif
                .endm
                .macro  senduart,rd,rx
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index d785248377db..04ebef5c6e95 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -240,7 +240,9 @@ extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
 extern dma_addr_t omap_get_dma_src_pos(int lch);
 extern dma_addr_t omap_get_dma_dst_pos(int lch);
+extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
+extern int omap_dma_running(void);
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 extern int omap_dma_in_1510_mode(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
new file mode 100644
index 000000000000..11772c792f3e
--- /dev/null
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -0,0 +1,92 @@
+/*
+ * linux/include/asm-arm/arm/arch-omap/dmtimer.h
+ *
+ * OMAP Dual-Mode Timers
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_TIMER_H
+#define __ASM_ARCH_TIMER_H
+#include <linux/list.h>
+#define OMAP_TIMER_SRC_ARMXOR           0x00
+#define OMAP_TIMER_SRC_32_KHZ           0x01
+#define OMAP_TIMER_SRC_EXT_CLK          0x02
+/* timer control reg bits */
+#define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
+#define OMAP_TIMER_CTRL_PT              (1 << 12)
+#define OMAP_TIMER_CTRL_TRG_OVERFLOW    (0x1 << 10)
+#define OMAP_TIMER_CTRL_TRG_OFANDMATCH  (0x2 << 10)
+#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
+#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
+#define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
+#define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
+#define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
+#define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
+#define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
+#define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
+#define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
+/* timer interrupt enable bits */
+#define OMAP_TIMER_INT_CAPTURE          (1 << 2)
+#define OMAP_TIMER_INT_OVERFLOW         (1 << 1)
+#define OMAP_TIMER_INT_MATCH            (1 << 0)
+struct omap_dm_timer {
+        struct list_head timer_list;
+        u32 base;
+        unsigned int irq;
+};
+u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg);
+void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value);
+struct omap_dm_timer * omap_dm_timer_request(void);
+void omap_dm_timer_free(struct omap_dm_timer *timer);
+void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
+void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value);
+void omap_dm_timer_enable_compare(struct omap_dm_timer *timer);
+void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer);
+void omap_dm_timer_trigger(struct omap_dm_timer *timer);
+void omap_dm_timer_start(struct omap_dm_timer *timer);
+void omap_dm_timer_stop(struct omap_dm_timer *timer);
+void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load);
+void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match);
+unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
+void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
+void omap_dm_timer_reset_counter(struct omap_dm_timer *timer);
+int omap_dm_timers_active(void);
+#endif /* __ASM_ARCH_TIMER_H */
diff --git a/include/asm-arm/arch-omap/dsp.h b/include/asm-arm/arch-omap/dsp.h
new file mode 100644
index 000000000000..57bf4f39ca58
--- /dev/null
+++ b/include/asm-arm/arch-omap/dsp.h
@@ -0,0 +1,244 @@
+/*
+ * linux/include/asm-arm/arch-omap/dsp.h
+ *
+ * Header for OMAP DSP driver
+ *
+ * Copyright (C) 2002-2005 Nokia Corporation
+ *
+ * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * 2005/06/01:  DSP Gateway version 3.3
+ */
+#ifndef ASM_ARCH_DSP_H
+#define ASM_ARCH_DSP_H
+/*
+ * for /dev/dspctl/ctl
+ */
+#define OMAP_DSP_IOCTL_RESET                    1
+#define OMAP_DSP_IOCTL_RUN                      2
+#define OMAP_DSP_IOCTL_SETRSTVECT               3
+#define OMAP_DSP_IOCTL_CPU_IDLE                 4
+#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_ON         5
+#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_OFF        6
+#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_ON         7
+#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_OFF        8
+#define OMAP_DSP_IOCTL_GBL_IDLE                 9
+#define OMAP_DSP_IOCTL_DSPCFG                   10
+#define OMAP_DSP_IOCTL_DSPUNCFG                 11
+#define OMAP_DSP_IOCTL_TASKCNT                  12
+#define OMAP_DSP_IOCTL_POLL                     13
+#define OMAP_DSP_IOCTL_REGMEMR                  40
+#define OMAP_DSP_IOCTL_REGMEMW                  41
+#define OMAP_DSP_IOCTL_REGIOR                   42
+#define OMAP_DSP_IOCTL_REGIOW                   43
+#define OMAP_DSP_IOCTL_GETVAR                   44
+#define OMAP_DSP_IOCTL_SETVAR                   45
+#define OMAP_DSP_IOCTL_RUNLEVEL                 50
+#define OMAP_DSP_IOCTL_SUSPEND                  51
+#define OMAP_DSP_IOCTL_RESUME                   52
+#define OMAP_DSP_IOCTL_FBEN                     53
+#define OMAP_DSP_IOCTL_FBDIS                    54
+#define OMAP_DSP_IOCTL_MBSEND                   99
+/*
+ * for taskdev
+ * (ioctls below should be >= 0x10000)
+ */
+#define OMAP_DSP_TASK_IOCTL_BFLSH       0x10000
+#define OMAP_DSP_TASK_IOCTL_SETBSZ      0x10001
+#define OMAP_DSP_TASK_IOCTL_LOCK        0x10002
+#define OMAP_DSP_TASK_IOCTL_UNLOCK      0x10003
+#define OMAP_DSP_TASK_IOCTL_GETNAME     0x10004
+/*
+ * for /dev/dspctl/mem
+ */
+#define OMAP_DSP_MEM_IOCTL_EXMAP        1
+#define OMAP_DSP_MEM_IOCTL_EXUNMAP      2
+#define OMAP_DSP_MEM_IOCTL_EXMAP_FLUSH  3
+#define OMAP_DSP_MEM_IOCTL_FBEXPORT     5
+#define OMAP_DSP_MEM_IOCTL_MMUITACK     7
+#define OMAP_DSP_MEM_IOCTL_MMUINIT      9
+#define OMAP_DSP_MEM_IOCTL_KMEM_RESERVE 11
+#define OMAP_DSP_MEM_IOCTL_KMEM_RELEASE 12
+struct omap_dsp_mapinfo {
+        unsigned long dspadr;
+        unsigned long size;
+};
+/*
+ * for /dev/dspctl/twch
+ */
+#define OMAP_DSP_TWCH_IOCTL_MKDEV       1
+#define OMAP_DSP_TWCH_IOCTL_RMDEV       2
+#define OMAP_DSP_TWCH_IOCTL_TADD        11
+#define OMAP_DSP_TWCH_IOCTL_TDEL        12
+#define OMAP_DSP_TWCH_IOCTL_TKILL       13
+#define OMAP_DSP_DEVSTATE_NOTASK        0x00000001
+#define OMAP_DSP_DEVSTATE_ATTACHED      0x00000002
+#define OMAP_DSP_DEVSTATE_GARBAGE       0x00000004
+#define OMAP_DSP_DEVSTATE_INVALID       0x00000008
+#define OMAP_DSP_DEVSTATE_ADDREQ        0x00000100
+#define OMAP_DSP_DEVSTATE_DELREQ        0x00000200
+#define OMAP_DSP_DEVSTATE_ADDFAIL       0x00001000
+#define OMAP_DSP_DEVSTATE_ADDING        0x00010000
+#define OMAP_DSP_DEVSTATE_DELING        0x00020000
+#define OMAP_DSP_DEVSTATE_KILLING       0x00040000
+#define OMAP_DSP_DEVSTATE_STATE_MASK    0x7fffffff
+#define OMAP_DSP_DEVSTATE_STALE         0x80000000
+struct omap_dsp_taddinfo {
+        unsigned char minor;
+        unsigned long taskadr;
+};
+#define OMAP_DSP_TADD_ABORTADR  0xffffffff
+/*
+ * error cause definition (for error detection device)
+ */
+#define OMAP_DSP_ERRDT_WDT      0x00000001
+#define OMAP_DSP_ERRDT_MMU      0x00000002
+/*
+ * mailbox protocol definitions
+ */
+struct omap_dsp_mailbox_cmd {
+        unsigned short cmd;
+        unsigned short data;
+};
+struct omap_dsp_reginfo {
+        unsigned short adr;
+        unsigned short val;
+};
+struct omap_dsp_varinfo {
+        unsigned char varid;
+        unsigned short val[0];
+};
+#define OMAP_DSP_MBPROT_REVISION        0x0019
+#define OMAP_DSP_MBCMD_WDSND    0x10
+#define OMAP_DSP_MBCMD_WDREQ    0x11
+#define OMAP_DSP_MBCMD_BKSND    0x20
+#define OMAP_DSP_MBCMD_BKREQ    0x21
+#define OMAP_DSP_MBCMD_BKYLD    0x23
+#define OMAP_DSP_MBCMD_BKSNDP   0x24
+#define OMAP_DSP_MBCMD_BKREQP   0x25
+#define OMAP_DSP_MBCMD_TCTL     0x30
+#define OMAP_DSP_MBCMD_TCTLDATA 0x31
+#define OMAP_DSP_MBCMD_POLL     0x32
+#define OMAP_DSP_MBCMD_WDT      0x50    /* v3.3: obsolete */
+#define OMAP_DSP_MBCMD_RUNLEVEL 0x51
+#define OMAP_DSP_MBCMD_PM       0x52
+#define OMAP_DSP_MBCMD_SUSPEND  0x53
+#define OMAP_DSP_MBCMD_KFUNC    0x54
+#define OMAP_DSP_MBCMD_TCFG     0x60
+#define OMAP_DSP_MBCMD_TADD     0x62
+#define OMAP_DSP_MBCMD_TDEL     0x63
+#define OMAP_DSP_MBCMD_TSTOP    0x65
+#define OMAP_DSP_MBCMD_DSPCFG   0x70
+#define OMAP_DSP_MBCMD_REGRW    0x72
+#define OMAP_DSP_MBCMD_GETVAR   0x74
+#define OMAP_DSP_MBCMD_SETVAR   0x75
+#define OMAP_DSP_MBCMD_ERR      0x78
+#define OMAP_DSP_MBCMD_DBG      0x79
+#define OMAP_DSP_MBCMD_TCTL_TINIT       0x0000
+#define OMAP_DSP_MBCMD_TCTL_TEN         0x0001
+#define OMAP_DSP_MBCMD_TCTL_TDIS        0x0002
+#define OMAP_DSP_MBCMD_TCTL_TCLR        0x0003
+#define OMAP_DSP_MBCMD_TCTL_TCLR_FORCE  0x0004
+#define OMAP_DSP_MBCMD_RUNLEVEL_USER            0x01
+#define OMAP_DSP_MBCMD_RUNLEVEL_SUPER           0x0e
+#define OMAP_DSP_MBCMD_RUNLEVEL_RECOVERY        0x10
+#define OMAP_DSP_MBCMD_PM_DISABLE       0x00
+#define OMAP_DSP_MBCMD_PM_ENABLE        0x01
+#define OMAP_DSP_MBCMD_KFUNC_FBCTL      0x00
+#define OMAP_DSP_MBCMD_FBCTL_ENABLE     0x0002
+#define OMAP_DSP_MBCMD_FBCTL_DISABLE    0x0003
+#define OMAP_DSP_MBCMD_TDEL_SAFE        0x0000
+#define OMAP_DSP_MBCMD_TDEL_KILL        0x0001
+#define OMAP_DSP_MBCMD_DSPCFG_REQ       0x00
+#define OMAP_DSP_MBCMD_DSPCFG_SYSADRH   0x28
+#define OMAP_DSP_MBCMD_DSPCFG_SYSADRL   0x29
+#define OMAP_DSP_MBCMD_DSPCFG_PROTREV   0x70
+#define OMAP_DSP_MBCMD_DSPCFG_ABORT     0x78
+#define OMAP_DSP_MBCMD_DSPCFG_LAST      0x80
+#define OMAP_DSP_MBCMD_REGRW_MEMR       0x00
+#define OMAP_DSP_MBCMD_REGRW_MEMW       0x01
+#define OMAP_DSP_MBCMD_REGRW_IOR        0x02
+#define OMAP_DSP_MBCMD_REGRW_IOW        0x03
+#define OMAP_DSP_MBCMD_REGRW_DATA       0x04
+#define OMAP_DSP_MBCMD_VARID_ICRMASK    0x00
+#define OMAP_DSP_MBCMD_VARID_LOADINFO   0x01
+#define OMAP_DSP_TTYP_ARCV      0x0001
+#define OMAP_DSP_TTYP_ASND      0x0002
+#define OMAP_DSP_TTYP_BKMD      0x0004
+#define OMAP_DSP_TTYP_BKDM      0x0008
+#define OMAP_DSP_TTYP_PVMD      0x0010
+#define OMAP_DSP_TTYP_PVDM      0x0020
+#define OMAP_DSP_EID_BADTID     0x10
+#define OMAP_DSP_EID_BADTCN     0x11
+#define OMAP_DSP_EID_BADBID     0x20
+#define OMAP_DSP_EID_BADCNT     0x21
+#define OMAP_DSP_EID_NOTLOCKED  0x22
+#define OMAP_DSP_EID_STVBUF     0x23
+#define OMAP_DSP_EID_BADADR     0x24
+#define OMAP_DSP_EID_BADTCTL    0x30
+#define OMAP_DSP_EID_BADPARAM   0x50
+#define OMAP_DSP_EID_FATAL      0x58
+#define OMAP_DSP_EID_NOMEM      0xc0
+#define OMAP_DSP_EID_NORES      0xc1
+#define OMAP_DSP_EID_IPBFULL    0xc2
+#define OMAP_DSP_EID_WDT        0xd0
+#define OMAP_DSP_EID_TASKNOTRDY 0xe0
+#define OMAP_DSP_EID_TASKBSY    0xe1
+#define OMAP_DSP_EID_TASKERR    0xef
+#define OMAP_DSP_EID_BADCFGTYP  0xf0
+#define OMAP_DSP_EID_DEBUG      0xf8
+#define OMAP_DSP_EID_BADSEQ     0xfe
+#define OMAP_DSP_EID_BADCMD     0xff
+#define OMAP_DSP_TNM_LEN        16
+#define OMAP_DSP_TID_FREE       0xff
+#define OMAP_DSP_TID_ANON       0xfe
+#define OMAP_DSP_BID_NULL       0xffff
+#define OMAP_DSP_BID_PVT        0xfffe
+#endif /* ASM_ARCH_DSP_H */
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h
new file mode 100644
index 000000000000..4fcce6944056
--- /dev/null
+++ b/include/asm-arm/arch-omap/dsp_common.h
@@ -0,0 +1,37 @@
+/*
+ * linux/include/asm-arm/arch-omap/dsp_common.h
+ *
+ * Header for OMAP DSP subsystem control
+ *
+ * Copyright (C) 2004,2005 Nokia Corporation
+ *
+ * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * 2005/06/03:  DSP Gateway version 3.3
+ */
+#ifndef ASM_ARCH_DSP_COMMON_H
+#define ASM_ARCH_DSP_COMMON_H
+void omap_dsp_pm_suspend(void);
+void omap_dsp_pm_resume(void);
+void omap_dsp_request_mpui(void);
+void omap_dsp_release_mpui(void);
+int omap_dsp_request_mem(void);
+int omap_dsp_release_mem(void);
+#endif /* ASM_ARCH_DSP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index 57b126889b98..0d29b9c56a95 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -8,6 +8,8 @@
 * warranty of any kind, whether express or implied.
 */
+#if defined(CONFIG_ARCH_OMAP1)
                .macro  disable_fiq
                .endm
@@ -30,3 +32,29 @@
 1510:
                .endm
+#elif defined(CONFIG_ARCH_OMAP24XX)
+#include <asm/arch/omap24xx.h>
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =VA_IC_BASE
+                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
+                cmp     \irqnr, #0x0
+                bne     2222f
+                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
+                cmp     \irqnr, #0x0
+                bne     2222f
+                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+                cmp     \irqnr, #0x0
+2222:
+                ldrne   \irqnr, [\base, #IRQ_SIR_IRQ]
+                .endm
+                .macro  irq_prio_table
+                .endm
+#endif
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index fad2fc93ee70..74cb2b93b700 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -3,7 +3,7 @@
 *
 * OMAP GPIO handling defines and functions
 *
- * Copyright (C) 2003 Nokia Corporation
+ * Copyright (C) 2003-2005 Nokia Corporation
 *
 * Written by Juha Yrj�l� <juha.yrjola@nokia.com>
 *
@@ -30,7 +30,23 @@
 #include <asm/arch/irqs.h>
 #include <asm/io.h>
-#define OMAP_MPUIO_BASE                 0xfffb5000
+#define OMAP_MPUIO_BASE                 (void __iomem *)0xfffb5000
+#ifdef CONFIG_ARCH_OMAP730
+#define OMAP_MPUIO_INPUT_LATCH          0x00
+#define OMAP_MPUIO_OUTPUT               0x02
+#define OMAP_MPUIO_IO_CNTL              0x04
+#define OMAP_MPUIO_KBR_LATCH            0x08
+#define OMAP_MPUIO_KBC                  0x0a
+#define OMAP_MPUIO_GPIO_EVENT_MODE      0x0c
+#define OMAP_MPUIO_GPIO_INT_EDGE        0x0e
+#define OMAP_MPUIO_KBD_INT              0x10
+#define OMAP_MPUIO_GPIO_INT             0x12
+#define OMAP_MPUIO_KBD_MASKIT           0x14
+#define OMAP_MPUIO_GPIO_MASKIT          0x16
+#define OMAP_MPUIO_GPIO_DEBOUNCING      0x18
+#define OMAP_MPUIO_LATCH                0x1a
+#else
 #define OMAP_MPUIO_INPUT_LATCH          0x00
 #define OMAP_MPUIO_OUTPUT               0x04
 #define OMAP_MPUIO_IO_CNTL              0x08
@@ -44,6 +60,7 @@
 #define OMAP_MPUIO_GPIO_MASKIT          0x2c
 #define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
 #define OMAP_MPUIO_LATCH                0x34
+#endif
 #define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
@@ -52,18 +69,11 @@
                                 IH_MPUIO_BASE + ((nr) & 0x0f) : \
                                 IH_GPIO_BASE + ((nr) & 0x3f))
-/* For EDGECTRL */
-#define OMAP_GPIO_NO_EDGE         0x00
-#define OMAP_GPIO_FALLING_EDGE    0x01
-#define OMAP_GPIO_RISING_EDGE     0x02
-#define OMAP_GPIO_BOTH_EDGES      0x03
 extern int omap_gpio_init(void);        /* Call from board init only */
 extern int omap_request_gpio(int gpio);
 extern void omap_free_gpio(int gpio);
 extern void omap_set_gpio_direction(int gpio, int is_input);
 extern void omap_set_gpio_dataout(int gpio, int enable);
 extern int omap_get_gpio_datain(int gpio);
-extern void omap_set_gpio_edge_ctrl(int gpio, int edge);
 #endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 37e06c782bdf..60201e1dd6ad 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -43,6 +43,7 @@
 #include <asm/arch/cpu.h>
 #endif
 #include <asm/arch/io.h>
+#include <asm/arch/serial.h>
 /*
 * ---------------------------------------------------------------------------
@@ -54,6 +55,19 @@
 /*
 * ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE    (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE    (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE    (0xfffec700)
+#define MPU_TIMER_FREE          (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
+#define MPU_TIMER_AR            (1 << 1)
+#define MPU_TIMER_ST            (1 << 0)
+/*
+ * ----------------------------------------------------------------------------
 * Clocks
 * ----------------------------------------------------------------------------
 */
@@ -76,10 +90,12 @@
 /* DPLL control registers */
 #define DPLL_CTL                (0xfffecf00)
-/* DSP clock control */
+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
 #define DSP_CONFIG_REG_BASE     (0xe1008000)
+#define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
 #define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
 #define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
+#define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
 /*
 * ---------------------------------------------------------------------------
@@ -88,6 +104,7 @@
 */
 #define ULPD_REG_BASE           (0xfffe0800)
 #define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
 #define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
 #       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
 #       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
@@ -127,6 +144,13 @@
 * Interrupts
 * ---------------------------------------------------------------------------
 */
+#ifdef CONFIG_ARCH_OMAP1
+/*
+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
+ * or something similar.. -- PFM.
+ */
 #define OMAP_IH1_BASE           0xfffecb00
 #define OMAP_IH2_BASE           0xfffe0000
@@ -155,6 +179,8 @@
 #define IRQ_ILR0_REG_OFFSET     0x1c
 #define IRQ_GMR_REG_OFFSET      0xa0
+#endif
 /*
 * ----------------------------------------------------------------------------
 * System control registers
@@ -245,40 +271,18 @@
 /*
 * ---------------------------------------------------------------------------
- * Serial ports
- * ---------------------------------------------------------------------------
- */
-#define OMAP_UART1_BASE         (unsigned char *)0xfffb0000
-#define OMAP_UART2_BASE         (unsigned char *)0xfffb0800
-#define OMAP_UART3_BASE         (unsigned char *)0xfffb9800
-#define OMAP_MAX_NR_PORTS       3
-#define OMAP1510_BASE_BAUD      (12000000/16)
-#define OMAP16XX_BASE_BAUD      (48000000/16)
-#define is_omap_port(p) ({int __ret = 0;                        \
-                        if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
-                            p == IO_ADDRESS(OMAP_UART2_BASE) || \
-                            p == IO_ADDRESS(OMAP_UART3_BASE))   \
-                                __ret = 1;                      \
-                        __ret;                                  \
-                        })
-/*
- * ---------------------------------------------------------------------------
 * Processor specific defines
 * ---------------------------------------------------------------------------
 */
-#ifdef CONFIG_ARCH_OMAP730
-#include "omap730.h"
-#endif
-#ifdef CONFIG_ARCH_OMAP1510
+#include "omap730.h"
 #include "omap1510.h"
+#ifdef CONFIG_ARCH_OMAP24XX
+#include "omap24xx.h"
 #endif
-#ifdef CONFIG_ARCH_OMAP16XX
 #include "omap16xx.h"
-#endif
 /*
 * ---------------------------------------------------------------------------
@@ -304,7 +308,6 @@
 #ifdef CONFIG_MACH_OMAP_H4
 #include "board-h4.h"
-#error "Support for H4 board not yet implemented."
 #endif
 #ifdef CONFIG_MACH_OMAP_OSK
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 1c8c9fcc766e..11fbf629bf75 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -49,16 +49,24 @@
 * I/O mapping
 * ----------------------------------------------------------------------------
 */
-#define IO_PHYS                 0xFFFB0000
-#define IO_OFFSET               0x01000000      /* Virtual IO = 0xfefb0000 */
-#define IO_VIRT                 (IO_PHYS - IO_OFFSET)
-#define IO_SIZE                 0x40000
-#define IO_ADDRESS(x)           ((x) - IO_OFFSET)
-#define PCIO_BASE               0
+#if defined(CONFIG_ARCH_OMAP1)
+#define IO_PHYS         0xFFFB0000
+#define IO_OFFSET      -0x01000000      /* Virtual IO = 0xfefb0000 */
+#define IO_SIZE         0x40000
-#define io_p2v(x)               ((x) - IO_OFFSET)
+#elif defined(CONFIG_ARCH_OMAP2)
-#define io_v2p(x)               ((x) + IO_OFFSET)
+#define IO_PHYS         0x48000000      /* L4 peripherals; other stuff has to be mapped *
+                                         * manually. */
+#define IO_OFFSET       0x90000000      /* Virtual IO = 0xd8000000 */
+#define IO_SIZE         0x08000000
+#endif
+#define IO_VIRT         (IO_PHYS + IO_OFFSET)
+#define IO_ADDRESS(x)   ((x) + IO_OFFSET)
+#define PCIO_BASE       0
+#define io_p2v(x)       ((x) + IO_OFFSET)
+#define io_v2p(x)       ((x) - IO_OFFSET)
 #ifndef __ASSEMBLER__
@@ -96,6 +104,8 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
                                        ->offset[((vaddr)&4095)>>2]
 #define __REG32(paddr)          __REGV32(io_p2v(paddr))
+extern void omap_map_common_io(void);
 #else
 #define __REG8(paddr)           io_p2v(paddr)
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 6701fd9e5f9b..74e108ccac16 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -135,7 +135,6 @@
 /*
 * OMAP-1510 specific IRQ numbers for interrupt handler 2
 */
-#define INT_1510_OS_32kHz_TIMER (22 + IH2_BASE)
 #define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
 /*
@@ -159,6 +158,7 @@
 #define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
 #define INT_1610_MMC2           (42 + IH2_BASE)
 #define INT_1610_CF             (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
 #define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
 #define INT_1610_SPI            (49 + IH2_BASE)
 #define INT_1610_DMA_CH6        (53 + IH2_BASE)
@@ -231,6 +231,11 @@
 #define INT_730_DMA_CH15        (62 + IH2_BASE)
 #define INT_730_NAND            (63 + IH2_BASE)
+#define INT_24XX_GPIO_BANK1     29
+#define INT_24XX_GPIO_BANK2     30
+#define INT_24XX_GPIO_BANK3     31
+#define INT_24XX_GPIO_BANK4     32
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
 * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES     192
@@ -238,6 +243,8 @@
 #define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
 #define IH_BOARD_BASE           (16 + IH_MPUIO_BASE)
+#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 #ifndef __ASSEMBLY__
 extern void omap_init_irq(void);
 #endif
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index f6b57dd846a3..84f81e315a25 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -36,12 +36,11 @@
 /*
 * Physical DRAM offset.
 */
+#if defined(CONFIG_ARCH_OMAP1)
 #define PHYS_OFFSET             (0x10000000UL)
+#elif defined(CONFIG_ARCH_OMAP2)
-/*
+#define PHYS_OFFSET             (0x80000000UL)
- * OMAP-1510 Local Bus address offset
+#endif
- */
-#define OMAP1510_LB_OFFSET      (0x30000000UL)
 /*
 * Conversion between SDRAM and fake PCI bus, used by USB
@@ -64,6 +63,11 @@
 */
 #ifdef CONFIG_ARCH_OMAP1510
+/*
+ * OMAP-1510 Local Bus address offset
+ */
+#define OMAP1510_LB_OFFSET      (0x30000000UL)
 #define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
 #define is_lbus_device(dev)     (cpu_is_omap1510() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
diff --git a/include/asm-arm/arch-omap/mtd-xip.h b/include/asm-arm/arch-omap/mtd-xip.h
new file mode 100644
index 000000000000..a73a28571fee
--- /dev/null
+++ b/include/asm-arm/arch-omap/mtd-xip.h
@@ -0,0 +1,61 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions.
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ *
+ * Author: Vladimir Barinov <vbarinov@ru.mvista.com>
+ *
+ * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
+ * terms of the GNU General Public License version 2.  This program is
+ * licensed "as is" without any warranty of any kind, whether express or
+ * implied.
+ */
+#ifndef __ARCH_OMAP_MTD_XIP_H__
+#define __ARCH_OMAP_MTD_XIP_H__
+#include <asm/hardware.h>
+#define OMAP_MPU_TIMER_BASE     (0xfffec500)
+#define OMAP_MPU_TIMER_OFFSET   0x100
+typedef struct {
+        u32 cntl;                       /* CNTL_TIMER, R/W */
+        u32 load_tim;                   /* LOAD_TIM,   W */
+        u32 read_tim;                   /* READ_TIM,   R */
+} xip_omap_mpu_timer_regs_t;
+#define xip_omap_mpu_timer_base(n)                                      \
+((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +  \
+        (n)*OMAP_MPU_TIMER_OFFSET))
+static inline unsigned long xip_omap_mpu_timer_read(int nr)
+{
+        volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
+        return timer->read_tim;
+}
+#define xip_irqpending()        \
+        (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
+#define xip_currtime()          (~xip_omap_mpu_timer_read(0))
+/*
+ * It's permitted to do approxmation for xip_elapsed_since macro
+ * (see linux/mtd/xip.h)
+ */
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
+#else
+#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
+#endif
+/*
+ * xip_cpu_idle() is used when waiting for a delay equal or larger than
+ * the system timer tick period.  This should put the CPU into idle mode
+ * to save power and to be woken up only when some interrupts are pending.
+ * As above, this should not rely upon standard kernel code.
+ */
+#define xip_cpu_idle()  asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
+#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 39f99decbb7b..1b1ad4105349 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -185,6 +185,7 @@ typedef enum {
        /* MPUIO */
        MPUIO2,
+        N15_1610_MPUIO2,
        MPUIO4,
        MPUIO5,
        T20_1610_MPUIO5,
@@ -210,6 +211,7 @@ typedef enum {
        /* Misc ballouts */
        BALLOUT_V8_ARMIO3,
+        N20_HDQ,
        /* OMAP-1610 MMC2 */
        W8_1610_MMC2_DAT0,
@@ -231,23 +233,27 @@ typedef enum {
        J19_1610_ETM_D6,
        J18_1610_ETM_D7,
-        /* OMAP-1610 GPIO */
+        /* OMAP16XX GPIO */
        P20_1610_GPIO4,
        V9_1610_GPIO7,
        W8_1610_GPIO9,
+        N20_1610_GPIO11,
        N19_1610_GPIO13,
        P10_1610_GPIO22,
        V5_1610_GPIO24,
        AA20_1610_GPIO_41,
        W19_1610_GPIO48,
        M7_1610_GPIO62,
+        V14_16XX_GPIO37,
+        R9_16XX_GPIO18,
+        L14_16XX_GPIO49,
        /* OMAP-1610 uWire */
        V19_1610_UWIRE_SCLK,
        U18_1610_UWIRE_SDI,
        W21_1610_UWIRE_SDO,
        N14_1610_UWIRE_CS0,
-        P15_1610_UWIRE_CS0,
+        P15_1610_UWIRE_CS3,
        N15_1610_UWIRE_CS1,
        /* OMAP-1610 Flash */
@@ -285,12 +291,13 @@ typedef enum {
        V6_USB2_TXD,
        W5_USB2_SE0,
-        /* UART1 1610 */
+        /* 16XX UART */
        R13_1610_UART1_TX,
-        V14_1610_UART1_RX,
+        V14_16XX_UART1_RX,
        R14_1610_UART1_CTS,
        AA15_1610_UART1_RTS,
+        R9_16XX_UART2_RX,
+        L14_16XX_UART3_RX,
        /* I2C OMAP-1610 */
        I2C_SCL,
@@ -332,7 +339,7 @@ typedef enum {
 * Table of various FUNC_MUX and PULL_DWN combinations for each device.
 * See also reg_cfg_t above for the lookup table.
 */
-static reg_cfg_set __initdata_or_module
+static const reg_cfg_set __initdata_or_module
 reg_cfg_table[] = {
 /*
 *       description            mux  mode   mux  pull pull  pull  pu_pd  pu  dbg
@@ -407,7 +414,8 @@ MUX_CFG("N21_1710_GPIO14",       6,    9,    0,   1,   1,   1,    1,     1,  1)
 MUX_CFG("W15_1710_GPIO40",       9,   27,    7,   2,   5,   1,    2,     1,  1)
 /* MPUIO */
-MUX_CFG("MPUIO2",                7,   18,    0,   1,   1,   1,   NA,     0,  1)
+MUX_CFG("MPUIO2",                7,   18,    0,   1,  14,   1,   NA,     0,  1)
+MUX_CFG("N15_1610_MPUIO2",       7,   18,    0,   1,  14,   1,    1,     0,  1)
 MUX_CFG("MPUIO4",                7,   15,    0,   1,  13,   1,   NA,     0,  1)
 MUX_CFG("MPUIO5",                7,   12,    0,   1,  12,   1,   NA,     0,  1)
@@ -434,6 +442,7 @@ MUX_CFG("MCBSP3_CLKX",		 9,    3,    1,	  1,  29,   0,	 NA,	 0,  1)
 /* Misc ballouts */
 MUX_CFG("BALLOUT_V8_ARMIO3",     B,   18,    0,   2,  25,   1,   NA,     0,  1)
+MUX_CFG("N20_HDQ",             6,   18,    1,   1,   4,   0,    1,     4,  0)
 /* OMAP-1610 MMC2 */
 MUX_CFG("W8_1610_MMC2_DAT0",     B,   21,    6,   2,  23,   1,    2,     1,  1)
@@ -455,16 +464,20 @@ MUX_CFG("L19_1610_ETM_D0",	 5,   18,    1,	  0,  26,   0,	  0,	 0,  1)
 MUX_CFG("J19_1610_ETM_D6",       5,    0,    1,   0,  20,   0,    0,     0,  1)
 MUX_CFG("J18_1610_ETM_D7",       5,   27,    1,   0,  19,   0,    0,     0,  1)
-/* OMAP-1610 GPIO */
+/* OMAP16XX GPIO */
 MUX_CFG("P20_1610_GPIO4",        6,   27,    0,   1,   7,   0,    1,     1,  1)
 MUX_CFG("V9_1610_GPIO7",         B,   12,    1,   2,  20,   0,    2,     1,  1)
 MUX_CFG("W8_1610_GPIO9",         B,   21,    0,   2,  23,   0,    2,     1,  1)
+MUX_CFG("N20_1610_GPIO11",       6,   18,    0,   1,   4,   0,    1,     1,  1)
 MUX_CFG("N19_1610_GPIO13",       6,   12,    0,   1,   2,   0,    1,     1,  1)
 MUX_CFG("P10_1610_GPIO22",       C,    0,    7,   2,  26,   0,    2,     1,  1)
 MUX_CFG("V5_1610_GPIO24",        B,   15,    7,   2,  21,   0,    2,     1,  1)
 MUX_CFG("AA20_1610_GPIO_41",     9,    9,    7,   1,  31,   0,    1,     1,  1)
 MUX_CFG("W19_1610_GPIO48",       8,   15,    7,   1,  23,   1,    1,     0,  1)
 MUX_CFG("M7_1610_GPIO62",       10,    0,    0,   4,  24,   0,    4,     0,  1)
+MUX_CFG("V14_16XX_GPIO37",       9,   18,    7,   2,   2,   0,    2,     2,  0)
+MUX_CFG("R9_16XX_GPIO18",        C,   18,    7,   3,   0,   0,    3,     0,  0)
+MUX_CFG("L14_16XX_GPIO49",       6,    3,    7,   0,  31,   0,    0,    31,  0)
 /* OMAP-1610 uWire */
 MUX_CFG("V19_1610_UWIRE_SCLK",   8,    6,    0,   1,  20,   0,    1,     1,  1)
@@ -503,16 +516,17 @@ MUX_CFG("Y10_USB0_SUSP",	 B,   3,     5,	  2,  17,   0,	  2,	 0,  1)
 MUX_CFG("W9_USB2_TXEN",          B,   9,     1,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("AA9_USB2_VP",           B,   6,     1,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("Y5_USB2_RCV",           C,  21,     1,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("R8_USB2_VM",            C,  18,     1,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("R9_USB2_VM",            C,  18,     1,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("V6_USB2_TXD",           C,  27,     2,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("W5_USB2_SE0",           C,  24,     2,  NA,   0,   0,   NA,     0,  1)
+/* 16XX UART */
-/* UART1 */
 MUX_CFG("R13_1610_UART1_TX",     A,  12,     6,   2,  10,   0,    2,    10,  1)
-MUX_CFG("V14_1610_UART1_RX",     9,  18,     0,   2,   2,   0,    2,     2,  1)
+MUX_CFG("V14_16XX_UART1_RX",     9,  18,     0,   2,   2,   0,    2,     2,  1)
 MUX_CFG("R14_1610_UART1_CTS",    9,  15,     0,   2,   1,   0,    2,     1,  1)
 MUX_CFG("AA15_1610_UART1_RTS",   9,  12,     1,   2,   0,   0,    2,     0,  1)
+MUX_CFG("R9_16XX_UART2_RX",      C,  18,     0,   3,   0,   0,    3,     0,  1)
+MUX_CFG("L14_16XX_UART3_RX",     6,   3,     0,   0,  31,   0,    0,    31,  1)
 /* I2C interface */
 MUX_CFG("I2C_SCL",               7,  24,     0,  NA,   0,   0,   NA,     0,  0)
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
index f491a48ef2e1..f086a3933906 100644
--- a/include/asm-arm/arch-omap/omap1510.h
+++ b/include/asm-arm/arch-omap/omap1510.h
@@ -36,10 +36,6 @@
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-#define OMAP1510_SRAM_BASE      0xD0000000
-#define OMAP1510_SRAM_SIZE      (SZ_128K + SZ_64K)
-#define OMAP1510_SRAM_START     0x20000000
 #define OMAP1510_DSP_BASE       0xE0000000
 #define OMAP1510_DSP_SIZE       0x28000
 #define OMAP1510_DSP_START      0xE0000000
@@ -48,14 +44,5 @@
 #define OMAP1510_DSPREG_SIZE    SZ_128K
 #define OMAP1510_DSPREG_START   0xE1000000
-/*
- * ----------------------------------------------------------------------------
- * Memory used by power management
- * ----------------------------------------------------------------------------
- */
-#define OMAP1510_SRAM_IDLE_SUSPEND      (OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - 0x200)
-#define OMAP1510_SRAM_API_SUSPEND       (OMAP1510_SRAM_IDLE_SUSPEND + 0x100)
 #endif /*  __ASM_ARCH_OMAP1510_H */
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
index 88b1fe43ae9e..f0c7f0fb4dc0 100644
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -36,11 +36,6 @@
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-#define OMAP16XX_SRAM_BASE      0xD0000000
-#define OMAP1610_SRAM_SIZE      (SZ_16K)
-#define OMAP5912_SRAM_SIZE      0x3E800
-#define OMAP16XX_SRAM_START     0x20000000
 #define OMAP16XX_DSP_BASE       0xE0000000
 #define OMAP16XX_DSP_SIZE       0x28000
 #define OMAP16XX_DSP_START      0xE0000000
@@ -50,17 +45,6 @@
 #define OMAP16XX_DSPREG_START   0xE1000000
 /*
- * ----------------------------------------------------------------------------
- * Memory used by power management
- * ----------------------------------------------------------------------------
- */
-#define OMAP1610_SRAM_IDLE_SUSPEND      (OMAP16XX_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200)
-#define OMAP1610_SRAM_API_SUSPEND       (OMAP1610_SRAM_IDLE_SUSPEND + 0x100)
-#define OMAP5912_SRAM_IDLE_SUSPEND      (OMAP16XX_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200)
-#define OMAP5912_SRAM_API_SUSPEND       (OMAP5912_SRAM_IDLE_SUSPEND + 0x100)
-/*
 * ---------------------------------------------------------------------------
 * Interrupts
 * ---------------------------------------------------------------------------
@@ -183,5 +167,37 @@
 #define OMAP16XX_PWL_ENABLE     (OMAP16XX_PWL_BASE + 0x00)
 #define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+/* 32-bit Watchdog timer in OMAP 16XX */
+#define OMAP_16XX_WATCHDOG_BASE        (0xfffeb000)
+#define OMAP_16XX_WIDR         (OMAP_16XX_WATCHDOG_BASE + 0x00)
+#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
+#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
+#define OMAP_16XX_WCLR         (OMAP_16XX_WATCHDOG_BASE + 0x24)
+#define OMAP_16XX_WCRR         (OMAP_16XX_WATCHDOG_BASE + 0x28)
+#define OMAP_16XX_WLDR         (OMAP_16XX_WATCHDOG_BASE + 0x2c)
+#define OMAP_16XX_WTGR         (OMAP_16XX_WATCHDOG_BASE + 0x30)
+#define OMAP_16XX_WWPS         (OMAP_16XX_WATCHDOG_BASE + 0x34)
+#define OMAP_16XX_WSPR         (OMAP_16XX_WATCHDOG_BASE + 0x48)
+#define WCLR_PRE_SHIFT         5
+#define WCLR_PTV_SHIFT         2
+#define WWPS_W_PEND_WSPR       (1 << 4)
+#define WWPS_W_PEND_WTGR       (1 << 3)
+#define WWPS_W_PEND_WLDR       (1 << 2)
+#define WWPS_W_PEND_WCRR       (1 << 1)
+#define WWPS_W_PEND_WCLR       (1 << 0)
+#define WSPR_ENABLE_0          (0x0000bbbb)
+#define WSPR_ENABLE_1          (0x00004444)
+#define WSPR_DISABLE_0         (0x0000aaaa)
+#define WSPR_DISABLE_1         (0x00005555)
 #endif /*  __ASM_ARCH_OMAP16XX_H */
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
new file mode 100644
index 000000000000..a9105466a417
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_ARCH_OMAP24XX_H
+#define __ASM_ARCH_OMAP24XX_H
+#define OMAP24XX_L4_IO_BASE     0x48000000
+/* interrupt controller */
+#define OMAP24XX_IC_BASE        (OMAP24XX_L4_IO_BASE + 0xfe000)
+#define VA_IC_BASE              IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP24XX_IVA_INTC_BASE  0x40000000
+#define IRQ_SIR_IRQ             0x0040
+#endif /* __ASM_ARCH_OMAP24XX_H */
diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h
index 599ab00f5488..755b64c5e9f0 100644
--- a/include/asm-arm/arch-omap/omap730.h
+++ b/include/asm-arm/arch-omap/omap730.h
@@ -36,10 +36,6 @@
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-#define OMAP730_SRAM_BASE       0xD0000000
-#define OMAP730_SRAM_SIZE       (SZ_128K + SZ_64K + SZ_8K)
-#define OMAP730_SRAM_START      0x20000000
 #define OMAP730_DSP_BASE        0xE0000000
 #define OMAP730_DSP_SIZE        0x50000
 #define OMAP730_DSP_START       0xE0000000
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
index f209fc0953fb..fbd742d0c499 100644
--- a/include/asm-arm/arch-omap/pm.h
+++ b/include/asm-arm/arch-omap/pm.h
@@ -61,7 +61,10 @@
 #define PER_EN                          0x1
 #define CPU_SUSPEND_SIZE                200
-#define ULPD_LOW_POWER_EN               0x0001
+#define ULPD_LOW_PWR_EN                 0x0001
+#define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
+#define ULPD_SETUP_ANALOG_CELL_3_VAL    0
+#define ULPD_POWER_CTRL_REG_VAL         0x0219
 #define DSP_IDLE_DELAY                  10
 #define DSP_IDLE                        0x0040
@@ -86,46 +89,35 @@
 #define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
 #define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
 #define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
-#define OMAP1510_ULPD_LOW_POWER_REQ     0x0001
-#define OMAP1610_DEEP_SLEEP_REQUEST     0x17c7
+/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
-#define OMAP1610_BIG_SLEEP_REQUEST      TBD
+#define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
+#define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
+#define OMAP1610_IDLECT3_VAL            0x3f
+#define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
+#define OMAP1610_IDLECT3                0xfffece24
 #define OMAP1610_IDLE_LOOP_REQUEST      0x0400
-#define OMAP1610_IDLE_CLOCK_DOMAINS     0x09c7
-#define OMAP1610_ULPD_LOW_POWER_REQ     0x3
-#ifndef OMAP1510_SRAM_IDLE_SUSPEND
-#define OMAP1510_SRAM_IDLE_SUSPEND 0
-#endif
-#ifndef OMAP1610_SRAM_IDLE_SUSPEND
-#define OMAP1610_SRAM_IDLE_SUSPEND 0
-#endif
-#ifndef OMAP5912_SRAM_IDLE_SUSPEND
-#define OMAP5912_SRAM_IDLE_SUSPEND 0
-#endif
-#ifndef OMAP1510_SRAM_API_SUSPEND
-#define OMAP1510_SRAM_API_SUSPEND 0
-#endif
-#ifndef OMAP1610_SRAM_API_SUSPEND
-#define OMAP1610_SRAM_API_SUSPEND 0
-#endif
-#ifndef OMAP5912_SRAM_API_SUSPEND
-#define OMAP5912_SRAM_API_SUSPEND 0
-#endif
 #if     !defined(CONFIG_ARCH_OMAP1510) && \
-        !defined(CONFIG_ARCH_OMAP16XX)
+        !defined(CONFIG_ARCH_OMAP16XX) && \
+        !defined(CONFIG_ARCH_OMAP24XX)
 #error "Power management for this processor not implemented yet"
 #endif
 #ifndef __ASSEMBLER__
 extern void omap_pm_idle(void);
 extern void omap_pm_suspend(void);
-extern int omap1510_cpu_suspend(unsigned short, unsigned short);
+extern void omap1510_cpu_suspend(unsigned short, unsigned short);
-extern int omap1610_cpu_suspend(unsigned short, unsigned short);
+extern void omap1610_cpu_suspend(unsigned short, unsigned short);
-extern int omap1510_idle_loop_suspend(void);
+extern void omap1510_idle_loop_suspend(void);
-extern int omap1610_idle_loop_suspend(void);
+extern void omap1610_idle_loop_suspend(void);
+#ifdef CONFIG_OMAP_SERIAL_WAKE
+extern void omap_serial_wake_trigger(int enable);
+#else
+#define omap_serial_wake_trigger(x)     {}
+#endif  /* CONFIG_OMAP_SERIAL_WAKE */
 extern unsigned int omap1510_cpu_suspend_sz;
 extern unsigned int omap1510_idle_loop_suspend_sz;
 extern unsigned int omap1610_cpu_suspend_sz;
@@ -161,6 +153,7 @@ enum arm_save_state {
        ARM_SLEEP_SAVE_ARM_CKCTL,
        ARM_SLEEP_SAVE_ARM_IDLECT1,
        ARM_SLEEP_SAVE_ARM_IDLECT2,
+        ARM_SLEEP_SAVE_ARM_IDLECT3,
        ARM_SLEEP_SAVE_ARM_EWUPCT,
        ARM_SLEEP_SAVE_ARM_RSTCT1,
        ARM_SLEEP_SAVE_ARM_RSTCT2,
diff --git a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h
new file mode 100644
index 000000000000..79a5297af9fc
--- /dev/null
+++ b/include/asm-arm/arch-omap/serial.h
@@ -0,0 +1,37 @@
+/*
+ *  linux/include/asm-arm/arch-omap/serial.h
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+#if defined(CONFIG_ARCH_OMAP1)
+/* OMAP1 serial ports */
+#define OMAP_UART1_BASE         0xfffb0000
+#define OMAP_UART2_BASE         0xfffb0800
+#define OMAP_UART3_BASE         0xfffb9800
+#elif defined(CONFIG_ARCH_OMAP2)
+/* OMAP2 serial ports */
+#define OMAP_UART1_BASE         0x4806a000
+#define OMAP_UART2_BASE         0x4806c000
+#define OMAP_UART3_BASE         0x4806e000
+#endif
+#define OMAP_MAX_NR_PORTS       3
+#define OMAP1510_BASE_BAUD      (12000000/16)
+#define OMAP16XX_BASE_BAUD      (48000000/16)
+#define is_omap_port(p) ({int __ret = 0;                        \
+                        if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART2_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART3_BASE))   \
+                                __ret = 1;                      \
+                        __ret;                                  \
+                        })
+#endif
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index 17a2c4825f07..ff37bc27e603 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -5,7 +5,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 #include <linux/config.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
+#include <asm/mach-types.h>
 static inline void arch_idle(void)
 {
@@ -14,7 +16,24 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode)
 {
-        omap_writew(1, ARM_RSTCT1);
+#ifdef CONFIG_ARCH_OMAP16XX
+        /*
+         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+         * "Global Software Reset Affects Traffic Controller Frequency".
+         */
+        if (cpu_is_omap5912()) {
+                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
+                                 DPLL_CTL);
+                omap_writew(0x8, ARM_RSTCT1);
+        }
+#endif
+#ifdef CONFIG_MACH_VOICEBLUE
+        if (machine_is_voiceblue())
+                voiceblue_reset();
+        else
+#endif
+                omap_writew(1, ARM_RSTCT1);
 }
 #endif
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h
index 0f97bb2e8fce..b9aa2b3a3909 100644
--- a/include/asm-arm/arch-omap/tps65010.h
+++ b/include/asm-arm/arch-omap/tps65010.h
@@ -30,6 +30,66 @@
 /*
 * ----------------------------------------------------------------------------
+ * Registers, all 8 bits
+ * ----------------------------------------------------------------------------
+ */
+#define TPS_CHGSTATUS           0x01
+#       define  TPS_CHG_USB             (1 << 7)
+#       define  TPS_CHG_AC              (1 << 6)
+#       define  TPS_CHG_THERM           (1 << 5)
+#       define  TPS_CHG_TERM            (1 << 4)
+#       define  TPS_CHG_TAPER_TMO       (1 << 3)
+#       define  TPS_CHG_CHG_TMO         (1 << 2)
+#       define  TPS_CHG_PRECHG_TMO      (1 << 1)
+#       define  TPS_CHG_TEMP_ERR        (1 << 0)
+#define TPS_REGSTATUS           0x02
+#       define  TPS_REG_ONOFF           (1 << 7)
+#       define  TPS_REG_COVER           (1 << 6)
+#       define  TPS_REG_UVLO            (1 << 5)
+#       define  TPS_REG_NO_CHG          (1 << 4)        /* tps65013 */
+#       define  TPS_REG_PG_LD02         (1 << 3)
+#       define  TPS_REG_PG_LD01         (1 << 2)
+#       define  TPS_REG_PG_MAIN         (1 << 1)
+#       define  TPS_REG_PG_CORE         (1 << 0)
+#define TPS_MASK1               0x03
+#define TPS_MASK2               0x04
+#define TPS_ACKINT1             0x05
+#define TPS_ACKINT2             0x06
+#define TPS_CHGCONFIG           0x07
+#       define  TPS_CHARGE_POR          (1 << 7)        /* 65010/65012 */
+#       define  TPS65013_AUA            (1 << 7)        /* 65011/65013 */
+#       define  TPS_CHARGE_RESET        (1 << 6)
+#       define  TPS_CHARGE_FAST         (1 << 5)
+#       define  TPS_CHARGE_CURRENT      (3 << 3)
+#       define  TPS_VBUS_500MA          (1 << 2)
+#       define  TPS_VBUS_CHARGING       (1 << 1)
+#       define  TPS_CHARGE_ENABLE       (1 << 0)
+#define TPS_LED1_ON             0x08
+#define TPS_LED1_PER            0x09
+#define TPS_LED2_ON             0x0a
+#define TPS_LED2_PER            0x0b
+#define TPS_VDCDC1              0x0c
+#       define  TPS_ENABLE_LP           (1 << 3)
+#define TPS_VDCDC2              0x0d
+#define TPS_VREGS1              0x0e
+#       define  TPS_LDO2_ENABLE (1 << 7)
+#       define  TPS_LDO2_OFF    (1 << 6)
+#       define  TPS_VLDO2_3_0V  (3 << 4)
+#       define  TPS_VLDO2_2_75V (2 << 4)
+#       define  TPS_VLDO2_2_5V  (1 << 4)
+#       define  TPS_VLDO2_1_8V  (0 << 4)
+#       define  TPS_LDO1_ENABLE (1 << 3)
+#       define  TPS_LDO1_OFF    (1 << 2)
+#       define  TPS_VLDO1_3_0V  (3 << 0)
+#       define  TPS_VLDO1_2_75V (2 << 0)
+#       define  TPS_VLDO1_2_5V  (1 << 0)
+#       define  TPS_VLDO1_ADJ   (0 << 0)
+#define TPS_MASK3               0x0f
+#define TPS_DEFGPIO             0x10
+/*
+ * ----------------------------------------------------------------------------
 * Macros used by exported functions
 * ----------------------------------------------------------------------------
 */
@@ -71,10 +131,26 @@ extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
 */
 extern int tps65010_set_led(unsigned led, unsigned mode);
+/* tps65010_set_vib parameter:
+ * value: ON or OFF
+ */
+extern int tps65010_set_vib(unsigned value);
 /* tps65010_set_low_pwr parameter:
 * mode: ON or OFF
 */
 extern int tps65010_set_low_pwr(unsigned mode);
+/* tps65010_config_vregs1 parameter:
+ * value to be written to VREGS1 register
+ * Note: The complete register is written, set all bits you need
+ */
+extern int tps65010_config_vregs1(unsigned value);
+/* tps65013_set_low_pwr parameter:
+ * mode: ON or OFF
+ */
+extern int tps65013_set_low_pwr(unsigned mode);
 #endif /*  __ASM_ARCH_TPS65010_H */
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
index 3e640aba8c20..3545c86859cc 100644
--- a/include/asm-arm/arch-omap/uncompress.h
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -20,7 +20,7 @@
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/serial.h>
 unsigned int system_rev;
@@ -34,8 +34,9 @@ static void
 putstr(const char *s)
 {
        volatile u8 * uart = 0;
-        int shift;
+        int shift = 2;
+#ifdef CONFIG_ARCH_OMAP
 #ifdef  CONFIG_OMAP_LL_DEBUG_UART3
        uart = (volatile u8 *)(OMAP_UART3_BASE);
 #elif   CONFIG_OMAP_LL_DEBUG_UART2
@@ -44,6 +45,7 @@ putstr(const char *s)
        uart = (volatile u8 *)(OMAP_UART1_BASE);
 #endif
+#ifdef CONFIG_ARCH_OMAP1
        /* Determine which serial port to use */
        do {
                /* MMU is not on, so cpu_is_omapXXXX() won't work here */
@@ -51,14 +53,14 @@ putstr(const char *s)
                if (omap_id == OMAP_ID_730)
                        shift = 0;
-                else
-                        shift = 2;
                if (check_port(uart, shift))
                        break;
                /* Silent boot if no serial ports are enabled. */
                return;
        } while (0);
+#endif /* CONFIG_ARCH_OMAP1 */
+#endif
        /*
         * Now, xmit each character
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 1438c6cef0ca..054fb9a8e0c6 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -47,6 +47,15 @@
 #       define   HMC_TLLATTACH          (1 << 6)
 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
 #define OTG_CTRL_REG                    OTG_REG32(0x0c)
+#       define   OTG_USB2_EN            (1 << 29)
+#       define   OTG_USB2_DP            (1 << 28)
+#       define   OTG_USB2_DM            (1 << 27)
+#       define   OTG_USB1_EN            (1 << 26)
+#       define   OTG_USB1_DP            (1 << 25)
+#       define   OTG_USB1_DM            (1 << 24)
+#       define   OTG_USB0_EN            (1 << 23)
+#       define   OTG_USB0_DP            (1 << 22)
+#       define   OTG_USB0_DM            (1 << 21)
 #       define   OTG_ASESSVLD           (1 << 20)
 #       define   OTG_BSESSEND           (1 << 19)
 #       define   OTG_BSESSVLD           (1 << 18)
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
index 324db06b5dd4..4b7aa0b8391e 100644
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -103,18 +103,20 @@
 * Shared data structures
 */
 extern struct platform_device corgiscoop_device;
+extern struct platform_device corgissp_device;
+extern struct platform_device corgifb_device;
 /*
 * External Functions
 */
 extern unsigned long corgi_ssp_ads7846_putget(unsigned long);
 extern unsigned long corgi_ssp_ads7846_get(void);
-extern void corgi_ssp_ads7846_put(ulong data);
+extern void corgi_ssp_ads7846_put(unsigned long data);
 extern void corgi_ssp_ads7846_lock(void);
 extern void corgi_ssp_ads7846_unlock(void);
-extern void corgi_ssp_lcdtg_send (u8 adrs, u8 data);
+extern void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data);
 extern void corgi_ssp_blduty_set(int duty);
-extern int corgi_ssp_max1111_get(ulong data);
+extern int corgi_ssp_max1111_get(unsigned long data);
 #endif /* __ASM_ARCH_CORGI_H  */
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
index f288e74b67c2..b6ec68879176 100644
--- a/include/asm-arm/arch-pxa/debug-macro.S
+++ b/include/asm-arm/arch-pxa/debug-macro.S
@@ -11,6 +11,8 @@
 *
 */
+#include "hardware.h"
                .macro  addruart,rx
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 72b04d846a23..cf35721cfa45 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -44,24 +44,12 @@
 #ifndef __ASSEMBLY__
-#if 0
+# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
-#else
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)       __REGP(io_p2v(x))
-#endif
 /* With indexed regs we don't want to feed the index through io_p2v()
   especially if it is a variable, otherwise horrible code will result. */
-# define __REG2(x,y)     (*(volatile u32 *)((u32)&__REG(x) + (y)))
+# define __REG2(x,y)    \
+        (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
 # define __PREG(x)      (io_v2p((u32)&(x)))
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index 7492ea7ea614..88c17dd02ed2 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -9,7 +9,9 @@ struct mmc_host;
 struct pxamci_platform_data {
        unsigned int ocr_mask;                  /* available voltages */
+        unsigned long detect_delay;             /* delay in jiffies before detecting cards after interrupt */
        int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *);
+        int (*get_ro)(struct device *);
        void (*setpower)(struct device *, unsigned int);
        void (*exit)(struct device *, void *);
 };
diff --git a/include/asm-arm/arch-pxa/mtd-xip.h b/include/asm-arm/arch-pxa/mtd-xip.h
new file mode 100644
index 000000000000..8704dbceb432
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mtd-xip.h
@@ -0,0 +1,37 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ * 
+ * Author:      Nicolas Pitre
+ * Created:     Nov 2, 2004
+ * Copyright:   (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
+ */
+#ifndef __ARCH_PXA_MTD_XIP_H__
+#define __ARCH_PXA_MTD_XIP_H__
+#include <asm/arch/pxa-regs.h>
+#define xip_irqpending()        (ICIP & ICMR)
+/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
+#define xip_currtime()          (OSCR)
+#define xip_elapsed_since(x)    (signed)((OSCR - (x)) / 4)
+/*
+ * xip_cpu_idle() is used when waiting for a delay equal or larger than
+ * the system timer tick period.  This should put the CPU into idle mode
+ * to save power and to be woken up only when some interrupts are pending.
+ * As above, this should not rely upon standard kernel code.
+ */
+#define xip_cpu_idle()  asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
+#endif /* __ARCH_PXA_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index b5e54a9e9fa7..939d9e5020a0 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -818,6 +818,23 @@
 #define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
                                           Interrupt Enable */
+#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
+#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
+#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
+#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
+#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
+#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
+#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
+#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
+#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
+#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
+#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
+#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
+#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
+#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
+#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
 #define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
 #define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
 #define UDCCSR0_SA      (1 << 7)        /* Setup Active */
@@ -1423,6 +1440,7 @@
 #define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
 #define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
 #define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
 #define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
@@ -1505,10 +1523,13 @@
 #define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
 #define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
 #define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
+#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
 #define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
 #define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
 #define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
+#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
 #define PCFR_RO         (1 << 15)       /* RDH Override */
 #define PCFR_PO         (1 << 14)       /* PH Override */
 #define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
@@ -1516,6 +1537,7 @@
 #define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
 #define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
 #define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
 #define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
 #define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
 #define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
@@ -1809,6 +1831,11 @@
 #define LCCR0_PDD_S     12
 #define LCCR0_BM        (1 << 20)       /* Branch mask */
 #define LCCR0_OUM       (1 << 21)       /* Output FIFO underrun mask */
+#define LCCR0_LCDT      (1 << 22)       /* LCD panel type */
+#define LCCR0_RDSTM     (1 << 23)       /* Read status interrupt mask */
+#define LCCR0_CMDIM     (1 << 24)       /* Command interrupt mask */
+#define LCCR0_OUC       (1 << 25)       /* Overlay Underlay control bit */
+#define LCCR0_LDDALT    (1 << 26)       /* LDD alternate mapping control */
 #define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
 #define LCCR1_DisWdth(Pixel)            /* Display Width [1..800 pix.]  */ \
@@ -1965,6 +1992,7 @@
 #define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
 #define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
+#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
 #define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
 #define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
 #define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
@@ -2060,7 +2088,10 @@
 #define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
 #define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
 #define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
 #define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
 #define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
 #define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
 #define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
diff --git a/include/asm-arm/arch-s3c2410/anubis-cpld.h b/include/asm-arm/arch-s3c2410/anubis-cpld.h
new file mode 100644
index 000000000000..5675b1796b55
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/anubis-cpld.h
@@ -0,0 +1,24 @@
+/* linux/include/asm-arm/arch-s3c2410/anubis-cpld.h
+ *
+ * (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *
+*/
+#ifndef __ASM_ARCH_ANUBISCPLD_H
+#define __ASM_ARCH_ANUBISCPLD_H
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+#define ANUBIS_CTRL1_NANDSEL            (0x3)
+#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/anubis-irq.h b/include/asm-arm/arch-s3c2410/anubis-irq.h
new file mode 100644
index 000000000000..82f15dbd97e8
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/anubis-irq.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-s3c2410/anubis-irq.h
+ *
+ * (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *  ANUBIS - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ */
+#ifndef __ASM_ARCH_ANUBISIRQ_H
+#define __ASM_ARCH_ANUBISIRQ_H
+#define IRQ_IDE0       IRQ_EINT2
+#define IRQ_IDE1       IRQ_EINT3
+#define IRQ_ASIX       IRQ_EINT1
+#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
new file mode 100644
index 000000000000..97741d6e506a
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/anubis-map.h
@@ -0,0 +1,46 @@
+/* linux/include/asm-arm/arch-s3c2410/anubis-map.h
+ *
+ * (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+*/
+/* needs arch/map.h including with this */
+#ifndef __ASM_ARCH_ANUBISMAP_H
+#define __ASM_ARCH_ANUBISMAP_H
+/* start peripherals off after the S3C2410 */
+#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x02000000))
+#define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
+/* we put the CPLD registers next, to get them out of the way */
+#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01300000 */
+#define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
+#define ANUBIS_VA_CTRL2     ANUBIS_IOADDR(0x00100000)    /* 0x01400000 */
+#define ANUBIS_PA_CTRL2     (ANUBIS_PA_CPLD)
+#define ANUBIS_VA_CTRL3     ANUBIS_IOADDR(0x00200000)    /* 0x01500000 */
+#define ANUBIS_PA_CTRL3     (ANUBIS_PA_CPLD)
+#define ANUBIS_VA_CTRL4     ANUBIS_IOADDR(0x00300000)    /* 0x01600000 */
+#define ANUBIS_PA_CTRL4     (ANUBIS_PA_CPLD)
+#define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
+#define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
+#define ANUBIS_IDESEC       ANUBIS_IOADDR(0x01200000)
+#define ANUBIS_IDESECAUX    ANUBIS_IOADDR(0x01300000)
+#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/audio.h b/include/asm-arm/arch-s3c2410/audio.h
new file mode 100644
index 000000000000..0d276e67f2fb
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/audio.h
@@ -0,0 +1,49 @@
+/* linux/include/asm-arm/arch-s3c2410/audio.h
+ *
+ * (c) 2004-2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/SWLINUX/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Audio platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *      20-Nov-2004 BJD  Created file
+ *      07-Mar-2005 BJD  Added suspend/resume calls
+*/
+#ifndef __ASM_ARCH_AUDIO_H
+#define __ASM_ARCH_AUDIO_H __FILE__
+/* struct s3c24xx_iis_ops
+ *
+ * called from the s3c24xx audio core to deal with the architecture
+ * or the codec's setup and control.
+ *
+ * the pointer to itself is passed through in case the caller wants to
+ * embed this in an larger structure for easy reference to it's context.
+*/
+struct s3c24xx_iis_ops {
+        struct module *owner;
+        int     (*startup)(struct s3c24xx_iis_ops *me);
+        void    (*shutdown)(struct s3c24xx_iis_ops *me);
+        int     (*suspend)(struct s3c24xx_iis_ops *me);
+        int     (*resume)(struct s3c24xx_iis_ops *me);
+        int     (*open)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
+        int     (*close)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
+        int     (*prepare)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm, snd_pcm_runtime_t *rt);
+};
+struct s3c24xx_platdata_iis {
+        const char              *codec_clk;
+        struct s3c24xx_iis_ops  *ops;
+        int                     (*match_dev)(struct device *dev);
+};
+#endif /* __ASM_ARCH_AUDIO_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e5e938b79acc..16f4c3cc1388 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -1,7 +1,7 @@
 /* linux/include/asm/arch-s3c2410/regs-clock.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
+ *                    http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -17,6 +17,7 @@
 *    29-Sep-2004 Ben Dooks         Fixed usage for assembly inclusion
 *    10-Feb-2005 Ben Dooks         Fixed CAMDIVN address (Guillaume Gourat)
 *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA
+ *    27-Aug-2005 Ben Dooks         Add clock-slow info
 */
 #ifndef __ASM_ARM_REGS_CLOCK
@@ -74,6 +75,12 @@
 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
+#define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
+#define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
+#define S3C2410_CLKSLOW_SLOW            (1<<4)
+#define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
+#define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
 #ifndef __ASSEMBLY__
 static inline unsigned int
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index 385b07d510da..fdd62e8cd6cb 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -15,6 +15,9 @@
 *    12-03-2004     BJD     Updated include protection
 *    07-03-2005     BJD     Added FIFO size flags and S3C2440 MPLL
 *    05-04-2005     LCVR    Added IISFCON definitions for the S3C2400
+ *    18-07-2005     DA      Change IISCON_MPLL to IISMOD_MPLL
+ *                           Correct IISMOD_256FS and IISMOD_384FS
+ *                           Add IISCON_PSCEN
 */
 #ifndef __ASM_ARCH_REGS_IIS_H
@@ -22,7 +25,6 @@
 #define S3C2410_IISCON   (0x00)
-#define S3C2440_IISCON_MPLL       (1<<9)
 #define S3C2410_IISCON_LRINDEX    (1<<8)
 #define S3C2410_IISCON_TXFIFORDY  (1<<7)
 #define S3C2410_IISCON_RXFIFORDY  (1<<6)
@@ -30,10 +32,12 @@
 #define S3C2410_IISCON_RXDMAEN    (1<<4)
 #define S3C2410_IISCON_TXIDLE     (1<<3)
 #define S3C2410_IISCON_RXIDLE     (1<<2)
+#define S3C2410_IISCON_PSCEN      (1<<1)
 #define S3C2410_IISCON_IISEN      (1<<0)
 #define S3C2410_IISMOD   (0x04)
+#define S3C2440_IISMOD_MPLL       (1<<9)
 #define S3C2410_IISMOD_SLAVE      (1<<8)
 #define S3C2410_IISMOD_NOXFER     (0<<6)
 #define S3C2410_IISMOD_RXMODE     (1<<6)
@@ -46,8 +50,8 @@
 #define S3C2410_IISMOD_8BIT       (0<<3)
 #define S3C2410_IISMOD_16BIT      (1<<3)
 #define S3C2410_IISMOD_BITMASK    (1<<3)
-#define S3C2410_IISMOD_256FS      (0<<1)
+#define S3C2410_IISMOD_256FS      (0<<2)
-#define S3C2410_IISMOD_384FS      (1<<1)
+#define S3C2410_IISMOD_384FS      (1<<2)
 #define S3C2410_IISMOD_16FS       (0<<0)
 #define S3C2410_IISMOD_32FS       (1<<0)
 #define S3C2410_IISMOD_48FS       (2<<0)
diff --git a/include/asm-arm/arch-s3c2410/usb-control.h b/include/asm-arm/arch-s3c2410/usb-control.h
index 1cc85a096b23..bd43b566db3e 100644
--- a/include/asm-arm/arch-s3c2410/usb-control.h
+++ b/include/asm-arm/arch-s3c2410/usb-control.h
@@ -12,6 +12,7 @@
 * Changelog:
 *  11-Sep-2004 BJD  Created file
 *  21-Sep-2004 BJD  Updated port info
+ *  09-Aug-2005 BJD  Renamed s3c2410_report_oc s3c2410_usb_report_oc
 */
 #ifndef __ASM_ARCH_USBCONTROL_H
@@ -35,7 +36,7 @@ struct s3c2410_hcd_info {
        void            (*report_oc)(struct s3c2410_hcd_info *, int ports);
 };
-static void inline s3c2410_report_oc(struct s3c2410_hcd_info *info, int ports)
+static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
 {
        if (info->report_oc != NULL) {
                (info->report_oc)(info, ports);
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index 10c62db34362..19c3b1e186bb 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -49,23 +49,9 @@
   ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 #ifndef __ASSEMBLY__
-#include <asm/types.h>
-#if 0
+# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
+# define __PREG(x)      (io_v2p((unsigned long)&(x)))
-#else
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)       __REGP(io_p2v(x))
-#endif
-# define __PREG(x)      (io_v2p((u32)&(x)))
 #else
diff --git a/include/asm-arm/arch-sa1100/mcp.h b/include/asm-arm/arch-sa1100/mcp.h
new file mode 100644
index 000000000000..f58a22755c61
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/mcp.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-sa1100/mcp.h
+ *
+ *  Copyright (C) 2005 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_ARCH_MCP_H
+#define __ASM_ARM_ARCH_MCP_H
+#include <linux/types.h>
+struct mcp_plat_data {
+        u32 mccr0;
+        u32 mccr1;
+        unsigned int sclk_rate;
+};
+#endif
diff --git a/include/asm-arm/arch-sa1100/mtd-xip.h b/include/asm-arm/arch-sa1100/mtd-xip.h
new file mode 100644
index 000000000000..80cfdac2b944
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/mtd-xip.h
@@ -0,0 +1,26 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ * 
+ * Author:      Nicolas Pitre
+ * Created:     Nov 2, 2004
+ * Copyright:   (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
+ */
+#ifndef __ARCH_SA1100_MTD_XIP_H__
+#define __ARCH_SA1100_MTD_XIP_H__
+#define xip_irqpending()        (ICIP & ICMR)
+/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
+#define xip_currtime()          (OSCR)
+#define xip_elapsed_since(x)    (signed)((OSCR - (x)) / 4)
+#endif /* __ARCH_SA1100_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
index 1e7f26bc2e1d..5e6ed0038b2b 100644
--- a/include/asm-arm/arch-shark/io.h
+++ b/include/asm-arm/arch-shark/io.h
@@ -21,38 +21,8 @@
 */
 #define __PORT_PCIO(x)  (!((x) & 0x80000000))
-/*
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
- * Dynamic IO functions - let the compiler
- * optimize the expressions
- */
-#define DECLARE_DYN_OUT(fnsuffix,instr)                                         \
-static inline void __out##fnsuffix (unsigned int value, unsigned int port)      \
-{                                                                               \
-        unsigned long temp;                                                     \
-        __asm__ __volatile__(                                                   \
-        "tst    %2, #0x80000000\n\t"                                            \
-        "mov    %0, %4\n\t"                                                     \
-        "addeq  %0, %0, %3\n\t"                                                 \
-        "str" instr "   %1, [%0, %2]    @ out" #fnsuffix                        \
-        : "=&r" (temp)                                                          \
-        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)   \
-        : "cc");                                                                \
-}
-#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
-static inline unsigned sz __in##fnsuffix (unsigned int port)            \
-{                                                                               \
-        unsigned long temp, value;                                              \
-        __asm__ __volatile__(                                                   \
-        "tst    %2, #0x80000000\n\t"                                            \
-        "mov    %0, %4\n\t"                                                     \
-        "addeq  %0, %0, %3\n\t"                                                 \
-        "ldr" instr "   %1, [%0, %2]    @ in" #fnsuffix                         \
-        : "=&r" (temp), "=r" (value)                                            \
-        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
-        : "cc");                                                                \
-        return (unsigned sz)value;                                              \
-}
 static inline unsigned int __ioaddr (unsigned int port)                 \
 {                                                                               \
@@ -62,123 +32,8 @@ static inline unsigned int __ioaddr (unsigned int port)			\
                return (unsigned int)(IO_BASE + (port));                        \
 }
-#define DECLARE_IO(sz,fnsuffix,instr)   \
-        DECLARE_DYN_OUT(fnsuffix,instr) \
-        DECLARE_DYN_IN(sz,fnsuffix,instr)
-DECLARE_IO(char,b,"b")
-DECLARE_IO(short,w,"h")
-DECLARE_IO(long,l,"")
-#undef DECLARE_IO
-#undef DECLARE_DYN_OUT
-#undef DECLARE_DYN_IN
-/*
- * Constant address IO functions
- *
- * These have to be macros for the 'J' constraint to work -
- * +/-4096 immediate operand.
- */
-#define __outbc(value,port)                                                     \
-({                                                                              \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]            @ outbc"                        \
-                : : "r" (value), "r" (PCIO_BASE), "Jr" (port));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]            @ outbc"                        \
-                : : "r" (value), "r" (IO_BASE), "r" (port));            \
-})
-#define __inbc(port)                                                            \
-({                                                                              \
-        unsigned char result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]            @ inbc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]            @ inbc"                         \
-                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
-        result;                                                                 \
-})
-#define __outwc(value,port)                                                     \
-({                                                                              \
-        unsigned long v = value;                                                \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "strh   %0, [%1, %2]            @ outwc"                        \
-                : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" (port));       \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "strh   %0, [%1, %2]            @ outwc"                        \
-                : : "r" (v|v<<16), "r" (IO_BASE), "r" (port));          \
-})
-#define __inwc(port)                                                            \
-({                                                                              \
-        unsigned short result;                                                  \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldrh   %0, [%1, %2]            @ inwc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldrh   %0, [%1, %2]            @ inwc"                         \
-                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
-        result & 0xffff;                                                        \
-})
-#define __outlc(value,port)                                                             \
-({                                                                              \
-        unsigned long v = value;                                                \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]            @ outlc"                        \
-                : : "r" (v), "r" (PCIO_BASE), "Jr" (port));             \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]            @ outlc"                        \
-                : : "r" (v), "r" (IO_BASE), "r" (port));                        \
-})
-#define __inlc(port)                                                            \
-({                                                                              \
-        unsigned long result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]            @ inlc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]            @ inlc"                         \
-                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
-        result;                                                                 \
-})
-#define __ioaddrc(port)                                                         \
-({                                                                              \
-        unsigned long addr;                                                     \
-        if (__PORT_PCIO((port)))                                                \
-                addr = PCIO_BASE + (port);                              \
-        else                                                                    \
-                addr = IO_BASE + (port);                                        \
-        addr;                                                                   \
-})
 #define __mem_pci(addr) (addr)
-#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
-#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
-#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
-#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
-#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
-#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
 /*
 * Translated address IO functions
 *
diff --git a/include/asm-arm/arch-versatile/hardware.h b/include/asm-arm/arch-versatile/hardware.h
index d5fb4a251e7f..41c1bee342ad 100644
--- a/include/asm-arm/arch-versatile/hardware.h
+++ b/include/asm-arm/arch-versatile/hardware.h
@@ -25,19 +25,26 @@
 #include <asm/sizes.h>
 #include <asm/arch/platform.h>
-// FIXME = PCI settings need to be fixed!!!!!
 /*
- * Similar to above, but for PCI addresses (memory, IO, Config and the
+ * PCI space virtual addresses
- * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
 */
-#define PCI_MEMORY_VADDR       0xe8000000
+#define VERSATILE_PCI_VIRT_BASE         0xe8000000
-#define PCI_CONFIG_VADDR       0xec000000
+#define VERSATILE_PCI_CFG_VIRT_BASE     0xe9000000
-#define PCI_V3_VADDR           0xed000000
-#define PCI_IO_VADDR           0xee000000
+#if 0
+#define VERSATILE_PCI_VIRT_MEM_BASE0    0xf4000000
+#define VERSATILE_PCI_VIRT_MEM_BASE1    0xf5000000
+#define VERSATILE_PCI_VIRT_MEM_BASE2    0xf6000000
+#define PCIO_BASE                       VERSATILE_PCI_VIRT_MEM_BASE0
+#define PCIMEM_BASE                     VERSATILE_PCI_VIRT_MEM_BASE1
+#endif
+/* CIK guesswork */
+#define PCIBIOS_MIN_IO                  0x44000000
+#define PCIBIOS_MIN_MEM                 0x50000000
-#define PCIO_BASE               PCI_IO_VADDR
+#define pcibios_assign_all_busses()     1
-#define PCIMEM_BASE             PCI_MEMORY_VADDR
 /* macro to get at IO space when running virtually */
 #define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h
index dbb7158788fc..9f895bf61494 100644
--- a/include/asm-arm/arch-versatile/io.h
+++ b/include/asm-arm/arch-versatile/io.h
@@ -20,7 +20,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffff
+#define IO_SPACE_LIMIT 0xffffffff
 #define __io(a)                 ((void __iomem *)(a))
 #define __mem_pci(a)            (a)
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h
index 2598d1f08548..cbdd9fb96332 100644
--- a/include/asm-arm/arch-versatile/platform.h
+++ b/include/asm-arm/arch-versatile/platform.h
@@ -76,7 +76,7 @@
 #define VERSATILE_SYS_NVFLAGSSET_OFFSET       0x38
 #define VERSATILE_SYS_NVFLAGSCLR_OFFSET       0x3C
 #define VERSATILE_SYS_RESETCTL_OFFSET         0x40
-#define VERSATILE_SYS_PICCTL_OFFSET           0x44
+#define VERSATILE_SYS_PCICTL_OFFSET           0x44
 #define VERSATILE_SYS_MCI_OFFSET              0x48
 #define VERSATILE_SYS_FLASH_OFFSET            0x4C
 #define VERSATILE_SYS_CLCD_OFFSET             0x50
@@ -114,7 +114,7 @@
 #define VERSATILE_SYS_NVFLAGSSET              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
 #define VERSATILE_SYS_NVFLAGSCLR              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
 #define VERSATILE_SYS_RESETCTL                (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
-#define VERSATILE_SYS_PICCTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PICCTL_OFFSET)
+#define VERSATILE_SYS_PCICTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
 #define VERSATILE_SYS_MCI                     (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
 #define VERSATILE_SYS_FLASH                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
 #define VERSATILE_SYS_CLCD                    (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
@@ -225,7 +225,20 @@
 #define VERSATILE_SSMC_BASE            0x20000000       /* SSMC */
 #define VERSATILE_IB2_BASE             0x24000000       /* IB2 module */
 #define VERSATILE_MBX_BASE             0x40000000       /* MBX */
+/* PCI space */
 #define VERSATILE_PCI_BASE             0x41000000       /* PCI Interface */
+#define VERSATILE_PCI_CFG_BASE         0x42000000
+#define VERSATILE_PCI_MEM_BASE0        0x44000000
+#define VERSATILE_PCI_MEM_BASE1        0x50000000
+#define VERSATILE_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define VERSATILE_PCI_BASE_SIZE        0x01000000
+#define VERSATILE_PCI_CFG_BASE_SIZE    0x02000000
+#define VERSATILE_PCI_MEM_BASE0_SIZE   0x0c000000       /* 32Mb */
+#define VERSATILE_PCI_MEM_BASE1_SIZE   0x10000000       /* 256Mb */
+#define VERSATILE_PCI_MEM_BASE2_SIZE   0x10000000       /* 256Mb */
 #define VERSATILE_SDRAM67_BASE         0x70000000       /* SDRAM banks 6 and 7 */
 #define VERSATILE_LT_BASE              0x80000000       /* Logic Tile expansion */
@@ -498,11 +511,17 @@
 /*
 * IB2 Versatile/AB expansion board definitions
 */
-#define VERSATILE_IB2_CAMERA_BANK       0x24000000
+#define VERSATILE_IB2_CAMERA_BANK       VERSATILE_IB2_BASE
-#define VERSATILE_IB2_KBD_DATAREG       0x25000000
+#define VERSATILE_IB2_KBD_DATAREG       (VERSATILE_IB2_BASE + 0x01000000)
-#define VERSATILE_IB2_IER               0x26000000      /* for VICINTSOURCE27 */
-#define VERSATILE_IB2_CTRL              0x27000000
+/* VICINTSOURCE27 */
-#define VERSATILE_IB2_STAT              0x27000004
+#define VERSATILE_IB2_INT_BASE          (VERSATILE_IB2_BASE + 0x02000000)
+#define VERSATILE_IB2_IER               (VERSATILE_IB2_INT_BASE + 0)
+#define VERSATILE_IB2_ISR               (VERSATILE_IB2_INT_BASE + 4)
+#define VERSATILE_IB2_CTL_BASE          (VERSATILE_IB2_BASE + 0x03000000)
+#define VERSATILE_IB2_CTRL              (VERSATILE_IB2_CTL_BASE + 0)
+#define VERSATILE_IB2_STAT              (VERSATILE_IB2_CTL_BASE + 4)
 #endif
 #endif
diff --git a/include/asm-arm/auxvec.h b/include/asm-arm/auxvec.h
new file mode 100644
index 000000000000..c0536f6b29a7
--- /dev/null
+++ b/include/asm-arm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMARM_AUXVEC_H
+#define __ASMARM_AUXVEC_H
+#endif
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 4edd4dc40c5b..aad7aad026b3 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -21,8 +21,8 @@
 #include <asm/system.h>
-#define smp_mb__before_clear_bit()      do { } while (0)
+#define smp_mb__before_clear_bit()      mb()
-#define smp_mb__after_clear_bit()       do { } while (0)
+#define smp_mb__after_clear_bit()       mb()
 /*
 * These functions are the basis of our bit ops.
@@ -229,6 +229,7 @@ extern int _find_next_zero_bit_be(const void * p, int size, int offset);
 extern int _find_first_bit_be(const unsigned long *p, unsigned size);
 extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
+#ifndef CONFIG_SMP
 /*
 * The __* form of bitops are non-atomic and may be reordered.
 */
@@ -241,6 +242,10 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
        (__builtin_constant_p(nr) ?             \
         ____atomic_##name(nr, p) :             \
         _##name##_be(nr,p))
+#else
+#define ATOMIC_BITOP_LE(name,nr,p)      _##name##_le(nr,p)
+#define ATOMIC_BITOP_BE(name,nr,p)      _##name##_be(nr,p)
+#endif
 #define NONATOMIC_BITOP(name,nr,p)              \
        (____nonatomic_##name(nr, p))
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index 24d11672eb60..7fb02138f585 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -5,7 +5,7 @@
 #ifdef CONFIG_BUG
 #ifdef CONFIG_DEBUG_BUGVERBOSE
-extern volatile void __bug(const char *file, int line, void *data);
+extern void __bug(const char *file, int line, void *data) __attribute__((noreturn));
 /* give file/line information */
 #define BUG()           __bug(__FILE__, __LINE__, NULL)
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 09ffeed507c2..e81baff4f54b 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -16,6 +16,9 @@
 #include <asm/mman.h>
 #include <asm/glue.h>
+#include <asm/shmparam.h>
+#define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 /*
 *      Cache Model
@@ -253,7 +256,7 @@ extern void dmac_flush_range(unsigned long, unsigned long);
 * Convert calls to our calling convention.
 */
 #define flush_cache_all()               __cpuc_flush_kern_all()
+#ifndef CONFIG_CPU_CACHE_VIPT
 static inline void flush_cache_mm(struct mm_struct *mm)
 {
        if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
@@ -276,6 +279,11 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned l
                __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
        }
 }
+#else
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
+#endif
 /*
 * flush_cache_user_range is used when we want to ensure that the
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
index ff48022e4720..4679f63688e9 100644
--- a/include/asm-arm/cpu-multi32.h
+++ b/include/asm-arm/cpu-multi32.h
@@ -31,7 +31,7 @@ extern struct processor {
        /*
         * Special stuff for a reset
         */
-        volatile void (*reset)(unsigned long addr);
+        void (*reset)(unsigned long addr) __attribute__((noreturn));
        /*
         * Idle the processor
         */
diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h
index b5ec5d54665d..6723e67244fa 100644
--- a/include/asm-arm/cpu-single.h
+++ b/include/asm-arm/cpu-single.h
@@ -41,4 +41,4 @@ extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_set_pte(pte_t *ptep, pte_t pte);
-extern volatile void cpu_reset(unsigned long addr);
+extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
diff --git a/include/asm-arm/emergency-restart.h b/include/asm-arm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-arm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+#include <asm-generic/emergency-restart.h>
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-arm/fcntl.h b/include/asm-arm/fcntl.h
index 485b6bdf4d7a..a80b6607b2ef 100644
--- a/include/asm-arm/fcntl.h
+++ b/include/asm-arm/fcntl.h
@@ -1,87 +1,11 @@
 #ifndef _ARM_FCNTL_H
 #define _ARM_FCNTL_H
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
 #define O_DIRECTORY      040000 /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
 #define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
 #define O_LARGEFILE     0400000
-#define O_NOATIME       01000000
-#define F_DUPFD         0       /* dup */
+#include <asm-generic/fcntl.h>
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-/* for leases */
-#define F_INPROGRESS    16
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-#define F_LINUX_SPECIFIC_BASE   1024
 #endif
diff --git a/include/asm-arm/futex.h b/include/asm-arm/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-arm/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+#ifdef __KERNEL__
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+        inc_preempt_count();
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+        dec_preempt_count();
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+#endif
+#endif
diff --git a/include/asm-arm/hardware/arm_timer.h b/include/asm-arm/hardware/arm_timer.h
new file mode 100644
index 000000000000..04be3bdf46b8
--- /dev/null
+++ b/include/asm-arm/hardware/arm_timer.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
+#define __ASM_ARM_HARDWARE_ARM_TIMER_H
+#define TIMER_LOAD      0x00
+#define TIMER_VALUE     0x04
+#define TIMER_CTRL      0x08
+#define TIMER_CTRL_ONESHOT      (1 << 0)
+#define TIMER_CTRL_32BIT        (1 << 1)
+#define TIMER_CTRL_DIV1         (0 << 2)
+#define TIMER_CTRL_DIV16        (1 << 2)
+#define TIMER_CTRL_DIV256       (2 << 2)
+#define TIMER_CTRL_IE           (1 << 5)        /* Interrupt Enable (versatile only) */
+#define TIMER_CTRL_PERIODIC     (1 << 6)
+#define TIMER_CTRL_ENABLE       (1 << 7)
+#define TIMER_INTCLR    0x0c
+#define TIMER_RIS       0x10
+#define TIMER_MIS       0x14
+#define TIMER_BGLOAD    0x18
+#endif
diff --git a/include/asm-arm/hardware/gic.h b/include/asm-arm/hardware/gic.h
new file mode 100644
index 000000000000..3fa5eb70f64e
--- /dev/null
+++ b/include/asm-arm/hardware/gic.h
@@ -0,0 +1,41 @@
+/*
+ *  linux/include/asm-arm/hardware/gic.h
+ *
+ *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_HARDWARE_GIC_H
+#define __ASM_ARM_HARDWARE_GIC_H
+#include <linux/compiler.h>
+#define GIC_CPU_CTRL                    0x00
+#define GIC_CPU_PRIMASK                 0x04
+#define GIC_CPU_BINPOINT                0x08
+#define GIC_CPU_INTACK                  0x0c
+#define GIC_CPU_EOI                     0x10
+#define GIC_CPU_RUNNINGPRI              0x14
+#define GIC_CPU_HIGHPRI                 0x18
+#define GIC_DIST_CTRL                   0x000
+#define GIC_DIST_CTR                    0x004
+#define GIC_DIST_ENABLE_SET             0x100
+#define GIC_DIST_ENABLE_CLEAR           0x180
+#define GIC_DIST_PENDING_SET            0x200
+#define GIC_DIST_PENDING_CLEAR          0x280
+#define GIC_DIST_ACTIVE_BIT             0x300
+#define GIC_DIST_PRI                    0x400
+#define GIC_DIST_TARGET                 0x800
+#define GIC_DIST_CONFIG                 0xc00
+#define GIC_DIST_SOFTINT                0xf00
+#ifndef __ASSEMBLY__
+void gic_dist_init(void __iomem *base);
+void gic_cpu_init(void __iomem *base);
+void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
+#endif
+#endif
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
index 7ea771ff6144..527404b5a8df 100644
--- a/include/asm-arm/hardware/scoop.h
+++ b/include/asm-arm/hardware/scoop.h
@@ -40,6 +40,19 @@ struct scoop_config {
        unsigned short io_dir;
 };
+/* Structure for linking scoop devices to PCMCIA sockets */
+struct scoop_pcmcia_dev {
+        struct device *dev;     /* Pointer to this socket's scoop device */
+        int     irq;                /* irq for socket */
+        int cd_irq;
+        const char *cd_irq_str;
+        unsigned char keep_vs;
+        unsigned char keep_rd;
+};
+extern int scoop_num;
+extern struct scoop_pcmcia_dev *scoop_devs;
 void reset_scoop(struct device *dev);
 unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
 unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
diff --git a/include/asm-arm/hdreg.h b/include/asm-arm/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-arm/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h
index 2114acb3d237..4f68c8a5a199 100644
--- a/include/asm-arm/ide.h
+++ b/include/asm-arm/ide.h
@@ -5,7 +5,7 @@
 */
 /*
- *  This file contains the i386 architecture specific IDE code.
+ *  This file contains the ARM architecture specific IDE code.
 */
 #ifndef __ASMARM_IDE_H
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 658ffa384fda..cfa71a0dffb6 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -82,7 +82,7 @@ extern void __readwrite_bug(const char *fn);
 * only.  Their primary purpose is to access PCI and ISA peripherals.
 *
 * Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerious
+ * big endian mode connectivity is in place, as described by numerous
 * ARM documents:
 *
 *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
@@ -273,6 +273,35 @@ extern void __iounmap(void __iomem *addr);
 #endif
 /*
+ * io{read,write}{8,16,32} macros
+ */
+#ifndef ioread8
+#define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __v; })
+#define ioread16(p)     ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
+#define ioread32(p)     ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
+#define iowrite8(v,p)   __raw_writeb(v, p)
+#define iowrite16(v,p)  __raw_writew(cpu_to_le16(v), p)
+#define iowrite32(v,p)  __raw_writel(cpu_to_le32(v), p)
+#define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
+#define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
+#define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
+#define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
+#define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
+#define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *addr);
+#endif
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
+/*
 * can the hardware map this into one segment or not, given no other
 * constraints.
 */
diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h
index c26298f3891f..f08dc8447913 100644
--- a/include/asm-arm/locks.h
+++ b/include/asm-arm/locks.h
@@ -28,7 +28,8 @@
 "       blmi    " #fail                         \
        :                                       \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
        })
 #define __down_op_ret(ptr,fail)                 \
@@ -48,12 +49,14 @@
 "       mov     %0, ip"                         \
        : "=&r" (ret)                           \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
        ret;                                    \
        })
 #define __up_op(ptr,wake)                       \
        ({                                      \
+        smp_mb();                               \
        __asm__ __volatile__(                   \
        "@ up_op\n"                             \
 "1:     ldrex   lr, [%0]\n"                     \
@@ -61,12 +64,12 @@
 "       strex   ip, lr, [%0]\n"                 \
 "       teq     ip, #0\n"                       \
 "       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
+"       cmp     lr, #0\n"                       \
 "       movle   ip, %0\n"                       \
 "       blle    " #wake                         \
        :                                       \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
        })
 /*
@@ -92,15 +95,17 @@
 "       blne    " #fail                         \
        :                                       \
        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
        })
 #define __up_op_write(ptr,wake)                 \
        ({                                      \
+        smp_mb();                               \
        __asm__ __volatile__(                   \
        "@ up_op_read\n"                        \
 "1:     ldrex   lr, [%0]\n"                     \
-"       add     lr, lr, %1\n"                   \
+"       adds    lr, lr, %1\n"                   \
 "       strex   ip, lr, [%0]\n"                 \
 "       teq     ip, #0\n"                       \
 "       bne     1b\n"                           \
@@ -108,7 +113,7 @@
 "       blcs    " #wake                         \
        :                                       \
        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
        })
 #define __down_op_read(ptr,fail)                \
@@ -116,6 +121,7 @@
 #define __up_op_read(ptr,wake)                  \
        ({                                      \
+        smp_mb();                               \
        __asm__ __volatile__(                   \
        "@ up_op_read\n"                        \
 "1:     ldrex   lr, [%0]\n"                     \
@@ -128,7 +134,7 @@
 "       bleq    " #wake                         \
        :                                       \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
        })
 #else
@@ -148,7 +154,8 @@
 "       blmi    " #fail                         \
        :                                       \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
        })
 #define __down_op_ret(ptr,fail)                 \
@@ -169,12 +176,14 @@
 "       mov     %0, ip"                         \
        : "=&r" (ret)                           \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
        ret;                                    \
        })
 #define __up_op(ptr,wake)                       \
        ({                                      \
+        smp_mb();                               \
        __asm__ __volatile__(                   \
        "@ up_op\n"                             \
 "       mrs     ip, cpsr\n"                     \
@@ -188,7 +197,7 @@
 "       blle    " #wake                         \
        :                                       \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
        })
 /*
@@ -215,7 +224,8 @@
 "       blne    " #fail                         \
        :                                       \
        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
        })
 #define __up_op_write(ptr,wake)                 \
@@ -233,7 +243,8 @@
 "       blcs    " #wake                         \
        :                                       \
        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
        })
 #define __down_op_read(ptr,fail)                \
@@ -241,6 +252,7 @@
 #define __up_op_read(ptr,wake)                  \
        ({                                      \
+        smp_mb();                               \
        __asm__ __volatile__(                   \
        "@ up_op_read\n"                        \
 "       mrs     ip, cpsr\n"                     \
@@ -254,7 +266,7 @@
 "       bleq    " #wake                         \
        :                                       \
        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
        })
 #endif
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index 3a32e929ec8c..56c6bf4ab0c3 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -26,7 +26,7 @@ struct machine_desc {
                                                 * page tabe entry      */
        const char              *name;          /* architecture name    */
-        unsigned int            param_offset;   /* parameter page       */
+        unsigned long           boot_params;    /* tagged list          */
        unsigned int            video_start;    /* start of video RAM   */
        unsigned int            video_end;      /* end of video RAM     */
@@ -54,38 +54,6 @@ const struct machine_desc __mach_desc_##_type	\
        .nr             = MACH_TYPE_##_type,    \
        .name           = _name,
-#define MAINTAINER(n)
-#define BOOT_MEM(_pram,_pio,_vio)               \
-        .phys_ram       = _pram,                \
-        .phys_io        = _pio,                 \
-        .io_pg_offst    = ((_vio)>>18)&0xfffc,
-#define BOOT_PARAMS(_params)                    \
-        .param_offset   = _params,
-#define VIDEO(_start,_end)                      \
-        .video_start    = _start,               \
-        .video_end      = _end,
-#define DISABLE_PARPORT(_n)                     \
-        .reserve_lp##_n = 1,
-#define SOFT_REBOOT                             \
-        .soft_reboot    = 1,
-#define FIXUP(_func)                            \
-        .fixup          = _func,
-#define MAPIO(_func)                            \
-        .map_io         = _func,
-#define INITIRQ(_func)                          \
-        .init_irq       = _func,
-#define INIT_MACHINE(_func)                     \
-        .init_machine   = _func,
 #define MACHINE_END                             \
 };
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
index a43a353f6c7b..0ce6ca588d8c 100644
--- a/include/asm-arm/mach/irq.h
+++ b/include/asm-arm/mach/irq.h
@@ -42,11 +42,11 @@ struct irqchip {
        /*
         * Set the type of the IRQ.
         */
-        int (*type)(unsigned int, unsigned int);
+        int (*set_type)(unsigned int, unsigned int);
        /*
         * Set wakeup-enable on the selected IRQ
         */
-        int (*wake)(unsigned int, unsigned int);
+        int (*set_wake)(unsigned int, unsigned int);
 #ifdef CONFIG_SMP
        /*
@@ -92,6 +92,14 @@ struct irqdesc {
 extern struct irqdesc irq_desc[];
 /*
+ * Helpful inline function for calling irq descriptor handlers.
+ */
+static inline void desc_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+        desc->handle(irq, desc, regs);
+}
+/*
 * This is internal.  Do not use it.
 */
 extern void (*init_arch_irq)(void);
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5cf4fd659fd5..96c6db7dd0e1 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -39,8 +39,29 @@ struct sys_timer {
        void                    (*suspend)(void);
        void                    (*resume)(void);
        unsigned long           (*offset)(void);
+#ifdef CONFIG_NO_IDLE_HZ
+        struct dyn_tick_timer   *dyn_tick;
+#endif
+};
+#ifdef CONFIG_NO_IDLE_HZ
+#define DYN_TICK_ENABLED        (1 << 1)
+struct dyn_tick_timer {
+        unsigned int    state;                  /* Current state */
+        int             (*enable)(void);        /* Enables dynamic tick */
+        int             (*disable)(void);       /* Disables dynamic tick */
+        void            (*reprogram)(unsigned long); /* Reprograms the timer */
+        int             (*handler)(int, void *, struct pt_regs *);
 };
+void timer_dyn_reprogram(void);
+#else
+#define timer_dyn_reprogram()   do { } while (0)
+#endif
 extern struct sys_timer *system_timer;
 extern void timer_tick(struct pt_regs *);
diff --git a/include/asm-arm/mtd-xip.h b/include/asm-arm/mtd-xip.h
new file mode 100644
index 000000000000..9eb127cc7db2
--- /dev/null
+++ b/include/asm-arm/mtd-xip.h
@@ -0,0 +1,26 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ * 
+ * Author:      Nicolas Pitre
+ * Created:     Nov 2, 2004
+ * Copyright:   (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
+ */
+#ifndef __ARM_MTD_XIP_H__
+#define __ARM_MTD_XIP_H__
+#include <asm/hardware.h>
+#include <asm/arch/mtd-xip.h>
+/* fill instruction prefetch */
+#define xip_iprefetch()         do { asm volatile (".rep 8; nop; .endr"); } while (0)
+#endif /* __ARM_MTD_XIP_H__ */
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 019c45d75730..4da1d532cbeb 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -163,20 +163,6 @@ typedef unsigned long pgprot_t;
 /* the upper-most page table pointer */
 extern pmd_t *top_pmd;
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size)
-{
-        int order;
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
 #include <asm/memory.h>
 #endif /* !__ASSEMBLY__ */
@@ -186,4 +172,6 @@ static inline int get_order(unsigned long size)
 #endif /* __KERNEL__ */
+#include <asm-generic/page.h>
 #endif
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index 40ffaefbeb1a..38ea5899a580 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -14,7 +14,7 @@ static inline void pcibios_set_master(struct pci_dev *dev)
        /* No special bus mastering setup handling */
 }
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
        /* We don't do dynamic PCI IRQ allocation */
 }
@@ -42,6 +42,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
 #define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
 #define HAVE_PCI_MMAP
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                               enum pci_mmap_state mmap_state, int write_combine);
@@ -50,6 +60,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
                         struct resource *res);
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                        struct pci_bus_region *region);
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h
index e814f8144f8b..bc18ff405181 100644
--- a/include/asm-arm/pgalloc.h
+++ b/include/asm-arm/pgalloc.h
@@ -89,6 +89,13 @@ static inline void pte_free(struct page *pte)
        __free_page(pte);
 }
+static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval)
+{
+        pmdp[0] = __pmd(pmdval);
+        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
+        flush_pmd_entry(pmdp);
+}
 /*
 * Populate the pmdp entry with a pointer to the pte.  This pmd is part
 * of the mm address space.
@@ -99,32 +106,19 @@ static inline void
 pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
 {
        unsigned long pte_ptr = (unsigned long)ptep;
-        unsigned long pmdval;
-        BUG_ON(mm != &init_mm);
        /*
         * The pmd must be loaded with the physical
         * address of the PTE table
         */
        pte_ptr -= PTRS_PER_PTE * sizeof(void *);
-        pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE;
+        __pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE);
-        pmdp[0] = __pmd(pmdval);
-        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
-        flush_pmd_entry(pmdp);
 }
 static inline void
 pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
 {
-        unsigned long pmdval;
+        __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE);
-        BUG_ON(mm == &init_mm);
-        pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE;
-        pmdp[0] = __pmd(pmdval);
-        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
-        flush_pmd_entry(pmdp);
 }
 #endif
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index a9892eb42a23..478c49b56e18 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -188,12 +188,18 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 /*
 *   - extended small page/tiny page
 */
+#define PTE_EXT_XN              (1 << 0)        /* v6 */
 #define PTE_EXT_AP_MASK         (3 << 4)
+#define PTE_EXT_AP0             (1 << 4)
+#define PTE_EXT_AP1             (2 << 4)
 #define PTE_EXT_AP_UNO_SRO      (0 << 4)
-#define PTE_EXT_AP_UNO_SRW      (1 << 4)
+#define PTE_EXT_AP_UNO_SRW      (PTE_EXT_AP0)
-#define PTE_EXT_AP_URO_SRW      (2 << 4)
+#define PTE_EXT_AP_URO_SRW      (PTE_EXT_AP1)
-#define PTE_EXT_AP_URW_SRW      (3 << 4)
+#define PTE_EXT_AP_URW_SRW      (PTE_EXT_AP1|PTE_EXT_AP0)
 #define PTE_EXT_TEX(x)          ((x) << 6)      /* v5 */
+#define PTE_EXT_APX             (1 << 9)        /* v6 */
+#define PTE_EXT_SHARED          (1 << 10)       /* v6 */
+#define PTE_EXT_NG              (1 << 11)       /* v6 */
 /*
 *   - small page
@@ -224,6 +230,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define L_PTE_WRITE             (1 << 5)
 #define L_PTE_EXEC              (1 << 6)
 #define L_PTE_DIRTY             (1 << 7)
+#define L_PTE_SHARED            (1 << 10)       /* shared between CPUs (v6) */
+#define L_PTE_ASID              (1 << 11)       /* non-global (use ASID, v6) */
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h
index 46e69ae395af..760f6e65af05 100644
--- a/include/asm-arm/signal.h
+++ b/include/asm-arm/signal.h
@@ -114,6 +114,7 @@ typedef unsigned long sigset_t;
 #define SIGSTKSZ        8192
 #ifdef __KERNEL__
+#define SA_TIMER                0x40000000
 #define SA_IRQNOMASK            0x08000000
 #endif
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index f21fd8f6bcdd..dbb4d859c586 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -21,10 +21,7 @@
 # error "<asm-arm/smp.h> included in non-SMP build"
 #endif
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id() (current_thread_info()->cpu)
-extern cpumask_t cpu_present_mask;
-#define cpu_possible_map cpu_present_mask
 /*
 * at the moment, there's not a big penalty for changing CPUs
@@ -55,4 +52,18 @@ extern void smp_cross_call(cpumask_t callmap);
 */
 extern int boot_secondary(unsigned int cpu, struct task_struct *);
+/*
+ * Perform platform specific initialisation of the specified CPU.
+ */
+extern void platform_secondary_init(unsigned int cpu);
+/*
+ * Initial data for bringing up a secondary CPU.
+ */
+struct secondary_data {
+        unsigned long pgdir;
+        void *stack;
+};
+extern struct secondary_data secondary_data;
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/include/asm-arm/socket.h b/include/asm-arm/socket.h
index 46d20585d951..3c51da6438c9 100644
--- a/include/asm-arm/socket.h
+++ b/include/asm-arm/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index 182323619caa..1f906d09b688 100644
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -8,9 +8,10 @@
 /*
 * ARMv6 Spin-locking.
 *
- * We (exclusively) read the old value, and decrement it.  If it
+ * We exclusively read the old value.  If it is zero, we may have
- * hits zero, we may have won the lock, so we try (exclusively)
+ * won the lock, so we try exclusively storing it.  A memory barrier
- * storing it.
+ * is required after we get a lock, and before we release it, because
+ * V6 CPUs are assumed to have weakly ordered memory.
 *
 * Unlocked value: 0
 * Locked value: 1
@@ -41,7 +42,9 @@ static inline void _raw_spin_lock(spinlock_t *lock)
 "       bne     1b"
        : "=&r" (tmp)
        : "r" (&lock->lock), "r" (1)
-        : "cc", "memory");
+        : "cc");
+        smp_mb();
 }
 static inline int _raw_spin_trylock(spinlock_t *lock)
@@ -54,18 +57,25 @@ static inline int _raw_spin_trylock(spinlock_t *lock)
 "       strexeq %0, %2, [%1]"
        : "=&r" (tmp)
        : "r" (&lock->lock), "r" (1)
-        : "cc", "memory");
+        : "cc");
-        return tmp == 0;
+        if (tmp == 0) {
+                smp_mb();
+                return 1;
+        } else {
+                return 0;
+        }
 }
 static inline void _raw_spin_unlock(spinlock_t *lock)
 {
+        smp_mb();
        __asm__ __volatile__(
 "       str     %1, [%0]"
        :
        : "r" (&lock->lock), "r" (0)
-        : "cc", "memory");
+        : "cc");
 }
 /*
@@ -79,7 +89,8 @@ typedef struct {
 } rwlock_t;
 #define RW_LOCK_UNLOCKED        (rwlock_t) { 0 }
-#define rwlock_init(x)          do { *(x) + RW_LOCK_UNLOCKED; } while (0)
+#define rwlock_init(x)          do { *(x) = RW_LOCK_UNLOCKED; } while (0)
+#define rwlock_is_locked(x)     (*((volatile unsigned int *)(x)) != 0)
 /*
 * Write locks are easy - we just set bit 31.  When unlocking, we can
@@ -97,16 +108,40 @@ static inline void _raw_write_lock(rwlock_t *rw)
 "       bne     1b"
        : "=&r" (tmp)
        : "r" (&rw->lock), "r" (0x80000000)
-        : "cc", "memory");
+        : "cc");
+        smp_mb();
+}
+static inline int _raw_write_trylock(rwlock_t *rw)
+{
+        unsigned long tmp;
+        __asm__ __volatile__(
+"1:     ldrex   %0, [%1]\n"
+"       teq     %0, #0\n"
+"       strexeq %0, %2, [%1]"
+        : "=&r" (tmp)
+        : "r" (&rw->lock), "r" (0x80000000)
+        : "cc");
+        if (tmp == 0) {
+                smp_mb();
+                return 1;
+        } else {
+                return 0;
+        }
 }
 static inline void _raw_write_unlock(rwlock_t *rw)
 {
+        smp_mb();
        __asm__ __volatile__(
        "str    %1, [%0]"
        :
        : "r" (&rw->lock), "r" (0)
-        : "cc", "memory");
+        : "cc");
 }
 /*
@@ -133,11 +168,17 @@ static inline void _raw_read_lock(rwlock_t *rw)
 "       bmi     1b"
        : "=&r" (tmp), "=&r" (tmp2)
        : "r" (&rw->lock)
-        : "cc", "memory");
+        : "cc");
+        smp_mb();
 }
 static inline void _raw_read_unlock(rwlock_t *rw)
 {
+        unsigned long tmp, tmp2;
+        smp_mb();
        __asm__ __volatile__(
 "1:     ldrex   %0, [%2]\n"
 "       sub     %0, %0, #1\n"
@@ -146,24 +187,9 @@ static inline void _raw_read_unlock(rwlock_t *rw)
 "       bne     1b"
        : "=&r" (tmp), "=&r" (tmp2)
        : "r" (&rw->lock)
-        : "cc", "memory");
+        : "cc");
 }
 #define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
-static inline int _raw_write_trylock(rwlock_t *rw)
-{
-        unsigned long tmp;
-        __asm__ __volatile__(
-"1:     ldrex   %0, [%1]\n"
-"       teq     %0, #0\n"
-"       strexeq %0, %2, [%1]"
-        : "=&r" (tmp)
-        : "r" (&rw->lock), "r" (0x80000000)
-        : "cc", "memory");
-        return tmp == 0;
-}
 #endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-arm/stat.h b/include/asm-arm/stat.h
index ca8e7a8436da..ec4e2c2e3b47 100644
--- a/include/asm-arm/stat.h
+++ b/include/asm-arm/stat.h
@@ -89,6 +89,6 @@ struct stat64 {
        unsigned long   st_ctime_nsec;
        unsigned long long      st_ino;
-};
+} __attribute__((packed));
 #endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index b13a8da4847b..8efa4ebdcacb 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -85,7 +85,9 @@ struct pt_regs;
 void die(const char *msg, struct pt_regs *regs, int err)
                __attribute__((noreturn));
-void die_if_kernel(const char *str, struct pt_regs *regs, int err);
+struct siginfo;
+void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
+                unsigned long err, unsigned long trap);
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                       struct pt_regs *),
@@ -104,6 +106,7 @@ extern void show_pte(struct mm_struct *mm, unsigned long addr);
 extern void __show_regs(struct pt_regs *);
 extern int cpu_architecture(void);
+extern void cpu_init(void);
 #define set_cr(x)                                       \
        __asm__ __volatile__(                           \
@@ -136,7 +139,12 @@ extern unsigned int user_debug;
 #define vectors_high()  (0)
 #endif
+#if __LINUX_ARM_ARCH__ >= 6
+#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+                                   : : "r" (0) : "memory")
+#else
 #define mb() __asm__ __volatile__ ("" : : : "memory")
+#endif
 #define rmb() mb()
 #define wmb() mb()
 #define read_barrier_depends() do { } while(0)
@@ -144,34 +152,12 @@ extern unsigned int user_debug;
 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-#ifdef CONFIG_SMP
-/*
- * Define our own context switch locking.  This allows us to enable
- * interrupts over the context switch, otherwise we end up with high
- * interrupt latency.  The real problem area is switch_mm() which may
- * do a full cache flush.
- */
-#define prepare_arch_switch(rq,next)                                    \
-do {                                                                    \
-        spin_lock(&(next)->switch_lock);                                \
-        spin_unlock_irq(&(rq)->lock);                                   \
-} while (0)
-#define finish_arch_switch(rq,prev)                                     \
-        spin_unlock(&(prev)->switch_lock)
-#define task_running(rq,p)                                              \
-        ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
-#else
 /*
- * Our UP-case is more simple, but we assume knowledge of how
+ * switch_mm() may do a full cache flush over the context switch,
- * spin_unlock_irq() and friends are implemented.  This avoids
+ * so enable interrupts over the context switch to avoid high
- * us needlessly decrementing and incrementing the preempt count.
+ * latency.
 */
-#define prepare_arch_switch(rq,next)    local_irq_enable()
+#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
-#define finish_arch_switch(rq,prev)     spin_unlock(&(rq)->lock)
-#define task_running(rq,p)              ((rq)->curr == (p))
-#endif
 /*
 * switch_to(prev, next) should switch from task `prev' to `next'
@@ -307,11 +293,10 @@ do {									\
 ({                                      \
        unsigned long flags;            \
        local_save_flags(flags);        \
-        flags & PSR_I_BIT;              \
+        (int)(flags & PSR_I_BIT);       \
 })
 #ifdef CONFIG_SMP
-#error SMP not supported
 #define smp_mb()                mb()
 #define smp_rmb()               rmb()
@@ -325,6 +310,8 @@ do {									\
 #define smp_wmb()               barrier()
 #define smp_read_barrier_depends()              do { } while(0)
+#endif /* CONFIG_SMP */
 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 /*
 * On the StrongARM, "swp" is terminally broken since it bypasses the
@@ -337,6 +324,9 @@ do {									\
 *
 * We choose (1) since its the "easiest" to achieve here and is not
 * dependent on the processor type.
+ *
+ * NOTE that this solution won't work on an SMP system, so explcitly
+ * forbid it here.
 */
 #define swp_is_buggy
 #endif
@@ -348,42 +338,73 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 #ifdef swp_is_buggy
        unsigned long flags;
 #endif
+#if __LINUX_ARM_ARCH__ >= 6
+        unsigned int tmp;
+#endif
        switch (size) {
-#ifdef swp_is_buggy
+#if __LINUX_ARM_ARCH__ >= 6
-                case 1:
+        case 1:
-                        local_irq_save(flags);
+                asm volatile("@ __xchg1\n"
-                        ret = *(volatile unsigned char *)ptr;
+                "1:     ldrexb  %0, [%3]\n"
-                        *(volatile unsigned char *)ptr = x;
+                "       strexb  %1, %2, [%3]\n"
-                        local_irq_restore(flags);
+                "       teq     %1, #0\n"
-                        break;
+                "       bne     1b"
+                        : "=&r" (ret), "=&r" (tmp)
-                case 4:
+                        : "r" (x), "r" (ptr)
-                        local_irq_save(flags);
+                        : "memory", "cc");
-                        ret = *(volatile unsigned long *)ptr;
+                break;
-                        *(volatile unsigned long *)ptr = x;
+        case 4:
-                        local_irq_restore(flags);
+                asm volatile("@ __xchg4\n"
-                        break;
+                "1:     ldrex   %0, [%3]\n"
+                "       strex   %1, %2, [%3]\n"
+                "       teq     %1, #0\n"
+                "       bne     1b"
+                        : "=&r" (ret), "=&r" (tmp)
+                        : "r" (x), "r" (ptr)
+                        : "memory", "cc");
+                break;
+#elif defined(swp_is_buggy)
+#ifdef CONFIG_SMP
+#error SMP is not supported on this platform
+#endif
+        case 1:
+                local_irq_save(flags);
+                ret = *(volatile unsigned char *)ptr;
+                *(volatile unsigned char *)ptr = x;
+                local_irq_restore(flags);
+                break;
+        case 4:
+                local_irq_save(flags);
+                ret = *(volatile unsigned long *)ptr;
+                *(volatile unsigned long *)ptr = x;
+                local_irq_restore(flags);
+                break;
 #else
-                case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
+        case 1:
-                                        : "=&r" (ret)
+                asm volatile("@ __xchg1\n"
-                                        : "r" (x), "r" (ptr)
+                "       swpb    %0, %1, [%2]"
-                                        : "memory", "cc");
+                        : "=&r" (ret)
-                        break;
+                        : "r" (x), "r" (ptr)
-                case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
+                        : "memory", "cc");
-                                        : "=&r" (ret)
+                break;
-                                        : "r" (x), "r" (ptr)
+        case 4:
-                                        : "memory", "cc");
+                asm volatile("@ __xchg4\n"
-                        break;
+                "       swp     %0, %1, [%2]"
+                        : "=&r" (ret)
+                        : "r" (x), "r" (ptr)
+                        : "memory", "cc");
+                break;
 #endif
-                default: __bad_xchg(ptr, size), ret = 0;
+        default:
+                __bad_xchg(ptr, size), ret = 0;
+                break;
        }
        return ret;
 }
-#endif /* CONFIG_SMP */
 #endif /* __ASSEMBLY__ */
 #define arch_align_stack(x) (x)
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 66c585c50cf9..8252a4cd860f 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -49,7 +49,7 @@ struct cpu_context_save {
 */
 struct thread_info {
        unsigned long           flags;          /* low level flags */
-        __s32                   preempt_count;  /* 0 => preemptable, <0 => bug */
+        int                     preempt_count;  /* 0 => preemptable, <0 => bug */
        mm_segment_t            addr_limit;     /* address limit */
        struct task_struct      *task;          /* main task structure */
        struct exec_domain      *exec_domain;   /* execution domain */
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8a864b118569..9387a5e1ffe0 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -235,7 +235,7 @@ extern struct cpu_tlb_fns cpu_tlb;
 #define tlb_flag(f)     ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
-static inline void flush_tlb_all(void)
+static inline void local_flush_tlb_all(void)
 {
        const int zero = 0;
        const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -253,7 +253,7 @@ static inline void flush_tlb_all(void)
                asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
 }
-static inline void flush_tlb_mm(struct mm_struct *mm)
+static inline void local_flush_tlb_mm(struct mm_struct *mm)
 {
        const int zero = 0;
        const int asid = ASID(mm);
@@ -282,7 +282,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
 }
 static inline void
-flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 {
        const int zero = 0;
        const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -313,7 +313,7 @@ flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
 }
-static inline void flush_tlb_kernel_page(unsigned long kaddr)
+static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
 {
        const int zero = 0;
        const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -384,8 +384,24 @@ static inline void clean_pmd_entry(pmd_t *pmd)
 /*
 * Convert calls to our calling convention.
 */
-#define flush_tlb_range(vma,start,end)  __cpu_flush_user_tlb_range(start,end,vma)
+#define local_flush_tlb_range(vma,start,end)    __cpu_flush_user_tlb_range(start,end,vma)
-#define flush_tlb_kernel_range(s,e)     __cpu_flush_kern_tlb_range(s,e)
+#define local_flush_tlb_kernel_range(s,e)       __cpu_flush_kern_tlb_range(s,e)
+#ifndef CONFIG_SMP
+#define flush_tlb_all           local_flush_tlb_all
+#define flush_tlb_mm            local_flush_tlb_mm
+#define flush_tlb_page          local_flush_tlb_page
+#define flush_tlb_kernel_page   local_flush_tlb_kernel_page
+#define flush_tlb_range         local_flush_tlb_range
+#define flush_tlb_kernel_range  local_flush_tlb_kernel_range
+#else
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
+extern void flush_tlb_kernel_page(unsigned long kaddr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+#endif
 /*
 * if PG_dcache_dirty is set for the page, we need to ensure that any
diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h
index f4c92e4c8c02..22992ee0627a 100644
--- a/include/asm-arm/types.h
+++ b/include/asm-arm/types.h
@@ -52,8 +52,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
-typedef unsigned int kmem_bufctl_t;
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-arm/uaccess.h b/include/asm-arm/uaccess.h
index a7c018b8a0d4..a2fdad0138b3 100644
--- a/include/asm-arm/uaccess.h
+++ b/include/asm-arm/uaccess.h
@@ -77,12 +77,6 @@ static inline void set_fs (mm_segment_t fs)
 #define access_ok(type,addr,size)       (__range_ok(addr,size) == 0)
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void __user *addr, unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
 /*
 * Single-value transfer routines.  They automatically use the right
 * size if we just have the right pointer type.  Note that the functions
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index ace27480886e..278de61224d1 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -295,7 +295,7 @@
 #define __NR_fstatfs64                  (__NR_SYSCALL_BASE+267)
 #define __NR_tgkill                     (__NR_SYSCALL_BASE+268)
 #define __NR_utimes                     (__NR_SYSCALL_BASE+269)
-#define __NR_fadvise64_64               (__NR_SYSCALL_BASE+270)
+#define __NR_arm_fadvise64_64           (__NR_SYSCALL_BASE+270)
 #define __NR_pciconfig_iobase           (__NR_SYSCALL_BASE+271)
 #define __NR_pciconfig_read             (__NR_SYSCALL_BASE+272)
 #define __NR_pciconfig_write            (__NR_SYSCALL_BASE+273)
@@ -350,6 +350,11 @@
 #endif
 #define __NR_vserver                    (__NR_SYSCALL_BASE+313)
+#define __NR_ioprio_set                 (__NR_SYSCALL_BASE+314)
+#define __NR_ioprio_get                 (__NR_SYSCALL_BASE+315)
+#define __NR_inotify_init               (__NR_SYSCALL_BASE+316)
+#define __NR_inotify_add_watch          (__NR_SYSCALL_BASE+317)
+#define __NR_inotify_rm_watch           (__NR_SYSCALL_BASE+318)
 /*
 * The following SWIs are ARM private.
@@ -510,7 +515,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #define __ARCH_WANT_SYS_TIME
 #define __ARCH_WANT_SYS_UTIME
 #define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
 #define __ARCH_WANT_SYS_GETPGRP
 #define __ARCH_WANT_SYS_LLSEEK
 #define __ARCH_WANT_SYS_NICE