aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-iop32x/iop321.h132
-rw-r--r--include/asm-arm/arch-iop33x/iop331.h115
-rw-r--r--include/asm-arm/hardware/iop3xx.h114
3 files changed, 114 insertions, 247 deletions
diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h
index 8042946327ed..1757222a4cad 100644
--- a/include/asm-arm/arch-iop32x/iop321.h
+++ b/include/asm-arm/arch-iop32x/iop321.h
@@ -37,102 +37,13 @@
37 37
38/* Messaging Unit 0x00000300 through 0x000003FF */ 38/* Messaging Unit 0x00000300 through 0x000003FF */
39 39
40/* Reserved 0x00000300 through 0x0000030c */
41#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310)
42#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314)
43#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318)
44#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
45#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320)
46#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324)
47#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328)
48#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
49#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330)
50#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334)
51/* Reserved 0x00000338 through 0x0000034F */
52#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350)
53#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354)
54/* Reserved 0x00000358 through 0x0000035C */
55#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360)
56#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364)
57#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368)
58#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
59#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370)
60#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374)
61#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
62#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
63#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
64
65#define IOP321_IIxR_MASK 0x7f /* masks all */
66#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */
67#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */
68#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */
69#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */
70#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */
71#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */
72#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */
73
74/* Reserved 0x00000384 through 0x000003FF */
75
76/* DMA Controller 0x00000400 through 0x000004FF */ 40/* DMA Controller 0x00000400 through 0x000004FF */
77#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400)
78#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404)
79#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
80#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410)
81#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414)
82#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
83#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
84#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420)
85#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424)
86/* Reserved 0x00000428 through 0x0000043C */
87#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440)
88#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444)
89#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
90#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450)
91#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454)
92#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
93#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
94#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460)
95#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464)
96/* Reserved 0x00000468 through 0x000004FF */
97 41
98/* Memory controller 0x00000500 through 0x0005FF */ 42/* Memory controller 0x00000500 through 0x0005FF */
99 43
100/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ 44/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
101#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680)
102#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684)
103#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688)
104#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
105#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690)
106#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694)
107#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698)
108#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
109#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
110#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
111#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
112#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
113#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
114#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
115#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
116/* Reserved 0x000006BC */
117#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
118/* Reserved 0x000006C4 through 0x000006DC */
119#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
120#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
121
122#define IOP321_PBCR_EN 0x1
123
124#define IOP321_PBISR_BOOR_ERR 0x1
125 45
126/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ 46/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
127#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700)
128#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704)
129#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708)
130/* reserved 0x00000070c */
131#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710)
132/* PERC0 DOESN'T EXIST - index from 1! */
133#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710)
134
135#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */
136 47
137/* Internal arbitration unit 0x00000780 through 0x0007BF */ 48/* Internal arbitration unit 0x00000780 through 0x0007BF */
138#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780) 49#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
@@ -151,49 +62,6 @@
151#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) 62#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
152 63
153/* Application accelerator unit 0x00000800 - 0x000008FF */ 64/* Application accelerator unit 0x00000800 - 0x000008FF */
154#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
155#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
156#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
157#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
158#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
159#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814)
160#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818)
161#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
162#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
163#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830)
164#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834)
165#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838)
166#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840)
167#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844)
168#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848)
169#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
170#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850)
171#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854)
172#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858)
173#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
174#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864)
175#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868)
176#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
177#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870)
178#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874)
179#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878)
180#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
181#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880)
182#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888)
183#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
184#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890)
185#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894)
186#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898)
187#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
188#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
189#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
190#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
191#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
192#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
193#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
194#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860)
195#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884)
196
197 65
198/* SSP serial port unit 0x00001600 - 0x0000167F */ 66/* SSP serial port unit 0x00001600 - 0x0000167F */
199/* I2C bus interface unit 0x00001680 - 0x000016FF */ 67/* I2C bus interface unit 0x00001680 - 0x000016FF */
diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h
index a21872abd877..8c7ec583615f 100644
--- a/include/asm-arm/arch-iop33x/iop331.h
+++ b/include/asm-arm/arch-iop33x/iop331.h
@@ -36,83 +36,11 @@
36 36
37/* Messaging Unit 0x00000300 through 0x000003FF */ 37/* Messaging Unit 0x00000300 through 0x000003FF */
38 38
39/* Reserved 0x00000300 through 0x0000030c */
40#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310)
41#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314)
42#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318)
43#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
44#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320)
45#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324)
46#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328)
47#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
48#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330)
49#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334)
50/* Reserved 0x00000338 through 0x0000034F */
51#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350)
52#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354)
53/* Reserved 0x00000358 through 0x0000035C */
54#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360)
55#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364)
56#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368)
57#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
58#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370)
59#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374)
60#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378)
61#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
62#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380)
63/* Reserved 0x00000384 through 0x000003FF */
64
65/* DMA Controller 0x00000400 through 0x000004FF */ 39/* DMA Controller 0x00000400 through 0x000004FF */
66#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400)
67#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404)
68#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
69#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410)
70#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414)
71#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
72#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
73#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420)
74#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424)
75/* Reserved 0x00000428 through 0x0000043C */
76#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440)
77#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444)
78#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
79#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450)
80#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454)
81#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
82#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
83#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460)
84#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464)
85/* Reserved 0x00000468 through 0x000004FF */
86 40
87/* Memory controller 0x00000500 through 0x0005FF */ 41/* Memory controller 0x00000500 through 0x0005FF */
88 42
89/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ 43/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
90#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680)
91#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684)
92#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688)
93#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
94#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690)
95#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694)
96#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698)
97#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
98#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
99#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
100#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
101#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
102#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
103#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
104#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
105/* Reserved 0x000006BC */
106#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
107/* Reserved 0x000006C4 through 0x000006DC */
108#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
109#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
110
111#define IOP331_PBCR_EN 0x1
112
113#define IOP331_PBISR_BOOR_ERR 0x1
114
115
116 44
117/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ 45/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
118/* Internal arbitration unit 0x00000780 through 0x0007BF */ 46/* Internal arbitration unit 0x00000780 through 0x0007BF */
@@ -137,49 +65,6 @@
137 65
138 66
139/* Application accelerator unit 0x00000800 - 0x000008FF */ 67/* Application accelerator unit 0x00000800 - 0x000008FF */
140#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
141#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
142#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808)
143#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
144#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810)
145#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814)
146#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818)
147#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
148#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
149#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830)
150#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834)
151#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838)
152#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840)
153#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844)
154#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848)
155#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
156#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850)
157#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854)
158#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858)
159#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
160#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864)
161#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868)
162#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
163#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870)
164#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874)
165#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878)
166#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
167#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880)
168#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888)
169#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
170#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890)
171#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894)
172#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898)
173#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
174#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
175#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
176#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820)
177#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824)
178#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828)
179#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
180#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860)
181#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884)
182
183 68
184#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0) 69#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
185#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8) 70#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index f3c61d041fca..1018a7486ab7 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -97,6 +97,76 @@ extern void gpio_line_set(int line, int value);
97#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) 97#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
98#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) 98#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
99 99
100/* Messaging Unit */
101#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
102#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
103#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
104#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
105#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
106#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
107#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
108#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
109#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
110#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
111#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
112#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
113#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
114#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
115#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
116#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
117#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
118#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
119#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
120#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
121#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
122
123/* DMA Controller */
124#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
125#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
126#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
127#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
128#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
129#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
130#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
131#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
132#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
133#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
134#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
135#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
136#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
137#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
138#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
139#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
140#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
141#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
142
143/* Peripheral bus interface */
144#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
145#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
146#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
147#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
148#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
149#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
150#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
151#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
152#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
153#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
154#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
155#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
156#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
157#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
158#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
159#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
160#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
161
162/* Peripheral performance monitoring unit */
163#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
164#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
165#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
166#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
167/* PERCR0 DOESN'T EXIST - index from 1! */
168#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
169
100/* General Purpose I/O */ 170/* General Purpose I/O */
101#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004) 171#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
102#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008) 172#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
@@ -120,6 +190,50 @@ extern void gpio_line_set(int line, int value);
120#define IOP3XX_TMR_RATIO_8_1 0x20 190#define IOP3XX_TMR_RATIO_8_1 0x20
121#define IOP3XX_TMR_RATIO_16_1 0x30 191#define IOP3XX_TMR_RATIO_16_1 0x30
122 192
193/* Application accelerator unit */
194#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
195#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
196#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
197#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
198#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
199#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
200#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
201#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
202#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
203#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
204#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
205#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
206#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
207#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
208#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
209#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
210#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
211#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
212#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
213#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
214#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
215#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
216#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
217#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
218#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
219#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
220#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
221#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
222#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
223#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
224#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
225#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
226#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
227#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
228#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
229#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
230#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
231#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
232#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
233#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
234#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
235#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
236
123/* I2C bus interface unit */ 237/* I2C bus interface unit */
124#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) 238#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
125#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) 239#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 11:30:26 -0500