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-rw-r--r--include/asm-arm/arch-pxa/irda.h17
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
2 files changed, 17 insertions, 2 deletions
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
new file mode 100644
index 000000000000..748406f384c2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -0,0 +1,17 @@
1#ifndef ASMARM_ARCH_IRDA_H
2#define ASMARM_ARCH_IRDA_H
3
4/* board specific transceiver capabilities */
5
6#define IR_OFF 1
7#define IR_SIRMODE 2
8#define IR_FIRMODE 4
9
10struct pxaficp_platform_data {
11 int transceiver_cap;
12 void (*transceiver_mode)(struct device *dev, int mode);
13};
14
15extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
16
17#endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 75f085dc9894..a75a2470f4f5 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1032,14 +1032,12 @@
1032#define ICCR0_LBM (1 << 1) /* Loopback mode */ 1032#define ICCR0_LBM (1 << 1) /* Loopback mode */
1033#define ICCR0_ITR (1 << 0) /* IrDA transmission */ 1033#define ICCR0_ITR (1 << 0) /* IrDA transmission */
1034 1034
1035#ifdef CONFIG_PXA27x
1036#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ 1035#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
1037#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ 1036#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
1038#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ 1037#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
1039#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ 1038#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
1040#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ 1039#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
1041#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ 1040#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
1042#endif
1043 1041
1044#ifdef CONFIG_PXA27x 1042#ifdef CONFIG_PXA27x
1045#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ 1043#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */