14 files changed, 453 insertions, 138 deletions

diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
new file mode 100644
index 000000000000..bff5ea45f604
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
@@ -0,0 +1,81 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Serial Peripheral Interface (SPI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_SPI_H
+#define AT91RM9200_SPI_H
+
+#define AT91_SPI_CR                     0x00            /* Control Register */
+#define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
+#define         AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
+#define         AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
+#define         AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_MR                     0x04            /* Mode Register */
+#define         AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
+#define         AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
+#define                 AT91_SPI_PS_FIXED       (0 << 1)
+#define                 AT91_SPI_PS_VARIABLE    (1 << 1)
+#define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
+#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection */
+#define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
+#define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
+#define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
+#define         AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
+
+#define AT91_SPI_RDR            0x08                    /* Receive Data Register */
+#define         AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
+#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
+
+#define AT91_SPI_TDR            0x0c                    /* Transmit Data Register */
+#define         AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
+#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
+#define         AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_SR             0x10                    /* Status Register */
+#define         AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
+#define         AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
+#define         AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
+#define         AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
+#define         AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
+#define         AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
+#define         AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
+#define         AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
+#define         AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
+#define         AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
+#define         AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
+
+#define AT91_SPI_IER            0x14                    /* Interrupt Enable Register */
+#define AT91_SPI_IDR            0x18                    /* Interrupt Disable Register */
+#define AT91_SPI_IMR            0x1c                    /* Interrupt Mask Register */
+
+#define AT91_SPI_CSR(n)         (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
+#define         AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
+#define         AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
+#define         AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
+#define         AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
+#define                 AT91_SPI_BITS_8         (0 << 4)
+#define                 AT91_SPI_BITS_9         (1 << 4)
+#define                 AT91_SPI_BITS_10        (2 << 4)
+#define                 AT91_SPI_BITS_11        (3 << 4)
+#define                 AT91_SPI_BITS_12        (4 << 4)
+#define                 AT91_SPI_BITS_13        (5 << 4)
+#define                 AT91_SPI_BITS_14        (6 << 4)
+#define                 AT91_SPI_BITS_15        (7 << 4)
+#define                 AT91_SPI_BITS_16        (8 << 4)
+#define         AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
+#define         AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
+#define         AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
new file mode 100644
index 000000000000..ac880227147f
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Serial Synchronous Controller (SSC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_SSC_H
+#define AT91RM9200_SSC_H
+
+#define AT91_SSC_CR             0x00    /* Control Register */
+#define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
+#define         AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
+#define         AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
+#define         AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
+#define         AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
+
+#define AT91_SSC_CMR            0x04    /* Clock Mode Register */
+#define         AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
+
+#define AT91_SSC_RCMR           0x10    /* Receive Clock Mode Register */
+#define         AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
+#define                 AT91_SSC_CKS_DIV                (0 << 0)
+#define                 AT91_SSC_CKS_CLOCK              (1 << 0)
+#define                 AT91_SSC_CKS_PIN                (2 << 0)
+#define         AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
+#define                 AT91_SSC_CKO_NONE               (0 << 2)
+#define                 AT91_SSC_CKO_CONTINUOUS         (1 << 2)
+#define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
+#define                 AT91_SSC_CKI_FALLING            (0 << 5)
+#define                 AT91_SSC_CK_RISING              (1 << 5)
+#define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
+#define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
+#define                 AT91_SSC_START_TX_RX            (1 << 8)
+#define                 AT91_SSC_START_LOW_RF           (2 << 8)
+#define                 AT91_SSC_START_HIGH_RF          (3 << 8)
+#define                 AT91_SSC_START_FALLING_RF       (4 << 8)
+#define                 AT91_SSC_START_RISING_RF        (5 << 8)
+#define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
+#define                 AT91_SSC_START_EDGE_RF          (7 << 8)
+#define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
+#define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
+
+#define AT91_SSC_RFMR           0x14    /* Receive Frame Mode Register */
+#define         AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
+#define         AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
+#define         AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
+#define         AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
+#define         AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
+#define         AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
+#define                 AT91_SSC_FSOS_NONE              (0 << 20)
+#define                 AT91_SSC_FSOS_NEGATIVE          (1 << 20)
+#define                 AT91_SSC_FSOS_POSITIVE          (2 << 20)
+#define                 AT91_SSC_FSOS_LOW               (3 << 20)
+#define                 AT91_SSC_FSOS_HIGH              (4 << 20)
+#define                 AT91_SSC_FSOS_TOGGLE            (5 << 20)
+#define         AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
+#define                 AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
+#define                 AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
+
+#define AT91_SSC_TCMR           0x18    /* Transmit Clock Mode Register */
+#define AT91_SSC_TFMR           0x1c    /* Transmit Fram Mode Register */
+#define         AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
+#define         AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
+
+#define AT91_SSC_RHR            0x20    /* Receive Holding Register */
+#define AT91_SSC_THR            0x24    /* Transmit Holding Register */
+#define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
+#define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
+
+#define AT91_SSC_SR             0x40    /* Status Register */
+#define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
+#define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
+#define         AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
+#define         AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
+#define         AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
+#define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
+#define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
+#define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
+#define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
+#define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
+#define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
+#define         AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
+
+#define AT91_SSC_IER            0x44    /* Interrupt Enable Register */
+#define AT91_SSC_IDR            0x48    /* Interrupt Disable Register */
+#define AT91_SSC_IMR            0x4c    /* Interrupt Mask Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 2910d359f919..0f4c12d5f0cd 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -68,8 +68,17 @@
 #define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
 #define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
 #define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
+
 #define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
 #define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
+#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
+#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
+#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
+#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
+#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
+#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
+#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
 
 
 /*
@@ -241,7 +250,7 @@
 #define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
 #define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
 #define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
-#define         At91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
+#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
 
 #define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
 #define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
new file mode 100644
index 000000000000..f4da752bb0c8
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
@@ -0,0 +1,146 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Timer/Counter Unit (TC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_TC_H
+#define AT91RM9200_TC_H
+
+#define AT91_TC_BCR             0xc0            /* TC Block Control Register */
+#define         AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
+
+#define AT91_TC_BMR             0xc4            /* TC Block Mode Register */
+#define         AT91_TC_TC0XC0S         (3 << 0)        /* External Clock Signal 0 Selection */
+#define                 AT91_TC_TC0XC0S_TCLK0           (0 << 0)
+#define                 AT91_TC_TC0XC0S_NONE            (1 << 0)
+#define                 AT91_TC_TC0XC0S_TIOA1           (2 << 0)
+#define                 AT91_TC_TC0XC0S_TIOA2           (3 << 0)
+#define         AT91_TC_TC1XC1S         (3 << 2)        /* External Clock Signal 1 Selection */
+#define                 AT91_TC_TC1XC1S_TCLK1           (0 << 2)
+#define                 AT91_TC_TC1XC1S_NONE            (1 << 2)
+#define                 AT91_TC_TC1XC1S_TIOA0           (2 << 2)
+#define                 AT91_TC_TC1XC1S_TIOA2           (3 << 2)
+#define         AT91_TC_TC2XC2S         (3 << 4)        /* External Clock Signal 2 Selection */
+#define                 AT91_TC_TC2XC2S_TCLK2           (0 << 4)
+#define                 AT91_TC_TC2XC2S_NONE            (1 << 4)
+#define                 AT91_TC_TC2XC2S_TIOA0           (2 << 4)
+#define                 AT91_TC_TC2XC2S_TIOA1           (3 << 4)
+
+
+#define AT91_TC_CCR             0x00            /* Channel Control Register */
+#define         AT91_TC_CLKEN           (1 << 0)        /* Counter Clock Enable Command */
+#define         AT91_TC_CLKDIS          (1 << 1)        /* Counter CLock Disable Command */
+#define         AT91_TC_SWTRG           (1 << 2)        /* Software Trigger Command */
+
+#define AT91_TC_CMR             0x04            /* Channel Mode Register */
+#define         AT91_TC_TCCLKS          (7 << 0)        /* Capture/Waveform Mode: Clock Selection */
+#define                 AT91_TC_TIMER_CLOCK1            (0 << 0)
+#define                 AT91_TC_TIMER_CLOCK2            (1 << 0)
+#define                 AT91_TC_TIMER_CLOCK3            (2 << 0)
+#define                 AT91_TC_TIMER_CLOCK4            (3 << 0)
+#define                 AT91_TC_TIMER_CLOCK5            (4 << 0)
+#define                 AT91_TC_XC0                     (5 << 0)
+#define                 AT91_TC_XC1                     (6 << 0)
+#define                 AT91_TC_XC2                     (7 << 0)
+#define         AT91_TC_CLKI            (1 << 3)        /* Capture/Waveform Mode: Clock Invert */
+#define         AT91_TC_BURST           (3 << 4)        /* Capture/Waveform Mode: Burst Signal Selection */
+#define         AT91_TC_LDBSTOP         (1 << 6)        /* Capture Mode: Counter Clock Stopped with TB Loading */
+#define         AT91_TC_LDBDIS          (1 << 7)        /* Capture Mode: Counter Clock Disable with RB Loading */
+#define         AT91_TC_ETRGEDG         (3 << 8)        /* Capture Mode: External Trigger Edge Selection */
+#define         AT91_TC_ABETRG          (1 << 10)       /* Capture Mode: TIOA or TIOB External Trigger Selection */
+#define         AT91_TC_CPCTRG          (1 << 14)       /* Capture Mode: RC Compare Trigger Enable */
+#define         AT91_TC_WAVE            (1 << 15)       /* Capture/Waveform mode */
+#define         AT91_TC_LDRA            (3 << 16)       /* Capture Mode: RA Loading Selection */
+#define         AT91_TC_LDRB            (3 << 18)       /* Capture Mode: RB Loading Selection */
+
+#define         AT91_TC_CPCSTOP         (1 <<  6)       /* Waveform Mode: Counter Clock Stopped with RC Compare */
+#define         AT91_TC_CPCDIS          (1 <<  7)       /* Waveform Mode: Counter Clock Disable with RC Compare */
+#define         AT91_TC_EEVTEDG         (3 <<  8)       /* Waveform Mode: External Event Edge Selection */
+#define                 AT91_TC_EEVTEDG_NONE            (0 << 8)
+#define                 AT91_TC_EEVTEDG_RISING          (1 << 8)
+#define                 AT91_TC_EEVTEDG_FALLING         (2 << 8)
+#define                 AT91_TC_EEVTEDG_BOTH            (3 << 8)
+#define         AT91_TC_EEVT            (3 << 10)       /* Waveform Mode: External Event Selection */
+#define                 AT91_TC_EEVT_TIOB               (0 << 10)
+#define                 AT91_TC_EEVT_XC0                (1 << 10)
+#define                 AT91_TC_EEVT_XC1                (2 << 10)
+#define                 AT91_TC_EEVT_XC2                (3 << 10)
+#define         AT91_TC_ENETRG          (1 << 12)       /* Waveform Mode: External Event Trigger Enable */
+#define         AT91_TC_WAVESEL         (3 << 13)       /* Waveform Mode: Waveform Selection */
+#define                 AT91_TC_WAVESEL_UP              (0 << 13)
+#define                 AT91_TC_WAVESEL_UP_AUTO         (2 << 13)
+#define                 AT91_TC_WAVESEL_UPDOWN          (1 << 13)
+#define                 AT91_TC_WAVESEL_UPDOWN_AUTO     (3 << 13)
+#define         AT91_TC_ACPA            (3 << 16)       /* Waveform Mode: RA Compare Effect on TIOA */
+#define                 AT91_TC_ACPA_NONE               (0 << 16)
+#define                 AT91_TC_ACPA_SET                (1 << 16)
+#define                 AT91_TC_ACPA_CLEAR              (2 << 16)
+#define                 AT91_TC_ACPA_TOGGLE             (3 << 16)
+#define         AT91_TC_ACPC            (3 << 18)       /* Waveform Mode: RC Compre Effect on TIOA */
+#define                 AT91_TC_ACPC_NONE               (0 << 18)
+#define                 AT91_TC_ACPC_SET                (1 << 18)
+#define                 AT91_TC_ACPC_CLEAR              (2 << 18)
+#define                 AT91_TC_ACPC_TOGGLE             (3 << 18)
+#define         AT91_TC_AEEVT           (3 << 20)       /* Waveform Mode: External Event Effect on TIOA */
+#define                 AT91_TC_AEEVT_NONE              (0 << 20)
+#define                 AT91_TC_AEEVT_SET               (1 << 20)
+#define                 AT91_TC_AEEVT_CLEAR             (2 << 20)
+#define                 AT91_TC_AEEVT_TOGGLE            (3 << 20)
+#define         AT91_TC_ASWTRG          (3 << 22)       /* Waveform Mode: Software Trigger Effect on TIOA */
+#define                 AT91_TC_ASWTRG_NONE             (0 << 22)
+#define                 AT91_TC_ASWTRG_SET              (1 << 22)
+#define                 AT91_TC_ASWTRG_CLEAR            (2 << 22)
+#define                 AT91_TC_ASWTRG_TOGGLE           (3 << 22)
+#define         AT91_TC_BCPB            (3 << 24)       /* Waveform Mode: RB Compare Effect on TIOB */
+#define                 AT91_TC_BCPB_NONE               (0 << 24)
+#define                 AT91_TC_BCPB_SET                (1 << 24)
+#define                 AT91_TC_BCPB_CLEAR              (2 << 24)
+#define                 AT91_TC_BCPB_TOGGLE             (3 << 24)
+#define         AT91_TC_BCPC            (3 << 26)       /* Waveform Mode: RC Compare Effect on TIOB */
+#define                 AT91_TC_BCPC_NONE               (0 << 26)
+#define                 AT91_TC_BCPC_SET                (1 << 26)
+#define                 AT91_TC_BCPC_CLEAR              (2 << 26)
+#define                 AT91_TC_BCPC_TOGGLE             (3 << 26)
+#define         AT91_TC_BEEVT           (3 << 28)       /* Waveform Mode: External Event Effect on TIOB */
+#define                 AT91_TC_BEEVT_NONE              (0 << 28)
+#define                 AT91_TC_BEEVT_SET               (1 << 28)
+#define                 AT91_TC_BEEVT_CLEAR             (2 << 28)
+#define                 AT91_TC_BEEVT_TOGGLE            (3 << 28)
+#define         AT91_TC_BSWTRG          (3 << 30)       /* Waveform Mode: Software Trigger Effect on TIOB */
+#define                 AT91_TC_BSWTRG_NONE             (0 << 30)
+#define                 AT91_TC_BSWTRG_SET              (1 << 30)
+#define                 AT91_TC_BSWTRG_CLEAR            (2 << 30)
+#define                 AT91_TC_BSWTRG_TOGGLE           (3 << 30)
+
+#define AT91_TC_CV              0x10            /* Counter Value */
+#define AT91_TC_RA              0x14            /* Register A */
+#define AT91_TC_RB              0x18            /* Register B */
+#define AT91_TC_RC              0x1c            /* Register C */
+
+#define AT91_TC_SR              0x20            /* Status Register */
+#define         AT91_TC_COVFS           (1 <<  0)       /* Counter Overflow Status */
+#define         AT91_TC_LOVRS           (1 <<  1)       /* Load Overrun Status */
+#define         AT91_TC_CPAS            (1 <<  2)       /* RA Compare Status */
+#define         AT91_TC_CPBS            (1 <<  3)       /* RB Compare Status */
+#define         AT91_TC_CPCS            (1 <<  4)       /* RC Compare Status */
+#define         AT91_TC_LDRAS           (1 <<  5)       /* RA Loading Status */
+#define         AT91_TC_LDRBS           (1 <<  6)       /* RB Loading Status */
+#define         AT91_TC_ETRGS           (1 <<  7)       /* External Trigger Status */
+#define         AT91_TC_CLKSTA          (1 << 16)       /* Clock Enabling Status */
+#define         AT91_TC_MTIOA           (1 << 17)       /* TIOA Mirror */
+#define         AT91_TC_MTIOB           (1 << 18)       /* TIOB Mirror */
+
+#define AT91_TC_IER             0x24            /* Interrupt Enable Register */
+#define AT91_TC_IDR             0x28            /* Interrupt Disable Register */
+#define AT91_TC_IMR             0x2c            /* Interrupt Mask Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
new file mode 100644
index 000000000000..951e3f61cef4
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
@@ -0,0 +1,77 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * USB Device Port (UDP) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_UDP_H
+#define AT91RM9200_UDP_H
+
+#define AT91_UDP_FRM_NUM        0x00            /* Frame Number Register */
+#define         AT91_UDP_NUM            (0x7ff <<  0)           /* Frame Number */
+#define         AT91_UDP_FRM_ERR        (1     << 16)           /* Frame Error */
+#define         AT91_UDP_FRM_OK         (1     << 17)           /* Frame OK */
+
+#define AT91_UDP_GLB_STAT       0x04            /* Global State Register */
+#define         AT91_UDP_FADDEN         (1 <<  0)               /* Function Address Enable */
+#define         AT91_UDP_CONFG          (1 <<  1)               /* Configured */
+#define         AT91_UDP_ESR            (1 <<  2)               /* Enable Send Resume */
+#define         AT91_UDP_RSMINPR        (1 <<  3)               /* Resume has been sent */
+#define         AT91_UDP_RMWUPE         (1 <<  4)               /* Remote Wake Up Enable */
+
+#define AT91_UDP_FADDR          0x08            /* Function Address Register */
+#define         AT91_UDP_FADD           (0x7f << 0)             /* Function Address Value */
+#define         AT91_UDP_FEN            (1    << 8)             /* Function Enable */
+
+#define AT91_UDP_IER            0x10            /* Interrupt Enable Register */
+#define AT91_UDP_IDR            0x14            /* Interrupt Disable Register */
+#define AT91_UDP_IMR            0x18            /* Interrupt Mask Register */
+
+#define AT91_UDP_ISR            0x1c            /* Interrupt Status Register */
+#define         AT91_UDP_EP(n)          (1 << (n))              /* Endpoint Interrupt Status */
+#define         AT91_UDP_RXSUSP         (1 <<  8)               /* USB Suspend Interrupt Status */
+#define         AT91_UDP_RXRSM          (1 <<  9)               /* USB Resume Interrupt Status */
+#define         AT91_UDP_EXTRSM         (1 << 10)               /* External Resume Interrupt Status */
+#define         AT91_UDP_SOFINT         (1 << 11)               /* Start of Frame Interrupt Status */
+#define         AT91_UDP_ENDBUSRES      (1 << 12)               /* End of Bus Reset Interrpt Status */
+#define         AT91_UDP_WAKEUP         (1 << 13)               /* USB Wakeup Interrupt Status */
+
+#define AT91_UDP_ICR            0x20            /* Interrupt Clear Register */
+#define AT91_UDP_RST_EP         0x28            /* Reset Endpoint Register */
+
+#define AT91_UDP_CSR(n)         (0x30 + ((n) * 4))      /* Endpoint Control/Status Registers 0-7 */
+#define         AT91_UDP_TXCOMP         (1 <<  0)               /* Generates IN packet with data previously written in DPR */
+#define         AT91_UDP_RX_DATA_BK0    (1 <<  1)               /* Receive Data Bank 0 */
+#define         AT91_UDP_RXSETUP        (1 <<  2)               /* Send STALL to the host */
+#define         AT91_UDP_STALLSENT      (1 <<  3)               /* Stall Sent / Isochronous error (Isochronous endpoints) */
+#define         AT91_UDP_TXPKTRDY       (1 <<  4)               /* Transmit Packet Ready */
+#define         AT91_UDP_FORCESTALL     (1 <<  5)               /* Force Stall */
+#define         AT91_UDP_RX_DATA_BK1    (1 <<  6)               /* Receive Data Bank 1 */
+#define         AT91_UDP_DIR            (1 <<  7)               /* Transfer Direction */
+#define         AT91_UDP_EPTYPE         (7 <<  8)               /* Endpoint Type */
+#define                 AT91_UDP_EPTYPE_CTRL            (0 <<  8)
+#define                 AT91_UDP_EPTYPE_ISO_OUT         (1 <<  8)
+#define                 AT91_UDP_EPTYPE_BULK_OUT        (2 <<  8)
+#define                 AT91_UDP_EPTYPE_INT_OUT         (3 <<  8)
+#define                 AT91_UDP_EPTYPE_ISO_IN          (5 <<  8)
+#define                 AT91_UDP_EPTYPE_BULK_IN         (6 <<  8)
+#define                 AT91_UDP_EPTYPE_INT_IN          (7 <<  8)
+#define         AT91_UDP_DTGLE          (1 << 11)               /* Data Toggle */
+#define         AT91_UDP_EPEDS          (1 << 15)               /* Endpoint Enable/Disable */
+#define         AT91_UDP_RXBYTECNT      (0x7ff << 16)           /* Number of bytes in FIFO */
+
+#define AT91_UDP_FDR(n)         (0x50 + ((n) * 4))      /* Endpoint FIFO Data Registers 0-7 */
+
+#define AT91_UDP_TXVC           0x74            /* Transceiver Control Register */
+#define         AT91_UDP_TXVC_TXVDIS    (1 << 8)                /* Transceiver Disable */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
index 4fdef13d01d4..1fdd70b23809 100644
--- a/include/asm-arm/arch-at91rm9200/board.h
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -31,14 +31,9 @@
 #ifndef __ASM_ARCH_BOARD_H
 #define __ASM_ARCH_BOARD_H
 
- /* Clocks */
-extern unsigned long at91_master_clock;
-
- /* Serial Port */
-extern int at91_serial_map[AT91_NR_UART];
-extern int at91_console_port;
-
 #include <linux/mtd/partitions.h>
+#include <linux/device.h>
+#include <linux/spi/spi.h>
 
  /* USB Device */
 struct at91_udc_data {
@@ -91,10 +86,25 @@ struct at91_nand_data {
 extern void __init at91_add_device_nand(struct at91_nand_data *data);
 
  /* I2C*/
-void __init at91_add_device_i2c(void);
+extern void __init at91_add_device_i2c(void);
+
+ /* SPI */
+extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
 
- /* RTC */
-void __init at91_add_device_rtc(void);
+ /* Serial */
+struct at91_uart_config {
+        unsigned short  console_tty;    /* tty number of serial console */
+        unsigned short  nr_tty;         /* number of serial tty's */
+        short           tty_map[];      /* map UART to tty number */
+};
+extern struct platform_device *at91_default_console_device;
+extern void __init at91_init_serial(struct at91_uart_config *config);
+
+struct at91_uart_data {
+        short           use_dma_tx;     /* use transmit DMA? */
+        short           use_dma_rx;     /* use receive DMA? */
+};
+extern void __init at91_add_device_serial(void);
 
  /* LEDs */
 extern u8 at91_leds_cpu;
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
index 6176ab2dc417..dbde1baaf251 100644
--- a/include/asm-arm/arch-at91rm9200/gpio.h
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_AT91RM9200_GPIO_H
 #define __ASM_ARCH_AT91RM9200_GPIO_H
 
+#include <asm/irq.h>
+
 #define PIN_BASE                NR_AIC_IRQS
 
 #define PQFP_GPIO_BANKS         3       /* PQFP package has 3 banks */
@@ -188,6 +190,9 @@ extern int at91_set_multi_drive(unsigned pin, int is_on);
 /* callable at any time */
 extern int at91_set_gpio_value(unsigned pin, int value);
 extern int at91_get_gpio_value(unsigned pin);
+
+extern void at91_gpio_suspend(void);
+extern void at91_gpio_resume(void);
 #endif
 
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 59e6f44d3a0d..235d39d91107 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -50,9 +50,12 @@
 #define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91_BASE_TCB0)
 
 /* Internal SRAM */
-#define AT91_BASE_SRAM          0x00200000      /* Internal SRAM base address */
+#define AT91_SRAM_BASE          0x00200000      /* Internal SRAM base address */
 #define AT91_SRAM_SIZE          0x00004000      /* Internal SRAM SIZE (16Kb) */
 
+ /* Internal SRAM is mapped below the IO devices */
+#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE)
+
 /* Serial ports */
 #define AT91_NR_UART            5               /* 4 USART3's and one DBGU port */
 
@@ -81,14 +84,14 @@ static inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
         void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
 
-        return readl(addr + reg_offset);
+        return __raw_readl(addr + reg_offset);
 }
 
 static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
 {
         void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
 
-        writel(value, addr + reg_offset);
+        __raw_writel(value, addr + reg_offset);
 }
 #endif
 
diff --git a/include/asm-arm/arch-at91rm9200/io.h b/include/asm-arm/arch-at91rm9200/io.h
index 23e670d85c9d..88fd1bebcef3 100644
--- a/include/asm-arm/arch-at91rm9200/io.h
+++ b/include/asm-arm/arch-at91rm9200/io.h
@@ -21,7 +21,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#include <asm/arch/at91rm9200.h>
 #include <asm/io.h>
 
 #define IO_SPACE_LIMIT          0xFFFFFFFF
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index 27b0497f1b36..2dc93b174a8f 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -37,8 +37,6 @@
  * symbols in gpio.h for ones handled indirectly as GPIOs.
  * We make provision for 4 banks of GPIO.
  */
-#include <asm/arch/gpio.h>
-
 #define NR_IRQS         (NR_AIC_IRQS + (4 * 32))
 
 
diff --git a/include/asm-arm/arch-at91rm9200/pio.h b/include/asm-arm/arch-at91rm9200/pio.h
deleted file mode 100644
index a89501b4a703..000000000000
--- a/include/asm-arm/arch-at91rm9200/pio.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * include/asm-arm/arch-at91rm9200/pio.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_PIO_H
-#define __ASM_ARCH_PIO_H
-
-#include <asm/arch/hardware.h>
-
-static inline void AT91_CfgPIO_USART0(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0);
-
-        /*
-         * Errata #39 - RTS0 is not internally connected to PA21.  We need to drive
-         *  the pin manually.  Default is off (RTS is active low).
-         */
-        at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0);
-        at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0);
-        at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
-}
-
-static inline void AT91_CfgPIO_USART1(void) {
-        at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1
-                        | AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1
-                        | AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1);
-}
-
-static inline void AT91_CfgPIO_USART2(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2);
-}
-
-static inline void AT91_CfgPIO_USART3(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
-        at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
-}
-
-static inline void AT91_CfgPIO_DBGU(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD);
-}
-
-/*
- * Enable the Two-Wire interface.
- */
-static inline void AT91_CfgPIO_TWI(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK);
-        at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK);
-        at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK);           /* open drain */
-}
-
-/*
- * Enable the Serial Peripheral Interface.
- */
-static inline void AT91_CfgPIO_SPI(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK);
-}
-
-static inline void AT91_CfgPIO_SPI_CS0(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0);
-}
-
-static inline void AT91_CfgPIO_SPI_CS1(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1);
-}
-
-static inline void AT91_CfgPIO_SPI_CS2(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2);
-}
-
-static inline void AT91_CfgPIO_SPI_CS3(void) {
-        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3);
-}
-
-/*
- * Select the DataFlash card.
- */
-static inline void AT91_CfgPIO_DataFlashCard(void) {
-        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7));
-        at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7));
-        at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7));
-}
-
-/*
- * Enable NAND Flash (SmartMedia) interface.
- */
-static inline void AT91_CfgPIO_SmartMedia(void) {
-        /* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
-        at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
-        at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
-
-        /* Configure PC2 as input (signal READY of the SmartMedia) */
-        at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD);    /* enable direct output enable */
-        at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD);    /* disable output */
-
-        /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
-        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1));     /* enable direct output enable */
-        at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1));     /* disable output */
-}
-
-static inline int AT91_PIO_SmartMedia_RDY(void) {
-        return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0;
-}
-
-static inline int AT91_PIO_SmartMedia_CardDetect(void) {
-        return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0;
-}
-
-#endif
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h
index 29c42655f05c..945e66507a78 100644
--- a/include/asm-arm/arch-at91rm9200/system.h
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -48,4 +48,12 @@ static inline void arch_reset(char mode)
         at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 
+#define ARCH_ID_AT91RM9200      0x09200080
+#define ARCH_ID_AT91SAM9261     0x019000a0
+
+static inline unsigned long arch_identify(void)
+{
+        return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
+}
+
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
index 34d9718feb90..4c367eb57f47 100644
--- a/include/asm-arm/arch-at91rm9200/vmalloc.h
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -21,6 +21,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END             (AT91_IO_VIRT_BASE & PGDIR_MASK)
+#define VMALLOC_END             (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
 
 #endif
diff --git a/include/asm-arm/mach/serial_at91rm9200.h b/include/asm-arm/mach/serial_at91.h
index 98f4b0cb883c..18bc4e00e475 100644
--- a/include/asm-arm/mach/serial_at91rm9200.h
+++ b/include/asm-arm/mach/serial_at91.h
@@ -1,5 +1,5 @@
 /*
- *  linux/include/asm-arm/mach/serial_at91rm9200.h
+ *  linux/include/asm-arm/mach/serial_at91.h
  *
  *  Based on serial_sa1100.h  by Nicolas Pitre
  *
@@ -15,7 +15,7 @@ struct uart_port;
  * This is a temporary structure for registering these
  * functions; it is intended to be discarded after boot.
  */
-struct at91rm9200_port_fns {
+struct at91_port_fns {
         void    (*set_mctrl)(struct uart_port *, u_int);
         u_int   (*get_mctrl)(struct uart_port *);
         void    (*enable_ms)(struct uart_port *);
@@ -26,11 +26,9 @@ struct at91rm9200_port_fns {
 };
 
 #if defined(CONFIG_SERIAL_AT91)
-void at91_register_uart_fns(struct at91rm9200_port_fns *fns);
-void at91_register_uart(int idx, int port);
+void at91_register_uart_fns(struct at91_port_fns *fns);
 #else
 #define at91_register_uart_fns(fns) do { } while (0)
-#define at91_register_uart(idx,port) do { } while (0)
 #endif