11 files changed, 219 insertions, 7 deletions

diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 2712ba77bb3a..6288fad0dc41 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -47,3 +47,28 @@
                 cmpcs   \irqnr, \irqnr
 
                 .endm
+
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt on the
+                 * controller, since this requires the original irqstat value which
+                 * we won't easily be able to recreate later.
+                 */
+
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                cmpcs   \irqnr, \irqnr
+                .endm
+
+                /* As above, this assumes that irqstat and base are preserved.. */
+
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index ff376494e5b1..c16223c9588d 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -21,6 +21,9 @@
 
 #include <asm/arch/platform.h>
 
+#define IRQ_LOCALTIMER                  29
+#define IRQ_LOCALWDOG                   30
+
 /* 
  *  IRQ interrupts definitions are the same the INT definitions
  *  held within platform.h
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 4b6de13a6b9a..18d7c18b738c 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -203,8 +203,16 @@
         /* Reserved 0x1001A000 - 0x1001FFFF */
 #define REALVIEW_CLCD_BASE            0x10020000        /* CLCD */
 #define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
+#ifndef CONFIG_REALVIEW_MPCORE
 #define REALVIEW_GIC_CPU_BASE         0x10040000        /* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC_DIST_BASE        0x10041000        /* Generic interrupt controller distributor */
+#else
+#define REALVIEW_MPCORE_SCU_BASE        0x10100000      /*  SCU registers */
+#define REALVIEW_GIC_CPU_BASE           0x10100100      /* Generic interrupt controller CPU interface */
+#define REALVIEW_TWD_BASE               0x10100700
+#define REALVIEW_TWD_SIZE               0x00000100
+#define REALVIEW_GIC_DIST_BASE          0x10101000      /* Generic interrupt controller distributor */
+#endif
 #define REALVIEW_SMC_BASE             0x10080000        /* SMC */
         /* Reserved 0x10090000 - 0x100EFFFF */
 
@@ -265,6 +273,7 @@
  *  Interrupts - bit assignment (primary)
  * ------------------------------------------------------------------------
  */
+#ifndef CONFIG_REALVIEW_MPCORE
 #define INT_WDOGINT                     0       /* Watchdog timer */
 #define INT_SOFTINT                     1       /* Software interrupt */
 #define INT_COMMRx                      2       /* Debug Comm Rx interrupt */
@@ -297,6 +306,52 @@
 #define INT_USB                         29      /* USB controller */
 #define INT_TSPENINT                    30      /* Touchscreen pen */
 #define INT_TSKPADINT                   31      /* Touchscreen keypad */
+#else
+#define INT_AACI                        0
+#define INT_TIMERINT0_1                 1
+#define INT_TIMERINT2_3                 2
+#define INT_USB                         3
+#define INT_UARTINT0                    4
+#define INT_UARTINT1                    5
+#define INT_RTCINT                      6
+#define INT_KMI0                        7
+#define INT_KMI1                        8
+#define INT_ETH                         9
+#define INT_EB_IRQ1                     10      /* main GIC */
+#define INT_EB_IRQ2                     11      /* tile GIC */
+#define INT_EB_FIQ1                     12      /* main GIC */
+#define INT_EB_FIQ2                     13      /* tile GIC */
+#define INT_MMCI0A                      14
+#define INT_MMCI0B                      15
+
+#define INT_PMU_CPU0                    17
+#define INT_PMU_CPU1                    18
+#define INT_PMU_CPU2                    19
+#define INT_PMU_CPU3                    20
+#define INT_PMU_SCU0                    21
+#define INT_PMU_SCU1                    22
+#define INT_PMU_SCU2                    23
+#define INT_PMU_SCU3                    24
+#define INT_PMU_SCU4                    25
+#define INT_PMU_SCU5                    26
+#define INT_PMU_SCU6                    27
+#define INT_PMU_SCU7                    28
+
+#define INT_L220_EVENT                  29
+#define INT_L220_SLAVE                  30
+#define INT_L220_DECODE                 31
+
+#define INT_UARTINT2                    -1
+#define INT_UARTINT3                    -1
+#define INT_CLCDINT                     -1
+#define INT_DMAINT                      -1
+#define INT_WDOGINT                     -1
+#define INT_GPIOINT0                    -1
+#define INT_GPIOINT1                    -1
+#define INT_GPIOINT2                    -1
+#define INT_SCIINT                      -1
+#define INT_SSPINT                      -1
+#endif
 
 /* 
  *  Interrupt bit positions
diff --git a/include/asm-arm/arch-realview/smp.h b/include/asm-arm/arch-realview/smp.h
new file mode 100644
index 000000000000..fc87783e8e8b
--- /dev/null
+++ b/include/asm-arm/arch-realview/smp.h
@@ -0,0 +1,31 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+#include <linux/config.h>
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id()                 \
+        ({                                              \
+                unsigned int cpunum;                    \
+                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
+                        : "=r" (cpunum));               \
+                cpunum &= 0x0F;                         \
+        })
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(cpumask_t callmap)
+{
+        gic_raise_softirq(callmap, 1);
+}
+
+/*
+ * Do nothing on MPcore.
+ */
+static inline void smp_cross_call_done(cpumask_t callmap)
+{
+}
+
+#endif
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index d7a4a8354fa9..ddd1578a7ee0 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -116,6 +116,8 @@ putstr(const char *ptr)
         }
 }
 
+#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
+
 /* CONFIG_S3C2410_BOOT_WATCHDOG
  *
  * Simple boot-time watchdog setup, to reboot the system if there is
@@ -126,8 +128,6 @@ putstr(const char *ptr)
 
 #define WDOG_COUNT (0xff00)
 
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
-
 static inline void arch_decomp_wdog(void)
 {
         __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
@@ -145,6 +145,24 @@ static void arch_decomp_wdog_start(void)
 #define arch_decomp_wdog()
 #endif
 
+#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
+
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+
+        while(1);
+}
+
+#define arch_error arch_decomp_error
+#endif
+
 static void error(char *err);
 
 static void
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index 69a28f96bee2..f31ac92b6c7f 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -83,10 +83,13 @@
  * Save the current IRQ state and disable IRQs.  Note that this macro
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
-        .macro  save_and_disable_irqs, oldcpsr, temp
+        .macro  save_and_disable_irqs, oldcpsr
         mrs     \oldcpsr, cpsr
-        mov     \temp, #PSR_I_BIT | MODE_SVC
-        msr     cpsr_c, \temp
+#if __LINUX_ARM_ARCH__ >= 6
+        cpsid   i
+#else
+        msr     cpsr_c, #PSR_I_BIT | MODE_SVC
+#endif
         .endm
 
 /*
diff --git a/include/asm-arm/hardirq.h b/include/asm-arm/hardirq.h
index e5ccb6b8ff83..1cbb173bf5b1 100644
--- a/include/asm-arm/hardirq.h
+++ b/include/asm-arm/hardirq.h
@@ -8,6 +8,7 @@
 
 typedef struct {
         unsigned int __softirq_pending;
+        unsigned int local_timer_irqs;
 } ____cacheline_aligned irq_cpustat_t;
 
 #include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h
new file mode 100644
index 000000000000..9903f60c84b7
--- /dev/null
+++ b/include/asm-arm/hardware/arm_scu.h
@@ -0,0 +1,13 @@
+#ifndef ASMARM_HARDWARE_ARM_SCU_H
+#define ASMARM_HARDWARE_ARM_SCU_H
+
+/*
+ * SCU registers
+ */
+#define SCU_CTRL                0x00
+#define SCU_CONFIG              0x04
+#define SCU_CPU_STATUS          0x08
+#define SCU_INVALIDATE          0x0c
+#define SCU_FPGA_REVISION       0x10
+
+#endif
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
index a8f1013930e3..d37bf7443264 100644
--- a/include/asm-arm/hardware/scoop.h
+++ b/include/asm-arm/hardware/scoop.h
@@ -52,8 +52,14 @@ struct scoop_pcmcia_dev {
         unsigned char keep_rd;
 };
 
-extern int scoop_num;
-extern struct scoop_pcmcia_dev *scoop_devs;
+struct scoop_pcmcia_config {
+        struct scoop_pcmcia_dev *devs;
+        int num_devs;
+        void (*pcmcia_init)(void);
+        void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
+};
+
+extern struct scoop_pcmcia_config *platform_scoop_config;
 
 void reset_scoop(struct device *dev);
 unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h
index cd57436d9874..05b029ef6371 100644
--- a/include/asm-arm/mach/flash.h
+++ b/include/asm-arm/mach/flash.h
@@ -11,6 +11,7 @@
 #define ASMARM_MACH_FLASH_H
 
 struct mtd_partition;
+struct mtd_info;
 
 /*
  * map_name:    the map probe function name
@@ -19,6 +20,7 @@ struct mtd_partition;
  * init:        method called at driver/device initialisation
  * exit:        method called at driver/device removal
  * set_vpp:     method called to enable or disable VPP
+ * mmcontrol:   method called to enable or disable Sync. Burst Read in OneNAND
  * parts:       optional array of mtd_partitions for static partitioning
  * nr_parts:    number of mtd_partitions for static partitoning
  */
@@ -29,6 +31,7 @@ struct flash_platform_data {
         int             (*init)(void);
         void            (*exit)(void);
         void            (*set_vpp)(int on);
+        void            (*mmcontrol)(struct mtd_info *mtd, int sync_read);
         struct mtd_partition *parts;
         unsigned int    nr_parts;
 };
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index 551cd3c3093c..5a72e50ca9fc 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -37,6 +37,11 @@ struct seq_file;
 extern void show_ipi_list(struct seq_file *p);
 
 /*
+ * Called from assembly code, this handles an IPI.
+ */
+asmlinkage void do_IPI(struct pt_regs *regs);
+
+/*
  * Move global data into per-processor storage.
  */
 extern void smp_store_cpu_info(unsigned int cpuid);
@@ -47,12 +52,23 @@ extern void smp_store_cpu_info(unsigned int cpuid);
 extern void smp_cross_call(cpumask_t callmap);
 
 /*
+ * Broadcast a timer interrupt to the other CPUs.
+ */
+extern void smp_send_timer(void);
+
+/*
  * Boot a secondary CPU, and assign it the specified idle task.
  * This also gives us the initial stack to use for this CPU.
  */
 extern int boot_secondary(unsigned int cpu, struct task_struct *);
 
 /*
+ * Called from platform specific assembly code, this is the
+ * secondary CPU entry point.
+ */
+asmlinkage void secondary_start_kernel(void);
+
+/*
  * Perform platform specific initialisation of the specified CPU.
  */
 extern void platform_secondary_init(unsigned int cpu);
@@ -76,4 +92,42 @@ extern void platform_cpu_die(unsigned int cpu);
 extern int platform_cpu_kill(unsigned int cpu);
 extern void platform_cpu_enable(unsigned int cpu);
 
+#ifdef CONFIG_LOCAL_TIMERS
+/*
+ * Setup a local timer interrupt for a CPU.
+ */
+extern void local_timer_setup(unsigned int cpu);
+
+/*
+ * Stop a local timer interrupt.
+ */
+extern void local_timer_stop(unsigned int cpu);
+
+/*
+ * Platform provides this to acknowledge a local timer IRQ
+ */
+extern int local_timer_ack(void);
+
+#else
+
+static inline void local_timer_setup(unsigned int cpu)
+{
+}
+
+static inline void local_timer_stop(unsigned int cpu)
+{
+}
+
+#endif
+
+/*
+ * show local interrupt info
+ */
+extern void show_local_irqs(struct seq_file *);
+
+/*
+ * Called from assembly, this is the local timer IRQ handler
+ */
+asmlinkage void do_local_timer(struct pt_regs *);
+
 #endif /* ifndef __ASM_ARM_SMP_H */