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-rw-r--r--include/asm-arm/arch-s3c2410/fb.h69
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h17
2 files changed, 86 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
new file mode 100644
index 000000000000..ac57bc887d82
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -0,0 +1,69 @@
1/* linux/include/asm/arch-s3c2410/fb.h
2 *
3 * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 * Inspired by pxafb.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *
12 * Changelog:
13 * 07-Sep-2004 RTP Created file
14 * 03-Nov-2004 BJD Updated and minor cleanups
15 * 03-Aug-2005 RTP Renamed to fb.h
16*/
17
18#ifndef __ASM_ARM_FB_H
19#define __ASM_ARM_FB_H
20
21#include <asm/arch/regs-lcd.h>
22
23struct s3c2410fb_val {
24 unsigned int defval;
25 unsigned int min;
26 unsigned int max;
27};
28
29struct s3c2410fb_hw {
30 unsigned long lcdcon1;
31 unsigned long lcdcon2;
32 unsigned long lcdcon3;
33 unsigned long lcdcon4;
34 unsigned long lcdcon5;
35};
36
37struct s3c2410fb_mach_info {
38 unsigned char fixed_syncs; /* do not update sync/border */
39
40 /* Screen size */
41 int width;
42 int height;
43
44 /* Screen info */
45 struct s3c2410fb_val xres;
46 struct s3c2410fb_val yres;
47 struct s3c2410fb_val bpp;
48
49 /* lcd configuration registers */
50 struct s3c2410fb_hw regs;
51
52 /* GPIOs */
53
54 unsigned long gpcup;
55 unsigned long gpcup_mask;
56 unsigned long gpccon;
57 unsigned long gpccon_mask;
58 unsigned long gpdup;
59 unsigned long gpdup_mask;
60 unsigned long gpdcon;
61 unsigned long gpdcon_mask;
62
63 /* lpc3600 control register */
64 unsigned long lpcsel;
65};
66
67void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
68
69#endif /* __ASM_ARM_FB_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index 7f882ea92b2a..b6b1b4e8bbeb 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -51,21 +51,32 @@
51 51
52#define S3C2410_LCDCON1_ENVID (1) 52#define S3C2410_LCDCON1_ENVID (1)
53 53
54#define S3C2410_LCDCON1_MODEMASK 0x1E
55
54#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) 56#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
55#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) 57#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
56#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) 58#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
57#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) 59#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
58 60
61#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
62#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
63#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
64
59#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) 65#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
60#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) 66#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
61#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) 67#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
62#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) 68#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
63#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) 69#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
64 70
71#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
72#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
73
65#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) 74#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
66#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) 75#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
67#define S3C2410_LCDCON4_WLH(x) ((x) << 0) 76#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
68 77
78#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
79
69#define S3C2410_LCDCON5_BPP24BL (1<<12) 80#define S3C2410_LCDCON5_BPP24BL (1<<12)
70#define S3C2410_LCDCON5_FRM565 (1<<11) 81#define S3C2410_LCDCON5_FRM565 (1<<11)
71#define S3C2410_LCDCON5_INVVCLK (1<<10) 82#define S3C2410_LCDCON5_INVVCLK (1<<10)
@@ -100,10 +111,16 @@
100#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) 111#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
101#define S3C2410_TPAL S3C2410_LCDREG(0x50) 112#define S3C2410_TPAL S3C2410_LCDREG(0x50)
102 113
114#define S3C2410_TPAL_EN (1<<24)
115
103/* interrupt info */ 116/* interrupt info */
104#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) 117#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
105#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) 118#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
106#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) 119#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
120#define S3C2410_LCDINT_FIWSEL (1<<2)
121#define S3C2410_LCDINT_FRSYNC (1<<1)
122#define S3C2410_LCDINT_FICNT (1<<0)
123
107#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) 124#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
108 125
109#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) 126#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))