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-rw-r--r--include/asm-arm/arch-at91/at91sam9rl.h110
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl_matrix.h96
-rw-r--r--include/asm-arm/arch-at91/cpu.h9
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h5
5 files changed, 222 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
new file mode 100644
index 000000000000..8a9708a370c6
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -0,0 +1,110 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9260.h
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Common definitions.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_H
15#define AT91SAM9RL_H
16
17/*
18 * Peripheral identifiers/interrupts.
19 */
20#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
21#define AT91_ID_SYS 1 /* System Controller */
22#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
23#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
24#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
25#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
26#define AT91SAM9RL_ID_US0 6 /* USART 0 */
27#define AT91SAM9RL_ID_US1 7 /* USART 1 */
28#define AT91SAM9RL_ID_US2 8 /* USART 2 */
29#define AT91SAM9RL_ID_US3 9 /* USART 3 */
30#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
31#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
32#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
33#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
34#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
37#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
38#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
39#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
40#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
41#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
42#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
43#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
44#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
45#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
46
47
48/*
49 * User Peripheral physical base addresses.
50 */
51#define AT91SAM9RL_BASE_TCB0 0xfffa0000
52#define AT91SAM9RL_BASE_TC0 0xfffa0000
53#define AT91SAM9RL_BASE_TC1 0xfffa0040
54#define AT91SAM9RL_BASE_TC2 0xfffa0080
55#define AT91SAM9RL_BASE_MCI 0xfffa4000
56#define AT91SAM9RL_BASE_TWI0 0xfffa8000
57#define AT91SAM9RL_BASE_TWI1 0xfffac000
58#define AT91SAM9RL_BASE_US0 0xfffb0000
59#define AT91SAM9RL_BASE_US1 0xfffb4000
60#define AT91SAM9RL_BASE_US2 0xfffb8000
61#define AT91SAM9RL_BASE_US3 0xfffbc000
62#define AT91SAM9RL_BASE_SSC0 0xfffc0000
63#define AT91SAM9RL_BASE_SSC1 0xfffc4000
64#define AT91SAM9RL_BASE_PWMC 0xfffc8000
65#define AT91SAM9RL_BASE_SPI 0xfffcc000
66#define AT91SAM9RL_BASE_TSC 0xfffd0000
67#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
68#define AT91SAM9RL_BASE_AC97C 0xfffd8000
69#define AT91_BASE_SYS 0xffffc000
70
71
72/*
73 * System Peripherals (offset from AT91_BASE_SYS)
74 */
75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
77#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
81#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
82#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
83#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
84#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
85#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
86#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
87#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
88#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
89#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
90#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
91#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
92#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
93#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
96
97
98/*
99 * Internal Memory.
100 */
101#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
102#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
103
104#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
105#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
106
107#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
108#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
109
110#endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
new file mode 100644
index 000000000000..b15f11b7c08d
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -0,0 +1,96 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9rl_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_MATRIX_H
15#define AT91SAM9RL_MATRIX_H
16
17#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
18#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
19#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
20#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
21#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
22#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
24#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
25#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
26#define AT91_MATRIX_ULBT_FOUR (2 << 0)
27#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
29
30#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
31#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
32#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
33#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
34#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
35#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
55#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
58
59#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
62#define AT91_MATRIX_RCB2 (1 << 2)
63#define AT91_MATRIX_RCB3 (1 << 3)
64#define AT91_MATRIX_RCB4 (1 << 4)
65#define AT91_MATRIX_RCB5 (1 << 5)
66
67#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
69#define AT91_MATRIX_ITCM_0 (0 << 0)
70#define AT91_MATRIX_ITCM_16 (5 << 0)
71#define AT91_MATRIX_ITCM_32 (6 << 0)
72#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
73#define AT91_MATRIX_DTCM_0 (0 << 4)
74#define AT91_MATRIX_DTCM_16 (5 << 4)
75#define AT91_MATRIX_DTCM_32 (6 << 4)
76
77#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
79#define AT91_MATRIX_CS1A_SMC (0 << 1)
80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
81#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
82#define AT91_MATRIX_CS3A_SMC (0 << 3)
83#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
84#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
85#define AT91_MATRIX_CS4A_SMC (0 << 4)
86#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
87#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
88#define AT91_MATRIX_CS5A_SMC (0 << 5)
89#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
90#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
91#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
92#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
93#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
94
95
96#endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7ef4eebe9f8e..ef93c30a9c5f 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -26,6 +26,8 @@
26#define ARCH_ID_AT91SAM9XE256 0x329a93a0 26#define ARCH_ID_AT91SAM9XE256 0x329a93a0
27#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 27#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
28 28
29#define ARCH_ID_AT91SAM9RL64 0x019b03a0
30
29static inline unsigned long at91_cpu_identify(void) 31static inline unsigned long at91_cpu_identify(void)
30{ 32{
31 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); 33 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
@@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void)
68#define cpu_is_at91sam9263() (0) 70#define cpu_is_at91sam9263() (0)
69#endif 71#endif
70 72
73#ifdef CONFIG_ARCH_AT91SAM9RL
74#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
75#else
76#define cpu_is_at91sam9rl() (0)
77#endif
78
79
71/* 80/*
72 * Since this is ARM, we will never run on any AVR32 CPU. But these 81 * Since this is ARM, we will never run on any AVR32 CPU. But these
73 * definitions may reduce clutter in common drivers. 82 * definitions may reduce clutter in common drivers.
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 28133e0154dd..0e51ad224eaa 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -24,6 +24,8 @@
24#include <asm/arch/at91sam9261.h> 24#include <asm/arch/at91sam9261.h>
25#elif defined(CONFIG_ARCH_AT91SAM9263) 25#elif defined(CONFIG_ARCH_AT91SAM9263)
26#include <asm/arch/at91sam9263.h> 26#include <asm/arch/at91sam9263.h>
27#elif defined(CONFIG_ARCH_AT91SAM9RL)
28#include <asm/arch/at91sam9rl.h>
27#else 29#else
28#error "Unsupported AT91 processor" 30#error "Unsupported AT91 processor"
29#endif 31#endif
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index f41636d607a2..2df1ee12dfb7 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -37,6 +37,11 @@
37#define AT91SAM9_MASTER_CLOCK 99959500 37#define AT91SAM9_MASTER_CLOCK 99959500
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39 39
40#elif defined(CONFIG_ARCH_AT91SAM9RL)
41
42#define AT91SAM9_MASTER_CLOCK 100000000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44
40#endif 45#endif
41 46
42#endif 47#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 17:42:25 -0500