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-rw-r--r--include/asm-arm/arch-iop32x/hardware.h20
-rw-r--r--include/asm-arm/arch-iop32x/iop321.h86
-rw-r--r--include/asm-arm/arch-iop32x/memory.h4
-rw-r--r--include/asm-arm/arch-iop32x/system.h2
-rw-r--r--include/asm-arm/arch-iop33x/hardware.h20
-rw-r--r--include/asm-arm/arch-iop33x/iop331.h96
-rw-r--r--include/asm-arm/arch-iop33x/memory.h4
-rw-r--r--include/asm-arm/arch-iop33x/system.h2
-rw-r--r--include/asm-arm/mach/pci.h8
9 files changed, 14 insertions, 228 deletions
diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h
index 8fb10134a107..16d0630ab252 100644
--- a/include/asm-arm/arch-iop32x/hardware.h
+++ b/include/asm-arm/arch-iop32x/hardware.h
@@ -19,27 +19,11 @@
19 */ 19 */
20 20
21#define pcibios_assign_all_busses() 1 21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000
22 24
23 25
24/* 26/*
25 * The min PCI I/O and MEM space are dependent on what specific
26 * chipset/platform we are running on, so instead of hardcoding with
27 * #ifdefs, we just fill these in the platform level PCI init code.
28 */
29#ifndef __ASSEMBLY__
30extern unsigned long iop3xx_pcibios_min_io;
31extern unsigned long iop3xx_pcibios_min_mem;
32
33extern unsigned int processor_id;
34#endif
35
36/*
37 * We just set these to zero since they are really bogus anyways
38 */
39#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
40#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
41
42/*
43 * Generic chipset bits 27 * Generic chipset bits
44 * 28 *
45 */ 29 */
diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h
index 1a82dd96bf50..e3c85a05e73a 100644
--- a/include/asm-arm/arch-iop32x/iop321.h
+++ b/include/asm-arm/arch-iop32x/iop321.h
@@ -25,27 +25,6 @@
25#endif 25#endif
26 26
27/* 27/*
28 * IOP321 I/O and Mem space regions for PCI autoconfiguration
29 */
30#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
31#define IOP321_PCI_LOWER_IO_PA 0x90000000
32#define IOP321_PCI_LOWER_IO_VA 0xfe000000
33#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
34#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
35#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
36#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
37#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
38
39/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
40#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
41#define IOP321_PCI_LOWER_MEM_PA 0x80000000
42#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
43#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
44#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
45#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
46
47
48/*
49 * IOP321 chipset registers 28 * IOP321 chipset registers
50 */ 29 */
51#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ 30#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
@@ -55,69 +34,6 @@
55/* Reserved 0x00000000 through 0x000000FF */ 34/* Reserved 0x00000000 through 0x000000FF */
56 35
57/* Address Translation Unit 0x00000100 through 0x000001FF */ 36/* Address Translation Unit 0x00000100 through 0x000001FF */
58#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100)
59#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102)
60#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104)
61#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106)
62#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108)
63#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109)
64#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C)
65#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D)
66#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E)
67#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F)
68#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110)
69#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114)
70#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118)
71#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
72#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120)
73#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124)
74#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
75#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
76#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130)
77/* Reserved 0x00000134 through 0x0000013B */
78#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C)
79#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D)
80#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E)
81#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F)
82#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140)
83#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144)
84#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148)
85#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
86#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150)
87#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154)
88#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158)
89#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
90#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160)
91#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164)
92#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168)
93#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
94/* Reserved 0x00000170 through 0x00000177*/
95#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178)
96/* Reserved 0x0000017C through 0x0000017F*/
97#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180)
98#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184)
99#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188)
100#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
101#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190)
102#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194)
103#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198)
104#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
105/* Reserved 0x000001A0 through 0x000001A3*/
106#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
107/* Reserved 0x000001A8 through 0x000001AB*/
108#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
109/* Reserved 0x000001B0 through 0x000001BB*/
110#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
111#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0)
112#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1)
113#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
114#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
115/* Reserved 0x000001C6 through 0x000001DF */
116#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0)
117#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1)
118#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
119#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
120#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
121 37
122/* Messaging Unit 0x00000300 through 0x000003FF */ 38/* Messaging Unit 0x00000300 through 0x000003FF */
123 39
@@ -317,6 +233,8 @@
317 233
318/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ 234/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
319 235
236#include <asm/hardware/iop3xx.h>
237
320 238
321#ifndef __ASSEMBLY__ 239#ifndef __ASSEMBLY__
322extern void iop321_init_irq(void); 240extern void iop321_init_irq(void);
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
index b4073f15b405..4c64d9e7229b 100644
--- a/include/asm-arm/arch-iop32x/memory.h
+++ b/include/asm-arm/arch-iop32x/memory.h
@@ -20,8 +20,8 @@
20 * to an address that the kernel can use. 20 * to an address that the kernel can use.
21 */ 21 */
22 22
23#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) 23#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
24#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) 24#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
25 25
26 26
27#endif 27#endif
diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h
index d4c8d691e1b0..1ac207a0d52e 100644
--- a/include/asm-arm/arch-iop32x/system.h
+++ b/include/asm-arm/arch-iop32x/system.h
@@ -16,7 +16,7 @@ static inline void arch_idle(void)
16 16
17static inline void arch_reset(char mode) 17static inline void arch_reset(char mode)
18{ 18{
19 *IOP321_PCSR = 0x30; 19 *IOP3XX_PCSR = 0x30;
20 20
21 if ( 1 && mode == 's') { 21 if ( 1 && mode == 's') {
22 /* Jump into ROM at address 0 */ 22 /* Jump into ROM at address 0 */
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h
index 4a457084c5c6..5e3cb32af020 100644
--- a/include/asm-arm/arch-iop33x/hardware.h
+++ b/include/asm-arm/arch-iop33x/hardware.h
@@ -19,27 +19,11 @@
19 */ 19 */
20 20
21#define pcibios_assign_all_busses() 1 21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000
22 24
23 25
24/* 26/*
25 * The min PCI I/O and MEM space are dependent on what specific
26 * chipset/platform we are running on, so instead of hardcoding with
27 * #ifdefs, we just fill these in the platform level PCI init code.
28 */
29#ifndef __ASSEMBLY__
30extern unsigned long iop3xx_pcibios_min_io;
31extern unsigned long iop3xx_pcibios_min_mem;
32
33extern unsigned int processor_id;
34#endif
35
36/*
37 * We just set these to zero since they are really bogus anyways
38 */
39#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
40#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
41
42/*
43 * Generic chipset bits 27 * Generic chipset bits
44 * 28 *
45 */ 29 */
diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h
index a7f47122c5e1..e85e1a2e1a86 100644
--- a/include/asm-arm/arch-iop33x/iop331.h
+++ b/include/asm-arm/arch-iop33x/iop331.h
@@ -24,27 +24,6 @@
24#endif 24#endif
25 25
26/* 26/*
27 * IOP331 I/O and Mem space regions for PCI autoconfiguration
28 */
29#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
30#define IOP331_PCI_LOWER_IO_PA 0x90000000
31#define IOP331_PCI_LOWER_IO_VA 0xfe000000
32#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
33#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
34#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
35#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
36#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
37
38/* this can be 128M if OMWTVR1 is set */
39#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
40/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */
41#define IOP331_PCI_LOWER_MEM_PA 0x80000000
42#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
43#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
44#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
45#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
46
47/*
48 * IOP331 chipset registers 27 * IOP331 chipset registers
49 */ 28 */
50#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ 29#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
@@ -54,79 +33,6 @@
54/* Reserved 0x00000000 through 0x000000FF */ 33/* Reserved 0x00000000 through 0x000000FF */
55 34
56/* Address Translation Unit 0x00000100 through 0x000001FF */ 35/* Address Translation Unit 0x00000100 through 0x000001FF */
57#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
58#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
59#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
60#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
61#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
62#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
63#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
64#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
65#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
66#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
67#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
68#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
69#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
70#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
71#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
72#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
73#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
74#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
75#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
76#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
77/* Reserved 0x00000138 through 0x0000013B */
78#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
79#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
80#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
81#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
82#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
83#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
84#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
85#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
86#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
87#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
88#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
89#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
90#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
91#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
92#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
93#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
94/* Reserved 0x00000170 through 0x00000177*/
95#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
96/* Reserved 0x0000017C through 0x0000017F*/
97#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
98#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
99#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
100#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
101#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
102#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
103#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
104#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
105/* Reserved 0x000001A0 through 0x000001A3*/
106#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
107/* Reserved 0x000001A8 through 0x000001AB*/
108#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
109/* Reserved 0x000001B0 through 0x000001BB*/
110#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
111#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
112#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
113#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
114#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
115#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
116#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
117#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
118/* Reserved 0x000001C6 through 0x000001CF */
119#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
120#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
121#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
122#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
123#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
124#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
125#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
126#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
127#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
128#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
129#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
130 36
131/* Messaging Unit 0x00000300 through 0x000003FF */ 37/* Messaging Unit 0x00000300 through 0x000003FF */
132 38
@@ -332,6 +238,8 @@
332 238
333/* Reserved 0x0000178c through 0x000019ff */ 239/* Reserved 0x0000178c through 0x000019ff */
334 240
241#include <asm/hardware/iop3xx.h>
242
335 243
336#ifndef __ASSEMBLY__ 244#ifndef __ASSEMBLY__
337extern void iop331_init_irq(void); 245extern void iop331_init_irq(void);
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
index 5e47164934ce..de208d2cca4e 100644
--- a/include/asm-arm/arch-iop33x/memory.h
+++ b/include/asm-arm/arch-iop33x/memory.h
@@ -19,8 +19,8 @@
19 * bus_to_virt: Used to convert an address for DMA operations 19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use. 20 * to an address that the kernel can use.
21 */ 21 */
22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0)) 22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2))) 23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
24 24
25 25
26#endif 26#endif
diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h
index 43cc787ea629..8270ad9f86c8 100644
--- a/include/asm-arm/arch-iop33x/system.h
+++ b/include/asm-arm/arch-iop33x/system.h
@@ -16,7 +16,7 @@ static inline void arch_idle(void)
16 16
17static inline void arch_reset(char mode) 17static inline void arch_reset(char mode)
18{ 18{
19 *IOP331_PCSR = 0x30; 19 *IOP3XX_PCSR = 0x30;
20 20
21 if ( 1 && mode == 's') { 21 if ( 1 && mode == 's') {
22 /* Jump into ROM at address 0 */ 22 /* Jump into ROM at address 0 */
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
index cb41defad4a1..24621c49a0c7 100644
--- a/include/asm-arm/mach/pci.h
+++ b/include/asm-arm/mach/pci.h
@@ -56,14 +56,6 @@ extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
56extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); 56extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
57extern void iop3xx_pci_preinit(void); 57extern void iop3xx_pci_preinit(void);
58 58
59extern int iop321_setup(int nr, struct pci_sys_data *);
60extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
61extern void iop321_init(void);
62
63extern int iop331_setup(int nr, struct pci_sys_data *);
64extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
65extern void iop331_init(void);
66
67extern int dc21285_setup(int nr, struct pci_sys_data *); 59extern int dc21285_setup(int nr, struct pci_sys_data *);
68extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); 60extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
69extern void dc21285_preinit(void); 61extern void dc21285_preinit(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 01:41:57 -0500