diff options
Diffstat (limited to 'include/asm-arm')
60 files changed, 3112 insertions, 740 deletions
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h index 24b51cccde8f..9eceb4148922 100644 --- a/include/asm-arm/arch-aaec2000/memory.h +++ b/include/asm-arm/arch-aaec2000/memory.h | |||
| @@ -17,8 +17,6 @@ | |||
| 17 | #define __virt_to_bus(x) __virt_to_phys(x) | 17 | #define __virt_to_bus(x) __virt_to_phys(x) |
| 18 | #define __bus_to_virt(x) __phys_to_virt(x) | 18 | #define __bus_to_virt(x) __phys_to_virt(x) |
| 19 | 19 | ||
| 20 | #ifdef CONFIG_DISCONTIGMEM | ||
| 21 | |||
| 22 | /* | 20 | /* |
| 23 | * The nodes are the followings: | 21 | * The nodes are the followings: |
| 24 | * | 22 | * |
| @@ -27,42 +25,6 @@ | |||
| 27 | * node 2: 0xf800.0000 - 0xfbff.ffff | 25 | * node 2: 0xf800.0000 - 0xfbff.ffff |
| 28 | * node 3: 0xfc00.0000 - 0xffff.ffff | 26 | * node 3: 0xfc00.0000 - 0xffff.ffff |
| 29 | */ | 27 | */ |
| 30 | 28 | #define NODE_MEM_SIZE_BITS 26 | |
| 31 | /* | ||
| 32 | * Given a kernel address, find the home node of the underlying memory. | ||
| 33 | */ | ||
| 34 | #define KVADDR_TO_NID(addr) \ | ||
| 35 | (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT) | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Given a page frame number, convert it to a node id. | ||
| 39 | */ | ||
| 40 | #define PFN_TO_NID(pfn) \ | ||
| 41 | (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT)) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory | ||
| 45 | * and return the mem_map of that node. | ||
| 46 | */ | ||
| 47 | #define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Given a page frame number, find the owning node of the memory | ||
| 51 | * and return the mem_map of that node. | ||
| 52 | */ | ||
| 53 | #define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | ||
| 57 | * and returns the index corresponding to the appropriate page in the | ||
| 58 | * node's mem_map. | ||
| 59 | */ | ||
| 60 | #define LOCAL_MAP_NR(addr) \ | ||
| 61 | (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT) | ||
| 62 | |||
| 63 | #define NODE_MAX_MEM_SHIFT 26 | ||
| 64 | #define NODE_MAX_MEM_SIZE (1 << NODE_MAX_MEM_SHIFT) | ||
| 65 | |||
| 66 | #endif /* CONFIG_DISCONTIGMEM */ | ||
| 67 | 29 | ||
| 68 | #endif /* __ASM_ARCH_MEMORY_H */ | 30 | #endif /* __ASM_ARCH_MEMORY_H */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91_aic.h b/include/asm-arm/arch-at91rm9200/at91_aic.h new file mode 100644 index 000000000000..267e69812e26 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_aic.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_aic.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Advanced Interrupt Controller (AIC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_AIC_H | ||
| 17 | #define AT91_AIC_H | ||
| 18 | |||
| 19 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ | ||
| 20 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | ||
| 21 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | ||
| 22 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | ||
| 23 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) | ||
| 24 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) | ||
| 25 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | ||
| 26 | |||
| 27 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | ||
| 28 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ | ||
| 29 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ | ||
| 30 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ | ||
| 31 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | ||
| 32 | |||
| 33 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ | ||
| 34 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ | ||
| 35 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ | ||
| 36 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | ||
| 37 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | ||
| 38 | |||
| 39 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ | ||
| 40 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ | ||
| 41 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ | ||
| 42 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ | ||
| 43 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ | ||
| 44 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ | ||
| 45 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ | ||
| 46 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | ||
| 47 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | ||
| 48 | |||
| 49 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ | ||
| 50 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ | ||
| 51 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_dbgu.h b/include/asm-arm/arch-at91rm9200/at91_dbgu.h new file mode 100644 index 000000000000..e4b8b27acfca --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_dbgu.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_dbgu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Debug Unit (DBGU) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_DBGU_H | ||
| 17 | #define AT91_DBGU_H | ||
| 18 | |||
| 19 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
| 20 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
| 21 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
| 22 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
| 23 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
| 24 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
| 25 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
| 26 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
| 27 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
| 28 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
| 29 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
| 30 | |||
| 31 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
| 32 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
| 33 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
| 34 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
| 35 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
| 36 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
| 37 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
| 38 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
| 39 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
| 40 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
| 41 | |||
| 42 | #define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ | ||
| 43 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ | ||
| 44 | |||
| 45 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h new file mode 100644 index 000000000000..fddf256a98d3 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_ecc.h | ||
| 3 | * | ||
| 4 | * Error Corrected Code Controller (ECC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_ECC_H | ||
| 14 | #define AT91_ECC_H | ||
| 15 | |||
| 16 | #define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ | ||
| 17 | #define AT91_ECC_RST (1 << 0) /* Reset parity */ | ||
| 18 | |||
| 19 | #define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ | ||
| 20 | #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ | ||
| 21 | #define AT91_ECC_PAGESIZE_528 (0) | ||
| 22 | #define AT91_ECC_PAGESIZE_1056 (1) | ||
| 23 | #define AT91_ECC_PAGESIZE_2112 (2) | ||
| 24 | #define AT91_ECC_PAGESIZE_4224 (3) | ||
| 25 | |||
| 26 | #define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ | ||
| 27 | #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ | ||
| 28 | #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ | ||
| 29 | #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ | ||
| 30 | |||
| 31 | #define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ | ||
| 32 | #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ | ||
| 33 | #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ | ||
| 34 | |||
| 35 | #define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ | ||
| 36 | #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_lcdc.h b/include/asm-arm/arch-at91rm9200/at91_lcdc.h new file mode 100644 index 000000000000..9cbfcdd3c471 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_lcdc.h | |||
| @@ -0,0 +1,148 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_lcdc.h | ||
| 3 | * | ||
| 4 | * LCD Controller (LCDC). | ||
| 5 | * Based on AT91SAM9261 datasheet revision E. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_LCDC_H | ||
| 14 | #define AT91_LCDC_H | ||
| 15 | |||
| 16 | #define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */ | ||
| 17 | #define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */ | ||
| 18 | #define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */ | ||
| 19 | #define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */ | ||
| 20 | #define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */ | ||
| 21 | #define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */ | ||
| 22 | |||
| 23 | #define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */ | ||
| 24 | #define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */ | ||
| 25 | #define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */ | ||
| 26 | |||
| 27 | #define AT91_LCDC_DMACON 0x1c /* DMA Control Register */ | ||
| 28 | #define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */ | ||
| 29 | #define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */ | ||
| 30 | #define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */ | ||
| 31 | |||
| 32 | #define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */ | ||
| 33 | #define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */ | ||
| 34 | #define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */ | ||
| 35 | #define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */ | ||
| 36 | |||
| 37 | #define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */ | ||
| 38 | #define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */ | ||
| 39 | #define AT91_LCDC_DISTYPE_STNMONO (0 << 0) | ||
| 40 | #define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0) | ||
| 41 | #define AT91_LCDC_DISTYPE_TFT (2 << 0) | ||
| 42 | #define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */ | ||
| 43 | #define AT91_LCDC_SCANMOD_SINGLE (0 << 2) | ||
| 44 | #define AT91_LCDC_SCANMOD_DUAL (1 << 2) | ||
| 45 | #define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */ | ||
| 46 | #define AT91_LCDC_IFWIDTH_4 (0 << 3) | ||
| 47 | #define AT91_LCDC_IFWIDTH_8 (1 << 3) | ||
| 48 | #define AT91_LCDC_IFWIDTH_16 (2 << 3) | ||
| 49 | #define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */ | ||
| 50 | #define AT91_LCDC_PIXELSIZE_1 (0 << 5) | ||
| 51 | #define AT91_LCDC_PIXELSIZE_2 (1 << 5) | ||
| 52 | #define AT91_LCDC_PIXELSIZE_4 (2 << 5) | ||
| 53 | #define AT91_LCDC_PIXELSIZE_8 (3 << 5) | ||
| 54 | #define AT91_LCDC_PIXELSIZE_16 (4 << 5) | ||
| 55 | #define AT91_LCDC_PIXELSIZE_24 (5 << 5) | ||
| 56 | #define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */ | ||
| 57 | #define AT91_LCDC_INVVD_NORMAL (0 << 8) | ||
| 58 | #define AT91_LCDC_INVVD_INVERTED (1 << 8) | ||
| 59 | #define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */ | ||
| 60 | #define AT91_LCDC_INVFRAME_NORMAL (0 << 9) | ||
| 61 | #define AT91_LCDC_INVFRAME_INVERTED (1 << 9) | ||
| 62 | #define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */ | ||
| 63 | #define AT91_LCDC_INVLINE_NORMAL (0 << 10) | ||
| 64 | #define AT91_LCDC_INVLINE_INVERTED (1 << 10) | ||
| 65 | #define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */ | ||
| 66 | #define AT91_LCDC_INVCLK_NORMAL (0 << 11) | ||
| 67 | #define AT91_LCDC_INVCLK_INVERTED (1 << 11) | ||
| 68 | #define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */ | ||
| 69 | #define AT91_LCDC_INVDVAL_NORMAL (0 << 12) | ||
| 70 | #define AT91_LCDC_INVDVAL_INVERTED (1 << 12) | ||
| 71 | #define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */ | ||
| 72 | #define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) | ||
| 73 | #define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) | ||
| 74 | #define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */ | ||
| 75 | #define AT91_LCDC_MEMOR_BIG (0 << 31) | ||
| 76 | #define AT91_LCDC_MEMOR_LITTLE (1 << 31) | ||
| 77 | |||
| 78 | #define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */ | ||
| 79 | #define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */ | ||
| 80 | #define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */ | ||
| 81 | #define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */ | ||
| 82 | #define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */ | ||
| 83 | |||
| 84 | #define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */ | ||
| 85 | #define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */ | ||
| 86 | #define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */ | ||
| 87 | #define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */ | ||
| 88 | |||
| 89 | #define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */ | ||
| 90 | #define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */ | ||
| 91 | #define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */ | ||
| 92 | |||
| 93 | #define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */ | ||
| 94 | #define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */ | ||
| 95 | |||
| 96 | #define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */ | ||
| 97 | #define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */ | ||
| 98 | #define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */ | ||
| 99 | #define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */ | ||
| 100 | #define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */ | ||
| 101 | #define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */ | ||
| 102 | #define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */ | ||
| 103 | #define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */ | ||
| 104 | #define AT91_LCDC_DP1_2_VAL (0xff) | ||
| 105 | #define AT91_LCDC_DP4_7_VAL (0xfffffff) | ||
| 106 | #define AT91_LCDC_DP3_5_VAL (0xfffff) | ||
| 107 | #define AT91_LCDC_DP2_3_VAL (0xfff) | ||
| 108 | #define AT91_LCDC_DP5_7_VAL (0xfffffff) | ||
| 109 | #define AT91_LCDC_DP3_4_VAL (0xffff) | ||
| 110 | #define AT91_LCDC_DP4_5_VAL (0xfffff) | ||
| 111 | #define AT91_LCDC_DP6_7_VAL (0xfffffff) | ||
| 112 | |||
| 113 | #define AT91_LCDC_PWRCON 0x083c /* Power Control Register */ | ||
| 114 | #define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */ | ||
| 115 | #define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */ | ||
| 116 | #define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */ | ||
| 117 | |||
| 118 | #define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */ | ||
| 119 | #define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */ | ||
| 120 | #define AT91_LCDC_PS_DIV1 (0 << 0) | ||
| 121 | #define AT91_LCDC_PS_DIV2 (1 << 0) | ||
| 122 | #define AT91_LCDC_PS_DIV4 (2 << 0) | ||
| 123 | #define AT91_LCDC_PS_DIV8 (3 << 0) | ||
| 124 | #define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */ | ||
| 125 | #define AT91_LCDC_POL_NEGATIVE (0 << 2) | ||
| 126 | #define AT91_LCDC_POL_POSITIVE (1 << 2) | ||
| 127 | #define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */ | ||
| 128 | #define AT91_LCDC_ENA_PWMDISABLE (0 << 3) | ||
| 129 | #define AT91_LCDC_ENA_PWMENABLE (1 << 3) | ||
| 130 | |||
| 131 | #define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */ | ||
| 132 | #define AT91_LCDC_CVAL (0xff) /* PWM compare value */ | ||
| 133 | |||
| 134 | #define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */ | ||
| 135 | #define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */ | ||
| 136 | #define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */ | ||
| 137 | #define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */ | ||
| 138 | #define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */ | ||
| 139 | #define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */ | ||
| 140 | #define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */ | ||
| 141 | #define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */ | ||
| 142 | #define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */ | ||
| 143 | #define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */ | ||
| 144 | #define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */ | ||
| 145 | |||
| 146 | #define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */ | ||
| 147 | |||
| 148 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h b/include/asm-arm/arch-at91rm9200/at91_mci.h index f28636d61e39..9a552cb743c0 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h +++ b/include/asm-arm/arch-at91rm9200/at91_mci.h | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h | 2 | * include/asm-arm/arch-at91rm9200/at91_mci.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| 6 | * | 6 | * |
| 7 | * MultiMedia Card Interface (MCI) registers. | 7 | * MultiMedia Card Interface (MCI) registers. |
| 8 | * Based on AT91RM9200 datasheet revision E. | 8 | * Based on AT91RM9200 datasheet revision F. |
| 9 | * | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by | 11 | * it under the terms of the GNU General Public License as published by |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_MCI_H | 16 | #ifndef AT91_MCI_H |
| 17 | #define AT91RM9200_MCI_H | 17 | #define AT91_MCI_H |
| 18 | 18 | ||
| 19 | #define AT91_MCI_CR 0x00 /* Control Register */ | 19 | #define AT91_MCI_CR 0x00 /* Control Register */ |
| 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ | 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ |
| @@ -25,10 +25,10 @@ | |||
| 25 | 25 | ||
| 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ | 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ |
| 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ | 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ |
| 28 | #define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */ | 28 | #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ |
| 29 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ | 29 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ |
| 30 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ | 30 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ |
| 31 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ | 31 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ |
| 32 | 32 | ||
| 33 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ | 33 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ |
| 34 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ | 34 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ |
| @@ -43,8 +43,8 @@ | |||
| 43 | #define AT91_MCI_DTOMUL_1M (7 << 4) | 43 | #define AT91_MCI_DTOMUL_1M (7 << 4) |
| 44 | 44 | ||
| 45 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ | 45 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ |
| 46 | #define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */ | 46 | #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ |
| 47 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ | 47 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ |
| 48 | 48 | ||
| 49 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ | 49 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ |
| 50 | 50 | ||
| @@ -78,18 +78,20 @@ | |||
| 78 | 78 | ||
| 79 | #define AT91_MCI_SR 0x40 /* Status Register */ | 79 | #define AT91_MCI_SR 0x40 /* Status Register */ |
| 80 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ | 80 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ |
| 81 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ | 81 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ |
| 82 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ | 82 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ |
| 83 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ | 83 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ |
| 84 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ | 84 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ |
| 85 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ | 85 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ |
| 86 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ | 86 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ |
| 87 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ | 87 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ |
| 88 | #define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ | ||
| 89 | #define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ | ||
| 88 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ | 90 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ |
| 89 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ | 91 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ |
| 90 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ | 92 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ |
| 91 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ | 93 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ |
| 92 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ | 94 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ |
| 93 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ | 95 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ |
| 94 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ | 96 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ |
| 95 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ | 97 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91_pdc.h index ce1150d4438d..79d6e02fa45e 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h +++ b/include/asm-arm/arch-at91rm9200/at91_pdc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h | 2 | * include/asm-arm/arch-at91rm9200/at91_pdc.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_PDC_H | 16 | #ifndef AT91_PDC_H |
| 17 | #define AT91RM9200_PDC_H | 17 | #define AT91_PDC_H |
| 18 | 18 | ||
| 19 | #define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ | 19 | #define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ |
| 20 | #define AT91_PDC_RCR 0x104 /* Receive Counter Register */ | 20 | #define AT91_PDC_RCR 0x104 /* Receive Counter Register */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91_pio.h b/include/asm-arm/arch-at91rm9200/at91_pio.h new file mode 100644 index 000000000000..680eaa1f5915 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_pio.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_pio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Parallel I/O Controller (PIO) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PIO_H | ||
| 17 | #define AT91_PIO_H | ||
| 18 | |||
| 19 | #define PIO_PER 0x00 /* Enable Register */ | ||
| 20 | #define PIO_PDR 0x04 /* Disable Register */ | ||
| 21 | #define PIO_PSR 0x08 /* Status Register */ | ||
| 22 | #define PIO_OER 0x10 /* Output Enable Register */ | ||
| 23 | #define PIO_ODR 0x14 /* Output Disable Register */ | ||
| 24 | #define PIO_OSR 0x18 /* Output Status Register */ | ||
| 25 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | ||
| 26 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | ||
| 27 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | ||
| 28 | #define PIO_SODR 0x30 /* Set Output Data Register */ | ||
| 29 | #define PIO_CODR 0x34 /* Clear Output Data Register */ | ||
| 30 | #define PIO_ODSR 0x38 /* Output Data Status Register */ | ||
| 31 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ | ||
| 32 | #define PIO_IER 0x40 /* Interrupt Enable Register */ | ||
| 33 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ | ||
| 34 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ | ||
| 35 | #define PIO_ISR 0x4c /* Interrupt Status Register */ | ||
| 36 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ | ||
| 37 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | ||
| 38 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ | ||
| 39 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ | ||
| 40 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ | ||
| 41 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ | ||
| 42 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ | ||
| 43 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ | ||
| 44 | #define PIO_ABSR 0x78 /* AB Status Register */ | ||
| 45 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ | ||
| 46 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ | ||
| 47 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_pit.h b/include/asm-arm/arch-at91rm9200/at91_pit.h new file mode 100644 index 000000000000..4a30d009c588 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_pit.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_pit.h | ||
| 3 | * | ||
| 4 | * Periodic Interval Timer (PIT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_PIT_H | ||
| 14 | #define AT91_PIT_H | ||
| 15 | |||
| 16 | #define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ | ||
| 17 | #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ | ||
| 18 | #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ | ||
| 19 | #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ | ||
| 20 | |||
| 21 | #define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ | ||
| 22 | #define AT91_PIT_PITS (1 << 0) /* Timer Status */ | ||
| 23 | |||
| 24 | #define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ | ||
| 25 | #define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ | ||
| 26 | #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ | ||
| 27 | #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h new file mode 100644 index 000000000000..de8c3da74a01 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_pmc.h | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_pmc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Power Management Controller (PMC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PMC_H | ||
| 17 | #define AT91_PMC_H | ||
| 18 | |||
| 19 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | ||
| 20 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | ||
| 21 | |||
| 22 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | ||
| 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
| 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | ||
| 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | ||
| 26 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | ||
| 27 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | ||
| 28 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | ||
| 29 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
| 30 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
| 31 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
| 32 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
| 33 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ | ||
| 34 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | ||
| 35 | |||
| 36 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | ||
| 37 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | ||
| 38 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | ||
| 39 | |||
| 40 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ | ||
| 41 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
| 42 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ | ||
| 43 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 44 | |||
| 45 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | ||
| 46 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
| 47 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
| 48 | |||
| 49 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | ||
| 50 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | ||
| 51 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
| 52 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
| 53 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
| 54 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
| 55 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
| 56 | |||
| 57 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | ||
| 58 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
| 59 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
| 60 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
| 61 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
| 62 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
| 63 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | ||
| 64 | #define AT91_PMC_PRES_1 (0 << 2) | ||
| 65 | #define AT91_PMC_PRES_2 (1 << 2) | ||
| 66 | #define AT91_PMC_PRES_4 (2 << 2) | ||
| 67 | #define AT91_PMC_PRES_8 (3 << 2) | ||
| 68 | #define AT91_PMC_PRES_16 (4 << 2) | ||
| 69 | #define AT91_PMC_PRES_32 (5 << 2) | ||
| 70 | #define AT91_PMC_PRES_64 (6 << 2) | ||
| 71 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
| 72 | #define AT91_PMC_MDIV_1 (0 << 8) | ||
| 73 | #define AT91_PMC_MDIV_2 (1 << 8) | ||
| 74 | #define AT91_PMC_MDIV_3 (2 << 8) | ||
| 75 | #define AT91_PMC_MDIV_4 (3 << 8) | ||
| 76 | |||
| 77 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | ||
| 78 | |||
| 79 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | ||
| 80 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | ||
| 81 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | ||
| 82 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
| 83 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
| 84 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
| 85 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
| 86 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
| 87 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
| 88 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
| 89 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
| 90 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | ||
| 91 | |||
| 92 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h new file mode 100644 index 000000000000..ccdc52da973d --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_rstc.h | ||
| 3 | * | ||
| 4 | * Reset Controller (RSTC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RSTC_H | ||
| 14 | #define AT91_RSTC_H | ||
| 15 | |||
| 16 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | ||
| 17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | ||
| 19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | ||
| 20 | #define AT01_RSTC_KEY (0xff << 24) /* KEY Password */ | ||
| 21 | |||
| 22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | ||
| 23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | ||
| 24 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | ||
| 25 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | ||
| 26 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) | ||
| 27 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) | ||
| 28 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) | ||
| 29 | #define AT91_RSTC_RSTTYP_USER (4 << 8) | ||
| 30 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | ||
| 31 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | ||
| 32 | |||
| 33 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | ||
| 34 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | ||
| 35 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | ||
| 36 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | ||
| 37 | #define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h new file mode 100644 index 000000000000..6e5065d56260 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rtc.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_rtc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Real Time Clock (RTC) - System peripheral registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_RTC_H | ||
| 17 | #define AT91_RTC_H | ||
| 18 | |||
| 19 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ | ||
| 20 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ | ||
| 21 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ | ||
| 22 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ | ||
| 23 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) | ||
| 24 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) | ||
| 25 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) | ||
| 26 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) | ||
| 27 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ | ||
| 28 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) | ||
| 29 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) | ||
| 30 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) | ||
| 31 | |||
| 32 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ | ||
| 33 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ | ||
| 34 | |||
| 35 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ | ||
| 36 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ | ||
| 37 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ | ||
| 38 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ | ||
| 39 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ | ||
| 40 | |||
| 41 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ | ||
| 42 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ | ||
| 43 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ | ||
| 44 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ | ||
| 45 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ | ||
| 46 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ | ||
| 47 | |||
| 48 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ | ||
| 49 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ | ||
| 50 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ | ||
| 51 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ | ||
| 52 | |||
| 53 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ | ||
| 54 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ | ||
| 55 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ | ||
| 56 | |||
| 57 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ | ||
| 58 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ | ||
| 59 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ | ||
| 60 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ | ||
| 61 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ | ||
| 62 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ | ||
| 63 | |||
| 64 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ | ||
| 65 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ | ||
| 66 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ | ||
| 67 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ | ||
| 68 | |||
| 69 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ | ||
| 70 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ | ||
| 71 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ | ||
| 72 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ | ||
| 73 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ | ||
| 74 | |||
| 75 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtt.h b/include/asm-arm/arch-at91rm9200/at91_rtt.h new file mode 100644 index 000000000000..c6751ba3cccc --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rtt.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_rtt.h | ||
| 3 | * | ||
| 4 | * Real-time Timer (RTT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RTT_H | ||
| 14 | #define AT91_RTT_H | ||
| 15 | |||
| 16 | #define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */ | ||
| 17 | #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ | ||
| 18 | #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ | ||
| 19 | #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ | ||
| 20 | #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */ | ||
| 23 | #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ | ||
| 24 | |||
| 25 | #define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */ | ||
| 26 | #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ | ||
| 27 | |||
| 28 | #define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */ | ||
| 29 | #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ | ||
| 30 | #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_shdwc.h b/include/asm-arm/arch-at91rm9200/at91_shdwc.h new file mode 100644 index 000000000000..0439250553c9 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_shdwc.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_shdwc.h | ||
| 3 | * | ||
| 4 | * Shutdown Controller (SHDWC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_SHDWC_H | ||
| 14 | #define AT91_SHDWC_H | ||
| 15 | |||
| 16 | #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ | ||
| 17 | #define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ | ||
| 21 | #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ | ||
| 22 | #define AT91_SHDW_WKMODE0_NONE 0 | ||
| 23 | #define AT91_SHDW_WKMODE0_HIGH 1 | ||
| 24 | #define AT91_SHDW_WKMODE0_LOW 2 | ||
| 25 | #define AT91_SHDW_WKMODE0_ANYLEVEL 3 | ||
| 26 | #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ | ||
| 27 | #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ | ||
| 28 | |||
| 29 | #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ | ||
| 30 | #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ | ||
| 31 | #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91_spi.h index bff5ea45f604..bec48ca89bba 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h +++ b/include/asm-arm/arch-at91rm9200/at91_spi.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h | 2 | * include/asm-arm/arch-at91rm9200/at91_spi.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_SPI_H | 16 | #ifndef AT91_SPI_H |
| 17 | #define AT91RM9200_SPI_H | 17 | #define AT91_SPI_H |
| 18 | 18 | ||
| 19 | #define AT91_SPI_CR 0x00 /* Control Register */ | 19 | #define AT91_SPI_CR 0x00 /* Control Register */ |
| 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ | 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ |
| @@ -28,7 +28,7 @@ | |||
| 28 | #define AT91_SPI_PS_FIXED (0 << 1) | 28 | #define AT91_SPI_PS_FIXED (0 << 1) |
| 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) | 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) |
| 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ | 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ |
| 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */ | 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ |
| 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ | 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ |
| 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ | 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ |
| 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91_ssc.h index ac880227147f..694bcaa8f7c2 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h +++ b/include/asm-arm/arch-at91rm9200/at91_ssc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h | 2 | * include/asm-arm/arch-at91rm9200/at91_ssc.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) SAN People | 4 | * Copyright (C) SAN People |
| 5 | * | 5 | * |
| @@ -12,8 +12,8 @@ | |||
| 12 | * (at your option) any later version. | 12 | * (at your option) any later version. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #ifndef AT91RM9200_SSC_H | 15 | #ifndef AT91_SSC_H |
| 16 | #define AT91RM9200_SSC_H | 16 | #define AT91_SSC_H |
| 17 | 17 | ||
| 18 | #define AT91_SSC_CR 0x00 /* Control Register */ | 18 | #define AT91_SSC_CR 0x00 /* Control Register */ |
| 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ | 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ |
| @@ -36,6 +36,10 @@ | |||
| 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ | 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ |
| 37 | #define AT91_SSC_CKI_FALLING (0 << 5) | 37 | #define AT91_SSC_CKI_FALLING (0 << 5) |
| 38 | #define AT91_SSC_CK_RISING (1 << 5) | 38 | #define AT91_SSC_CK_RISING (1 << 5) |
| 39 | #define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ | ||
| 40 | #define AT91_SSC_CKG_NONE (0 << 6) | ||
| 41 | #define AT91_SSC_CKG_RFLOW (1 << 6) | ||
| 42 | #define AT91_SSC_CKG_RFHIGH (2 << 6) | ||
| 39 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ | 43 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ |
| 40 | #define AT91_SSC_START_CONTINUOUS (0 << 8) | 44 | #define AT91_SSC_START_CONTINUOUS (0 << 8) |
| 41 | #define AT91_SSC_START_TX_RX (1 << 8) | 45 | #define AT91_SSC_START_TX_RX (1 << 8) |
| @@ -45,6 +49,7 @@ | |||
| 45 | #define AT91_SSC_START_RISING_RF (5 << 8) | 49 | #define AT91_SSC_START_RISING_RF (5 << 8) |
| 46 | #define AT91_SSC_START_LEVEL_RF (6 << 8) | 50 | #define AT91_SSC_START_LEVEL_RF (6 << 8) |
| 47 | #define AT91_SSC_START_EDGE_RF (7 << 8) | 51 | #define AT91_SSC_START_EDGE_RF (7 << 8) |
| 52 | #define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ | ||
| 48 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ | 53 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ |
| 49 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ | 54 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ |
| 50 | 55 | ||
| @@ -75,6 +80,9 @@ | |||
| 75 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ | 80 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ |
| 76 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ | 81 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ |
| 77 | 82 | ||
| 83 | #define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ | ||
| 84 | #define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ | ||
| 85 | |||
| 78 | #define AT91_SSC_SR 0x40 /* Status Register */ | 86 | #define AT91_SSC_SR 0x40 /* Status Register */ |
| 79 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ | 87 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ |
| 80 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ | 88 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ |
| @@ -84,6 +92,8 @@ | |||
| 84 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ | 92 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ |
| 85 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ | 93 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ |
| 86 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ | 94 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ |
| 95 | #define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ | ||
| 96 | #define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ | ||
| 87 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ | 97 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ |
| 88 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ | 98 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ |
| 89 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ | 99 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91_st.h b/include/asm-arm/arch-at91rm9200/at91_st.h new file mode 100644 index 000000000000..2432ddfc6c47 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_st.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_st.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * System Timer (ST) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_ST_H | ||
| 17 | #define AT91_ST_H | ||
| 18 | |||
| 19 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ | ||
| 20 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ | ||
| 23 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ | ||
| 24 | |||
| 25 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ | ||
| 26 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ | ||
| 27 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ | ||
| 28 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ | ||
| 29 | |||
| 30 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ | ||
| 31 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ | ||
| 32 | |||
| 33 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ | ||
| 34 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ | ||
| 35 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ | ||
| 36 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ | ||
| 37 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ | ||
| 38 | |||
| 39 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ | ||
| 40 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ | ||
| 41 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ | ||
| 42 | |||
| 43 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ | ||
| 44 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ | ||
| 45 | |||
| 46 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ | ||
| 47 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91_tc.h index f4da752bb0c8..8d06eb078e1d 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h +++ b/include/asm-arm/arch-at91rm9200/at91_tc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h | 2 | * include/asm-arm/arch-at91rm9200/at91_tc.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) SAN People | 4 | * Copyright (C) SAN People |
| 5 | * | 5 | * |
| @@ -12,8 +12,8 @@ | |||
| 12 | * (at your option) any later version. | 12 | * (at your option) any later version. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #ifndef AT91RM9200_TC_H | 15 | #ifndef AT91_TC_H |
| 16 | #define AT91RM9200_TC_H | 16 | #define AT91_TC_H |
| 17 | 17 | ||
| 18 | #define AT91_TC_BCR 0xc0 /* TC Block Control Register */ | 18 | #define AT91_TC_BCR 0xc0 /* TC Block Control Register */ |
| 19 | #define AT91_TC_SYNC (1 << 0) /* Synchro Command */ | 19 | #define AT91_TC_SYNC (1 << 0) /* Synchro Command */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91_twi.h index 93547d7482bd..cda914f1e740 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h +++ b/include/asm-arm/arch-at91rm9200/at91_twi.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h | 2 | * include/asm-arm/arch-at91rm9200/at91_twi.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_TWI_H | 16 | #ifndef AT91_TWI_H |
| 17 | #define AT91RM9200_TWI_H | 17 | #define AT91_TWI_H |
| 18 | 18 | ||
| 19 | #define AT91_TWI_CR 0x00 /* Control Register */ | 19 | #define AT91_TWI_CR 0x00 /* Control Register */ |
| 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ | 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ |
| @@ -43,8 +43,8 @@ | |||
| 43 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ | 43 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ |
| 44 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ | 44 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ |
| 45 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ | 45 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ |
| 46 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error */ | 46 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ |
| 47 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error */ | 47 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ |
| 48 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ | 48 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ |
| 49 | 49 | ||
| 50 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ | 50 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91_wdt.h b/include/asm-arm/arch-at91rm9200/at91_wdt.h new file mode 100644 index 000000000000..ac63e775772c --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_wdt.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_wdt.h | ||
| 3 | * | ||
| 4 | * Watchdog Timer (WDT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_WDT_H | ||
| 14 | #define AT91_WDT_H | ||
| 15 | |||
| 16 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | ||
| 17 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | ||
| 18 | #define AT91_WDT_KEY (0xff << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | ||
| 21 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | ||
| 22 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | ||
| 23 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | ||
| 24 | #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | ||
| 25 | #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | ||
| 26 | #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | ||
| 27 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | ||
| 28 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | ||
| 29 | |||
| 30 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | ||
| 31 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | ||
| 32 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | ||
| 33 | |||
| 34 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h index a5a86b1ff886..4d51177efddd 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200.h +++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h | |||
| @@ -80,6 +80,22 @@ | |||
| 80 | 80 | ||
| 81 | 81 | ||
| 82 | /* | 82 | /* |
| 83 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 84 | */ | ||
| 85 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ | ||
| 86 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ | ||
| 87 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ | ||
| 88 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ | ||
| 89 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ | ||
| 90 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ | ||
| 91 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ | ||
| 92 | #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ | ||
| 93 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ | ||
| 94 | #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ | ||
| 95 | |||
| 96 | #define AT91_MATRIX 0 /* not supported */ | ||
| 97 | |||
| 98 | /* | ||
| 83 | * Internal Memory. | 99 | * Internal Memory. |
| 84 | */ | 100 | */ |
| 85 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ | 101 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h new file mode 100644 index 000000000000..0c0d81480b3a --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_MC_H | ||
| 17 | #define AT91RM9200_MC_H | ||
| 18 | |||
| 19 | /* Memory Controller */ | ||
| 20 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | ||
| 21 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | ||
| 22 | |||
| 23 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | ||
| 24 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | ||
| 25 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | ||
| 26 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | ||
| 27 | #define AT91_MC_ABTSZ_BYTE (0 << 8) | ||
| 28 | #define AT91_MC_ABTSZ_HALFWORD (1 << 8) | ||
| 29 | #define AT91_MC_ABTSZ_WORD (2 << 8) | ||
| 30 | #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ | ||
| 31 | #define AT91_MC_ABTTYP_DATAREAD (0 << 10) | ||
| 32 | #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) | ||
| 33 | #define AT91_MC_ABTTYP_FETCH (2 << 10) | ||
| 34 | #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ | ||
| 35 | #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ | ||
| 36 | #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ | ||
| 37 | #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ | ||
| 38 | #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ | ||
| 39 | #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ | ||
| 40 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | ||
| 41 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | ||
| 42 | |||
| 43 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | ||
| 44 | |||
| 45 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | ||
| 46 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | ||
| 47 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | ||
| 48 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | ||
| 49 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | ||
| 50 | |||
| 51 | /* External Bus Interface (EBI) registers */ | ||
| 52 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | ||
| 53 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | ||
| 54 | #define AT91_EBI_CS0A_SMC (0 << 0) | ||
| 55 | #define AT91_EBI_CS0A_BFC (1 << 0) | ||
| 56 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 57 | #define AT91_EBI_CS1A_SMC (0 << 1) | ||
| 58 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) | ||
| 59 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ | ||
| 60 | #define AT91_EBI_CS3A_SMC (0 << 3) | ||
| 61 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 62 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ | ||
| 63 | #define AT91_EBI_CS4A_SMC (0 << 4) | ||
| 64 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) | ||
| 65 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ | ||
| 66 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | ||
| 67 | |||
| 68 | /* Static Memory Controller (SMC) registers */ | ||
| 69 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | ||
| 70 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | ||
| 71 | #define AT91_SMC_NWS_(x) ((x) << 0) | ||
| 72 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | ||
| 73 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ | ||
| 74 | #define AT91_SMC_TDF_(x) ((x) << 8) | ||
| 75 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ | ||
| 76 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ | ||
| 77 | #define AT91_SMC_DBW_16 (1 << 13) | ||
| 78 | #define AT91_SMC_DBW_8 (2 << 13) | ||
| 79 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ | ||
| 80 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ | ||
| 81 | #define AT91_SMC_ACSS_STD (0 << 16) | ||
| 82 | #define AT91_SMC_ACSS_1 (1 << 16) | ||
| 83 | #define AT91_SMC_ACSS_2 (2 << 16) | ||
| 84 | #define AT91_SMC_ACSS_3 (3 << 16) | ||
| 85 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ | ||
| 86 | #define AT91_SMC_RWSETUP_(x) ((x) << 24) | ||
| 87 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ | ||
| 88 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | ||
| 89 | |||
| 90 | /* SDRAM Controller registers */ | ||
| 91 | #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ | ||
| 92 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 93 | #define AT91_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 94 | #define AT91_SDRAMC_MODE_NOP (1 << 0) | ||
| 95 | #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 96 | #define AT91_SDRAMC_MODE_LMR (3 << 0) | ||
| 97 | #define AT91_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 98 | #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 99 | #define AT91_SDRAMC_DBW_32 (0 << 4) | ||
| 100 | #define AT91_SDRAMC_DBW_16 (1 << 4) | ||
| 101 | |||
| 102 | #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ | ||
| 103 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 104 | |||
| 105 | #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ | ||
| 106 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 107 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 108 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 109 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 110 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 111 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 112 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 113 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 114 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 115 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 116 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 117 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 118 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 119 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 120 | #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 121 | #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 122 | #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 123 | #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 124 | #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 125 | #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 126 | |||
| 127 | #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ | ||
| 128 | #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ | ||
| 129 | #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ | ||
| 130 | #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ | ||
| 131 | #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ | ||
| 132 | #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ | ||
| 133 | |||
| 134 | /* Burst Flash Controller register */ | ||
| 135 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | ||
| 136 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | ||
| 137 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | ||
| 138 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | ||
| 139 | #define AT91_BFC_BFCOM_BURST (2 << 0) | ||
| 140 | #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ | ||
| 141 | #define AT91_BFC_BFCC_MCK (1 << 2) | ||
| 142 | #define AT91_BFC_BFCC_DIV2 (2 << 2) | ||
| 143 | #define AT91_BFC_BFCC_DIV4 (3 << 2) | ||
| 144 | #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ | ||
| 145 | #define AT91_BFC_PAGES (7 << 8) /* Page Size */ | ||
| 146 | #define AT91_BFC_PAGES_NO_PAGE (0 << 8) | ||
| 147 | #define AT91_BFC_PAGES_16 (1 << 8) | ||
| 148 | #define AT91_BFC_PAGES_32 (2 << 8) | ||
| 149 | #define AT91_BFC_PAGES_64 (3 << 8) | ||
| 150 | #define AT91_BFC_PAGES_128 (4 << 8) | ||
| 151 | #define AT91_BFC_PAGES_256 (5 << 8) | ||
| 152 | #define AT91_BFC_PAGES_512 (6 << 8) | ||
| 153 | #define AT91_BFC_PAGES_1024 (7 << 8) | ||
| 154 | #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ | ||
| 155 | #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ | ||
| 156 | #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ | ||
| 157 | #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ | ||
| 158 | #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ | ||
| 159 | |||
| 160 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h deleted file mode 100644 index 73693fea76a2..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h +++ /dev/null | |||
| @@ -1,438 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_SYS_H | ||
| 17 | #define AT91RM9200_SYS_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Advanced Interrupt Controller. | ||
| 21 | */ | ||
| 22 | #define AT91_AIC 0x000 | ||
| 23 | |||
| 24 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ | ||
| 25 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | ||
| 26 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | ||
| 27 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | ||
| 28 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) | ||
| 29 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) | ||
| 30 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | ||
| 31 | |||
| 32 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | ||
| 33 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ | ||
| 34 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ | ||
| 35 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ | ||
| 36 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | ||
| 37 | |||
| 38 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ | ||
| 39 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ | ||
| 40 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ | ||
| 41 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | ||
| 42 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | ||
| 43 | |||
| 44 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ | ||
| 45 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ | ||
| 46 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ | ||
| 47 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ | ||
| 48 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ | ||
| 49 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ | ||
| 50 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ | ||
| 51 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | ||
| 52 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | ||
| 53 | |||
| 54 | |||
| 55 | /* | ||
| 56 | * Debug Unit. | ||
| 57 | */ | ||
| 58 | #define AT91_DBGU 0x200 | ||
| 59 | |||
| 60 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
| 61 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
| 62 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
| 63 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
| 64 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
| 65 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
| 66 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
| 67 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
| 68 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
| 69 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
| 70 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
| 71 | |||
| 72 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
| 73 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
| 74 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
| 75 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
| 76 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
| 77 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
| 78 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
| 79 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
| 80 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
| 81 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
| 82 | |||
| 83 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ | ||
| 84 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ | ||
| 85 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ | ||
| 86 | |||
| 87 | /* | ||
| 88 | * PIO Controllers. | ||
| 89 | */ | ||
| 90 | #define AT91_PIOA 0x400 | ||
| 91 | #define AT91_PIOB 0x600 | ||
| 92 | #define AT91_PIOC 0x800 | ||
| 93 | #define AT91_PIOD 0xa00 | ||
| 94 | |||
| 95 | #define PIO_PER 0x00 /* Enable Register */ | ||
| 96 | #define PIO_PDR 0x04 /* Disable Register */ | ||
| 97 | #define PIO_PSR 0x08 /* Status Register */ | ||
| 98 | #define PIO_OER 0x10 /* Output Enable Register */ | ||
| 99 | #define PIO_ODR 0x14 /* Output Disable Register */ | ||
| 100 | #define PIO_OSR 0x18 /* Output Status Register */ | ||
| 101 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | ||
| 102 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | ||
| 103 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | ||
| 104 | #define PIO_SODR 0x30 /* Set Output Data Register */ | ||
| 105 | #define PIO_CODR 0x34 /* Clear Output Data Register */ | ||
| 106 | #define PIO_ODSR 0x38 /* Output Data Status Register */ | ||
| 107 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ | ||
| 108 | #define PIO_IER 0x40 /* Interrupt Enable Register */ | ||
| 109 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ | ||
| 110 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ | ||
| 111 | #define PIO_ISR 0x4c /* Interrupt Status Register */ | ||
| 112 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ | ||
| 113 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | ||
| 114 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ | ||
| 115 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ | ||
| 116 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ | ||
| 117 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ | ||
| 118 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ | ||
| 119 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ | ||
| 120 | #define PIO_ABSR 0x78 /* AB Status Register */ | ||
| 121 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ | ||
| 122 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ | ||
| 123 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ | ||
| 124 | |||
| 125 | #define AT91_PIO_P(n) (1 << (n)) | ||
| 126 | |||
| 127 | |||
| 128 | /* | ||
| 129 | * Power Management Controller. | ||
| 130 | */ | ||
| 131 | #define AT91_PMC 0xc00 | ||
| 132 | |||
| 133 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | ||
| 134 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | ||
| 135 | |||
| 136 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | ||
| 137 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
| 138 | #define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */ | ||
| 139 | #define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */ | ||
| 140 | #define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */ | ||
| 141 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
| 142 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
| 143 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
| 144 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
| 145 | |||
| 146 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | ||
| 147 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | ||
| 148 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | ||
| 149 | |||
| 150 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ | ||
| 151 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
| 152 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 153 | |||
| 154 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | ||
| 155 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
| 156 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
| 157 | |||
| 158 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | ||
| 159 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | ||
| 160 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
| 161 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
| 162 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
| 163 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
| 164 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
| 165 | |||
| 166 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | ||
| 167 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
| 168 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
| 169 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
| 170 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
| 171 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
| 172 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | ||
| 173 | #define AT91_PMC_PRES_1 (0 << 2) | ||
| 174 | #define AT91_PMC_PRES_2 (1 << 2) | ||
| 175 | #define AT91_PMC_PRES_4 (2 << 2) | ||
| 176 | #define AT91_PMC_PRES_8 (3 << 2) | ||
| 177 | #define AT91_PMC_PRES_16 (4 << 2) | ||
| 178 | #define AT91_PMC_PRES_32 (5 << 2) | ||
| 179 | #define AT91_PMC_PRES_64 (6 << 2) | ||
| 180 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
| 181 | #define AT91_PMC_MDIV_1 (0 << 8) | ||
| 182 | #define AT91_PMC_MDIV_2 (1 << 8) | ||
| 183 | #define AT91_PMC_MDIV_3 (2 << 8) | ||
| 184 | #define AT91_PMC_MDIV_4 (3 << 8) | ||
| 185 | |||
| 186 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | ||
| 187 | |||
| 188 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | ||
| 189 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | ||
| 190 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | ||
| 191 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
| 192 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
| 193 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
| 194 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
| 195 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
| 196 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
| 197 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
| 198 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
| 199 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | ||
| 200 | |||
| 201 | |||
| 202 | /* | ||
| 203 | * System Timer. | ||
| 204 | */ | ||
| 205 | #define AT91_ST 0xd00 | ||
| 206 | |||
| 207 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ | ||
| 208 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ | ||
| 209 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ | ||
| 210 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ | ||
| 211 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ | ||
| 212 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ | ||
| 213 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ | ||
| 214 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ | ||
| 215 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ | ||
| 216 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ | ||
| 217 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ | ||
| 218 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ | ||
| 219 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ | ||
| 220 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ | ||
| 221 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ | ||
| 222 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ | ||
| 223 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ | ||
| 224 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ | ||
| 225 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ | ||
| 226 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ | ||
| 227 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ | ||
| 228 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ | ||
| 229 | |||
| 230 | |||
| 231 | /* | ||
| 232 | * Real-time Clock. | ||
| 233 | */ | ||
| 234 | #define AT91_RTC 0xe00 | ||
| 235 | |||
| 236 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ | ||
| 237 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ | ||
| 238 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ | ||
| 239 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ | ||
| 240 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) | ||
| 241 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) | ||
| 242 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) | ||
| 243 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) | ||
| 244 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ | ||
| 245 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) | ||
| 246 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) | ||
| 247 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) | ||
| 248 | |||
| 249 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ | ||
| 250 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ | ||
| 251 | |||
| 252 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ | ||
| 253 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ | ||
| 254 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ | ||
| 255 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ | ||
| 256 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ | ||
| 257 | |||
| 258 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ | ||
| 259 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ | ||
| 260 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ | ||
| 261 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ | ||
| 262 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ | ||
| 263 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ | ||
| 264 | |||
| 265 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ | ||
| 266 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ | ||
| 267 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ | ||
| 268 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ | ||
| 269 | |||
| 270 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ | ||
| 271 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ | ||
| 272 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ | ||
| 273 | |||
| 274 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ | ||
| 275 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ | ||
| 276 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ | ||
| 277 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ | ||
| 278 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ | ||
| 279 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ | ||
| 280 | |||
| 281 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ | ||
| 282 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ | ||
| 283 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ | ||
| 284 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ | ||
| 285 | |||
| 286 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ | ||
| 287 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ | ||
| 288 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ | ||
| 289 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ | ||
| 290 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ | ||
| 291 | |||
| 292 | |||
| 293 | /* | ||
| 294 | * Memory Controller. | ||
| 295 | */ | ||
| 296 | #define AT91_MC 0xf00 | ||
| 297 | |||
| 298 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | ||
| 299 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | ||
| 300 | |||
| 301 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | ||
| 302 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | ||
| 303 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | ||
| 304 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | ||
| 305 | #define AT91_MC_ABTSZ_BYTE (0 << 8) | ||
| 306 | #define AT91_MC_ABTSZ_HALFWORD (1 << 8) | ||
| 307 | #define AT91_MC_ABTSZ_WORD (2 << 8) | ||
| 308 | #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ | ||
| 309 | #define AT91_MC_ABTTYP_DATAREAD (0 << 10) | ||
| 310 | #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) | ||
| 311 | #define AT91_MC_ABTTYP_FETCH (2 << 10) | ||
| 312 | #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ | ||
| 313 | #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ | ||
| 314 | #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ | ||
| 315 | #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ | ||
| 316 | #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ | ||
| 317 | #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ | ||
| 318 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | ||
| 319 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | ||
| 320 | |||
| 321 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | ||
| 322 | |||
| 323 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | ||
| 324 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | ||
| 325 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | ||
| 326 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | ||
| 327 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | ||
| 328 | |||
| 329 | /* External Bus Interface (EBI) registers */ | ||
| 330 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | ||
| 331 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | ||
| 332 | #define AT91_EBI_CS0A_SMC (0 << 0) | ||
| 333 | #define AT91_EBI_CS0A_BFC (1 << 0) | ||
| 334 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 335 | #define AT91_EBI_CS1A_SMC (0 << 1) | ||
| 336 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) | ||
| 337 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ | ||
| 338 | #define AT91_EBI_CS3A_SMC (0 << 3) | ||
| 339 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 340 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ | ||
| 341 | #define AT91_EBI_CS4A_SMC (0 << 4) | ||
| 342 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) | ||
| 343 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ | ||
| 344 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | ||
| 345 | |||
| 346 | /* Static Memory Controller (SMC) registers */ | ||
| 347 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | ||
| 348 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | ||
| 349 | #define AT91_SMC_NWS_(x) ((x) << 0) | ||
| 350 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | ||
| 351 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ | ||
| 352 | #define AT91_SMC_TDF_(x) ((x) << 8) | ||
| 353 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ | ||
| 354 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ | ||
| 355 | #define AT91_SMC_DBW_16 (1 << 13) | ||
| 356 | #define AT91_SMC_DBW_8 (2 << 13) | ||
| 357 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ | ||
| 358 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ | ||
| 359 | #define AT91_SMC_ACSS_STD (0 << 16) | ||
| 360 | #define AT91_SMC_ACSS_1 (1 << 16) | ||
| 361 | #define AT91_SMC_ACSS_2 (2 << 16) | ||
| 362 | #define AT91_SMC_ACSS_3 (3 << 16) | ||
| 363 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ | ||
| 364 | #define AT91_SMC_RWSETUP_(x) ((x) << 24) | ||
| 365 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ | ||
| 366 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | ||
| 367 | |||
| 368 | /* SDRAM Controller registers */ | ||
| 369 | #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ | ||
| 370 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 371 | #define AT91_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 372 | #define AT91_SDRAMC_MODE_NOP (1 << 0) | ||
| 373 | #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 374 | #define AT91_SDRAMC_MODE_LMR (3 << 0) | ||
| 375 | #define AT91_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 376 | #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 377 | #define AT91_SDRAMC_DBW_32 (0 << 4) | ||
| 378 | #define AT91_SDRAMC_DBW_16 (1 << 4) | ||
| 379 | |||
| 380 | #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ | ||
| 381 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 382 | |||
| 383 | #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ | ||
| 384 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 385 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 386 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 387 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 388 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 389 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 390 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 391 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 392 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 393 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 394 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 395 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 396 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 397 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 398 | #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 399 | #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 400 | #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 401 | #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 402 | #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 403 | #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 404 | |||
| 405 | #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ | ||
| 406 | #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ | ||
| 407 | #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ | ||
| 408 | #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ | ||
| 409 | #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ | ||
| 410 | #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ | ||
| 411 | |||
| 412 | /* Burst Flash Controller register */ | ||
| 413 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | ||
| 414 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | ||
| 415 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | ||
| 416 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | ||
| 417 | #define AT91_BFC_BFCOM_BURST (2 << 0) | ||
| 418 | #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ | ||
| 419 | #define AT91_BFC_BFCC_MCK (1 << 2) | ||
| 420 | #define AT91_BFC_BFCC_DIV2 (2 << 2) | ||
| 421 | #define AT91_BFC_BFCC_DIV4 (3 << 2) | ||
| 422 | #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ | ||
| 423 | #define AT91_BFC_PAGES (7 << 8) /* Page Size */ | ||
| 424 | #define AT91_BFC_PAGES_NO_PAGE (0 << 8) | ||
| 425 | #define AT91_BFC_PAGES_16 (1 << 8) | ||
| 426 | #define AT91_BFC_PAGES_32 (2 << 8) | ||
| 427 | #define AT91_BFC_PAGES_64 (3 << 8) | ||
| 428 | #define AT91_BFC_PAGES_128 (4 << 8) | ||
| 429 | #define AT91_BFC_PAGES_256 (5 << 8) | ||
| 430 | #define AT91_BFC_PAGES_512 (6 << 8) | ||
| 431 | #define AT91_BFC_PAGES_1024 (7 << 8) | ||
| 432 | #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ | ||
| 433 | #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ | ||
| 434 | #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ | ||
| 435 | #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ | ||
| 436 | #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ | ||
| 437 | |||
| 438 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h deleted file mode 100644 index 951e3f61cef4..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * USB Device Port (UDP) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_UDP_H | ||
| 17 | #define AT91RM9200_UDP_H | ||
| 18 | |||
| 19 | #define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */ | ||
| 20 | #define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */ | ||
| 21 | #define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */ | ||
| 22 | #define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */ | ||
| 23 | |||
| 24 | #define AT91_UDP_GLB_STAT 0x04 /* Global State Register */ | ||
| 25 | #define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */ | ||
| 26 | #define AT91_UDP_CONFG (1 << 1) /* Configured */ | ||
| 27 | #define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */ | ||
| 28 | #define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */ | ||
| 29 | #define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */ | ||
| 30 | |||
| 31 | #define AT91_UDP_FADDR 0x08 /* Function Address Register */ | ||
| 32 | #define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */ | ||
| 33 | #define AT91_UDP_FEN (1 << 8) /* Function Enable */ | ||
| 34 | |||
| 35 | #define AT91_UDP_IER 0x10 /* Interrupt Enable Register */ | ||
| 36 | #define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */ | ||
| 37 | #define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */ | ||
| 38 | |||
| 39 | #define AT91_UDP_ISR 0x1c /* Interrupt Status Register */ | ||
| 40 | #define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */ | ||
| 41 | #define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ | ||
| 42 | #define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */ | ||
| 43 | #define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */ | ||
| 44 | #define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */ | ||
| 45 | #define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */ | ||
| 46 | #define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */ | ||
| 47 | |||
| 48 | #define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */ | ||
| 49 | #define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */ | ||
| 50 | |||
| 51 | #define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */ | ||
| 52 | #define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */ | ||
| 53 | #define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */ | ||
| 54 | #define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */ | ||
| 55 | #define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */ | ||
| 56 | #define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */ | ||
| 57 | #define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */ | ||
| 58 | #define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */ | ||
| 59 | #define AT91_UDP_DIR (1 << 7) /* Transfer Direction */ | ||
| 60 | #define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */ | ||
| 61 | #define AT91_UDP_EPTYPE_CTRL (0 << 8) | ||
| 62 | #define AT91_UDP_EPTYPE_ISO_OUT (1 << 8) | ||
| 63 | #define AT91_UDP_EPTYPE_BULK_OUT (2 << 8) | ||
| 64 | #define AT91_UDP_EPTYPE_INT_OUT (3 << 8) | ||
| 65 | #define AT91_UDP_EPTYPE_ISO_IN (5 << 8) | ||
| 66 | #define AT91_UDP_EPTYPE_BULK_IN (6 << 8) | ||
| 67 | #define AT91_UDP_EPTYPE_INT_IN (7 << 8) | ||
| 68 | #define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */ | ||
| 69 | #define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */ | ||
| 70 | #define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */ | ||
| 71 | |||
| 72 | #define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */ | ||
| 73 | |||
| 74 | #define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */ | ||
| 75 | #define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */ | ||
| 76 | |||
| 77 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260.h b/include/asm-arm/arch-at91rm9200/at91sam9260.h new file mode 100644 index 000000000000..46f4dd65c035 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9260.h | |||
| @@ -0,0 +1,125 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9260.h | ||
| 3 | * | ||
| 4 | * (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9260 datasheet revision A (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9260_H | ||
| 16 | #define AT91SAM9260_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ | ||
| 27 | #define AT91SAM9260_ID_US0 6 /* USART 0 */ | ||
| 28 | #define AT91SAM9260_ID_US1 7 /* USART 1 */ | ||
| 29 | #define AT91SAM9260_ID_US2 8 /* USART 2 */ | ||
| 30 | #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 31 | #define AT91SAM9260_ID_UDP 10 /* USB Device Port */ | ||
| 32 | #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ | ||
| 33 | #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 34 | #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 35 | #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ | ||
| 36 | #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ | ||
| 37 | #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ | ||
| 38 | #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ | ||
| 39 | #define AT91SAM9260_ID_UHP 20 /* USB Host port */ | ||
| 40 | #define AT91SAM9260_ID_EMAC 21 /* Ethernet */ | ||
| 41 | #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ | ||
| 42 | #define AT91SAM9260_ID_US3 23 /* USART 3 */ | ||
| 43 | #define AT91SAM9260_ID_US4 24 /* USART 4 */ | ||
| 44 | #define AT91SAM9260_ID_US5 25 /* USART 5 */ | ||
| 45 | #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ | ||
| 46 | #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ | ||
| 47 | #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ | ||
| 48 | #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 49 | #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 50 | #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 51 | |||
| 52 | |||
| 53 | /* | ||
| 54 | * User Peripheral physical base addresses. | ||
| 55 | */ | ||
| 56 | #define AT91SAM9260_BASE_TCB0 0xfffa0000 | ||
| 57 | #define AT91SAM9260_BASE_TC0 0xfffa0000 | ||
| 58 | #define AT91SAM9260_BASE_TC1 0xfffa0040 | ||
| 59 | #define AT91SAM9260_BASE_TC2 0xfffa0080 | ||
| 60 | #define AT91SAM9260_BASE_UDP 0xfffa4000 | ||
| 61 | #define AT91SAM9260_BASE_MCI 0xfffa8000 | ||
| 62 | #define AT91SAM9260_BASE_TWI 0xfffac000 | ||
| 63 | #define AT91SAM9260_BASE_US0 0xfffb0000 | ||
| 64 | #define AT91SAM9260_BASE_US1 0xfffb4000 | ||
| 65 | #define AT91SAM9260_BASE_US2 0xfffb8000 | ||
| 66 | #define AT91SAM9260_BASE_SSC 0xfffbc000 | ||
| 67 | #define AT91SAM9260_BASE_ISI 0xfffc0000 | ||
| 68 | #define AT91SAM9260_BASE_EMAC 0xfffc4000 | ||
| 69 | #define AT91SAM9260_BASE_SPI0 0xfffc8000 | ||
| 70 | #define AT91SAM9260_BASE_SPI1 0xfffcc000 | ||
| 71 | #define AT91SAM9260_BASE_US3 0xfffd0000 | ||
| 72 | #define AT91SAM9260_BASE_US4 0xfffd4000 | ||
| 73 | #define AT91SAM9260_BASE_US5 0xfffd8000 | ||
| 74 | #define AT91SAM9260_BASE_TCB1 0xfffdc000 | ||
| 75 | #define AT91SAM9260_BASE_TC3 0xfffdc000 | ||
| 76 | #define AT91SAM9260_BASE_TC4 0xfffdc040 | ||
| 77 | #define AT91SAM9260_BASE_TC5 0xfffdc080 | ||
| 78 | #define AT91SAM9260_BASE_ADC 0xfffe0000 | ||
| 79 | #define AT91_BASE_SYS 0xffffe800 | ||
| 80 | |||
| 81 | /* | ||
| 82 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 83 | */ | ||
| 84 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
| 85 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 86 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 88 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
| 89 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 90 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 92 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 95 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 96 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 97 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 98 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 99 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 100 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * Internal Memory. | ||
| 105 | */ | ||
| 106 | #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 107 | #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 108 | |||
| 109 | #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ | ||
| 110 | #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ | ||
| 111 | #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ | ||
| 112 | #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ | ||
| 113 | |||
| 114 | #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 115 | |||
| 116 | #if 0 | ||
| 117 | /* | ||
| 118 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 119 | */ | ||
| 120 | |||
| 121 | // TODO: Add | ||
| 122 | |||
| 123 | #endif | ||
| 124 | |||
| 125 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h new file mode 100644 index 000000000000..746d973705bf --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9260_MATRIX_H | ||
| 14 | #define AT91SAM9260_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 17 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 18 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 19 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 20 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 21 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */ | ||
| 22 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 23 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 24 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 25 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 26 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 27 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 28 | |||
| 29 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 30 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 31 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 32 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 33 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 34 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 35 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 36 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 39 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 40 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 41 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 42 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 45 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 46 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 47 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 48 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 49 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 50 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 51 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 52 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 53 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 54 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 55 | |||
| 56 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 57 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 58 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 59 | |||
| 60 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ | ||
| 61 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 62 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 63 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 64 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 65 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 66 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 70 | #define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ | ||
| 71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 74 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 75 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
| 76 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261.h b/include/asm-arm/arch-at91rm9200/at91sam9261.h new file mode 100644 index 000000000000..8d39672d5b82 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9261.h | |||
| @@ -0,0 +1,292 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9261.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9261 datasheet revision E. (Preliminary) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9261_H | ||
| 16 | #define AT91SAM9261_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9261_ID_US0 6 /* USART 0 */ | ||
| 27 | #define AT91SAM9261_ID_US1 7 /* USART 1 */ | ||
| 28 | #define AT91SAM9261_ID_US2 8 /* USART 2 */ | ||
| 29 | #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 30 | #define AT91SAM9261_ID_UDP 10 /* USB Device Port */ | ||
| 31 | #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ | ||
| 32 | #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 33 | #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 34 | #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 35 | #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 36 | #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 37 | #define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ | ||
| 38 | #define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ | ||
| 39 | #define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ | ||
| 40 | #define AT91SAM9261_ID_UHP 20 /* USB Host port */ | ||
| 41 | #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ | ||
| 42 | #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 43 | #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 44 | #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * User Peripheral physical base addresses. | ||
| 49 | */ | ||
| 50 | #define AT91SAM9261_BASE_TCB0 0xfffa0000 | ||
| 51 | #define AT91SAM9261_BASE_TC0 0xfffa0000 | ||
| 52 | #define AT91SAM9261_BASE_TC1 0xfffa0040 | ||
| 53 | #define AT91SAM9261_BASE_TC2 0xfffa0080 | ||
| 54 | #define AT91SAM9261_BASE_UDP 0xfffa4000 | ||
| 55 | #define AT91SAM9261_BASE_MCI 0xfffa8000 | ||
| 56 | #define AT91SAM9261_BASE_TWI 0xfffac000 | ||
| 57 | #define AT91SAM9261_BASE_US0 0xfffb0000 | ||
| 58 | #define AT91SAM9261_BASE_US1 0xfffb4000 | ||
| 59 | #define AT91SAM9261_BASE_US2 0xfffb8000 | ||
| 60 | #define AT91SAM9261_BASE_SSC0 0xfffbc000 | ||
| 61 | #define AT91SAM9261_BASE_SSC1 0xfffc0000 | ||
| 62 | #define AT91SAM9261_BASE_SSC2 0xfffc4000 | ||
| 63 | #define AT91SAM9261_BASE_SPI0 0xfffc8000 | ||
| 64 | #define AT91SAM9261_BASE_SPI1 0xfffcc000 | ||
| 65 | #define AT91_BASE_SYS 0xffffea00 | ||
| 66 | |||
| 67 | |||
| 68 | /* | ||
| 69 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 70 | */ | ||
| 71 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 72 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 74 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 75 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 76 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 77 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 78 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 79 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 80 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 82 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 83 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 84 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 85 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 86 | |||
| 87 | |||
| 88 | /* | ||
| 89 | * Internal Memory. | ||
| 90 | */ | ||
| 91 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 92 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ | ||
| 93 | |||
| 94 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 95 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 96 | |||
| 97 | #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 98 | #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ | ||
| 99 | |||
| 100 | |||
| 101 | #if 0 | ||
| 102 | /* | ||
| 103 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 104 | */ | ||
| 105 | #define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */ | ||
| 106 | #define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */ | ||
| 107 | #define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */ | ||
| 108 | #define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */ | ||
| 109 | #define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */ | ||
| 110 | #define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */ | ||
| 111 | #define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */ | ||
| 112 | #define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */ | ||
| 113 | #define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */ | ||
| 114 | #define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */ | ||
| 115 | #define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */ | ||
| 116 | #define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */ | ||
| 117 | #define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */ | ||
| 118 | #define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */ | ||
| 119 | #define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */ | ||
| 120 | #define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */ | ||
| 121 | #define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */ | ||
| 122 | #define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */ | ||
| 123 | #define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */ | ||
| 124 | #define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */ | ||
| 125 | #define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */ | ||
| 126 | #define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */ | ||
| 127 | #define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */ | ||
| 128 | #define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */ | ||
| 129 | #define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */ | ||
| 130 | #define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */ | ||
| 131 | #define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */ | ||
| 132 | #define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */ | ||
| 133 | #define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */ | ||
| 134 | #define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */ | ||
| 135 | #define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */ | ||
| 136 | #define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */ | ||
| 137 | #define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */ | ||
| 138 | #define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */ | ||
| 139 | #define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */ | ||
| 140 | #define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */ | ||
| 141 | #define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */ | ||
| 142 | #define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */ | ||
| 143 | #define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */ | ||
| 144 | #define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */ | ||
| 145 | #define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */ | ||
| 146 | #define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */ | ||
| 147 | #define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */ | ||
| 148 | #define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */ | ||
| 149 | #define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */ | ||
| 150 | #define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */ | ||
| 151 | #define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */ | ||
| 152 | #define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */ | ||
| 153 | #define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */ | ||
| 154 | #define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */ | ||
| 155 | #define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */ | ||
| 156 | #define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */ | ||
| 157 | #define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */ | ||
| 158 | #define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */ | ||
| 159 | #define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */ | ||
| 160 | #define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */ | ||
| 161 | #define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */ | ||
| 162 | #define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */ | ||
| 163 | #define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */ | ||
| 164 | #define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */ | ||
| 165 | #define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */ | ||
| 166 | #define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */ | ||
| 167 | #define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */ | ||
| 168 | |||
| 169 | #define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */ | ||
| 170 | #define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */ | ||
| 171 | #define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */ | ||
| 172 | #define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */ | ||
| 173 | #define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */ | ||
| 174 | #define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */ | ||
| 175 | #define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */ | ||
| 176 | #define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */ | ||
| 177 | #define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */ | ||
| 178 | #define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */ | ||
| 179 | #define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */ | ||
| 180 | #define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */ | ||
| 181 | #define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */ | ||
| 182 | #define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */ | ||
| 183 | #define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */ | ||
| 184 | #define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */ | ||
| 185 | #define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */ | ||
| 186 | #define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */ | ||
| 187 | #define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */ | ||
| 188 | #define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */ | ||
| 189 | #define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */ | ||
| 190 | #define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */ | ||
| 191 | #define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */ | ||
| 192 | #define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */ | ||
| 193 | #define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */ | ||
| 194 | #define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */ | ||
| 195 | #define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */ | ||
| 196 | #define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */ | ||
| 197 | #define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */ | ||
| 198 | #define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */ | ||
| 199 | #define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */ | ||
| 200 | #define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */ | ||
| 201 | #define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */ | ||
| 202 | #define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */ | ||
| 203 | #define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */ | ||
| 204 | #define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */ | ||
| 205 | #define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */ | ||
| 206 | #define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */ | ||
| 207 | #define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */ | ||
| 208 | #define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */ | ||
| 209 | #define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */ | ||
| 210 | #define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */ | ||
| 211 | #define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */ | ||
| 212 | #define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */ | ||
| 213 | #define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */ | ||
| 214 | #define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */ | ||
| 215 | #define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */ | ||
| 216 | #define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */ | ||
| 217 | #define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */ | ||
| 218 | #define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */ | ||
| 219 | #define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */ | ||
| 220 | #define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */ | ||
| 221 | #define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */ | ||
| 222 | #define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */ | ||
| 223 | #define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */ | ||
| 224 | #define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */ | ||
| 225 | #define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */ | ||
| 226 | #define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */ | ||
| 227 | #define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */ | ||
| 228 | #define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */ | ||
| 229 | #define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */ | ||
| 230 | |||
| 231 | #define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */ | ||
| 232 | #define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */ | ||
| 233 | #define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */ | ||
| 234 | #define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */ | ||
| 235 | #define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */ | ||
| 236 | #define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */ | ||
| 237 | #define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */ | ||
| 238 | #define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */ | ||
| 239 | #define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */ | ||
| 240 | #define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */ | ||
| 241 | #define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */ | ||
| 242 | #define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */ | ||
| 243 | #define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */ | ||
| 244 | #define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */ | ||
| 245 | #define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */ | ||
| 246 | #define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */ | ||
| 247 | #define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */ | ||
| 248 | #define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */ | ||
| 249 | #define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */ | ||
| 250 | #define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */ | ||
| 251 | #define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */ | ||
| 252 | #define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */ | ||
| 253 | #define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */ | ||
| 254 | #define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */ | ||
| 255 | #define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */ | ||
| 256 | #define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */ | ||
| 257 | #define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */ | ||
| 258 | #define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */ | ||
| 259 | #define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */ | ||
| 260 | #define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */ | ||
| 261 | #define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */ | ||
| 262 | #define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */ | ||
| 263 | #define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */ | ||
| 264 | #define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */ | ||
| 265 | #define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */ | ||
| 266 | #define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */ | ||
| 267 | #define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */ | ||
| 268 | #define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */ | ||
| 269 | #define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */ | ||
| 270 | #define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */ | ||
| 271 | #define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */ | ||
| 272 | #define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */ | ||
| 273 | #define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */ | ||
| 274 | #define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */ | ||
| 275 | #define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */ | ||
| 276 | #define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */ | ||
| 277 | #define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */ | ||
| 278 | #define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */ | ||
| 279 | #define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */ | ||
| 280 | #define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */ | ||
| 281 | #define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */ | ||
| 282 | #define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */ | ||
| 283 | #define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */ | ||
| 284 | #define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */ | ||
| 285 | #define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */ | ||
| 286 | #define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */ | ||
| 287 | #define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */ | ||
| 288 | #define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */ | ||
| 289 | #define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */ | ||
| 290 | #endif | ||
| 291 | |||
| 292 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h new file mode 100644 index 000000000000..270a5dcdf1cd --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9261_MATRIX_H | ||
| 14 | #define AT91SAM9261_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | ||
| 17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 18 | #define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 19 | |||
| 20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | ||
| 21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | ||
| 22 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ | ||
| 23 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ | ||
| 24 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ | ||
| 25 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 26 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 27 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 28 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 29 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 30 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 31 | |||
| 32 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ | ||
| 33 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 34 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 35 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 36 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 37 | #define AT91_MATRIX_ITCM_64 (7 << 0) | ||
| 38 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 39 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 40 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 41 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 42 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ | ||
| 45 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 46 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 47 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 48 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 49 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 50 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 51 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 52 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 53 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 54 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 55 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 56 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 57 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 58 | |||
| 59 | #define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ | ||
| 60 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h new file mode 100644 index 000000000000..7d94968b5d57 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | |||
| @@ -0,0 +1,134 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (SMC, SDRAMC) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM926x_MC_H | ||
| 14 | #define AT91SAM926x_MC_H | ||
| 15 | |||
| 16 | /* SDRAM Controller (SDRAMC) registers */ | ||
| 17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ | ||
| 18 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 19 | #define AT91_SDRAMC_MODE_NORMAL 0 | ||
| 20 | #define AT91_SDRAMC_MODE_NOP 1 | ||
| 21 | #define AT91_SDRAMC_MODE_PRECHARGE 2 | ||
| 22 | #define AT91_SDRAMC_MODE_LMR 3 | ||
| 23 | #define AT91_SDRAMC_MODE_REFRESH 4 | ||
| 24 | #define AT91_SDRAMC_MODE_EXT_LMR 5 | ||
| 25 | #define AT91_SDRAMC_MODE_DEEP 6 | ||
| 26 | |||
| 27 | #define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ | ||
| 28 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
| 29 | |||
| 30 | #define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ | ||
| 31 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 32 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 33 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 34 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 35 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 37 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 38 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 39 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 41 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 42 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 44 | #define AT91_SDRAMC_CAS_1 (1 << 5) | ||
| 45 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 46 | #define AT91_SDRAMC_CAS_3 (3 << 5) | ||
| 47 | #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ | ||
| 48 | #define AT91_SDRAMC_DBW_32 (0 << 7) | ||
| 49 | #define AT91_SDRAMC_DBW_16 (1 << 7) | ||
| 50 | #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ | ||
| 51 | #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ | ||
| 52 | #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ | ||
| 53 | #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ | ||
| 54 | #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ | ||
| 55 | #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ | ||
| 56 | |||
| 57 | #define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ | ||
| 58 | #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| 59 | #define AT91_SDRAMC_LPCB_DISABLE 0 | ||
| 60 | #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 | ||
| 61 | #define AT91_SDRAMC_LPCB_POWER_DOWN 2 | ||
| 62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 | ||
| 63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| 64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| 65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ | ||
| 66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| 67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| 68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| 69 | #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
| 70 | |||
| 71 | #define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ | ||
| 72 | #define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ | ||
| 73 | #define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ | ||
| 74 | #define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ | ||
| 75 | #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ | ||
| 76 | |||
| 77 | #define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ | ||
| 78 | #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ | ||
| 79 | #define AT91_SDRAMC_MD_SDRAM 0 | ||
| 80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 | ||
| 81 | |||
| 82 | |||
| 83 | /* Static Memory Controller (SMC) registers */ | ||
| 84 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 85 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
| 86 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
| 87 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
| 88 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
| 89 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
| 90 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
| 91 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
| 92 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
| 93 | |||
| 94 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 95 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
| 96 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
| 97 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
| 98 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
| 99 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
| 100 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
| 101 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
| 102 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
| 103 | |||
| 104 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 105 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
| 106 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
| 107 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
| 108 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
| 109 | |||
| 110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
| 112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
| 113 | #define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */ | ||
| 114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 5) | ||
| 115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 5) | ||
| 116 | #define AT91_SMC_EXNWMODE_READY (3 << 5) | ||
| 117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
| 118 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
| 119 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
| 120 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
| 121 | #define AT91_SMC_DBW_8 (0 << 12) | ||
| 122 | #define AT91_SMC_DBW_16 (1 << 12) | ||
| 123 | #define AT91_SMC_DBW_32 (2 << 12) | ||
| 124 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
| 125 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
| 126 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
| 127 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
| 128 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
| 129 | #define AT91_SMC_PS_4 (0 << 28) | ||
| 130 | #define AT91_SMC_PS_8 (1 << 28) | ||
| 131 | #define AT91_SMC_PS_16 (2 << 28) | ||
| 132 | #define AT91_SMC_PS_32 (3 << 28) | ||
| 133 | |||
| 134 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h index 3cc9aec80f9d..768e0fc6aa2f 100644 --- a/include/asm-arm/arch-at91rm9200/board.h +++ b/include/asm-arm/arch-at91rm9200/board.h | |||
| @@ -48,13 +48,14 @@ struct at91_cf_data { | |||
| 48 | u8 det_pin; /* Card detect */ | 48 | u8 det_pin; /* Card detect */ |
| 49 | u8 vcc_pin; /* power switching */ | 49 | u8 vcc_pin; /* power switching */ |
| 50 | u8 rst_pin; /* card reset */ | 50 | u8 rst_pin; /* card reset */ |
| 51 | u8 chipselect; /* EBI Chip Select number */ | ||
| 51 | }; | 52 | }; |
| 52 | extern void __init at91_add_device_cf(struct at91_cf_data *data); | 53 | extern void __init at91_add_device_cf(struct at91_cf_data *data); |
| 53 | 54 | ||
| 54 | /* MMC / SD */ | 55 | /* MMC / SD */ |
| 55 | struct at91_mmc_data { | 56 | struct at91_mmc_data { |
| 56 | u8 det_pin; /* card detect IRQ */ | 57 | u8 det_pin; /* card detect IRQ */ |
| 57 | unsigned is_b:1; /* uses B side (vs A) */ | 58 | unsigned slot_b:1; /* uses Slot B */ |
| 58 | unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ | 59 | unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ |
| 59 | u8 wp_pin; /* (SD) writeprotect detect */ | 60 | u8 wp_pin; /* (SD) writeprotect detect */ |
| 60 | u8 vcc_pin; /* power switching (high == on) */ | 61 | u8 vcc_pin; /* power switching (high == on) */ |
| @@ -81,7 +82,8 @@ struct at91_nand_data { | |||
| 81 | u8 rdy_pin; /* ready/busy */ | 82 | u8 rdy_pin; /* ready/busy */ |
| 82 | u8 ale; /* address line number connected to ALE */ | 83 | u8 ale; /* address line number connected to ALE */ |
| 83 | u8 cle; /* address line number connected to CLE */ | 84 | u8 cle; /* address line number connected to CLE */ |
| 84 | struct mtd_partition* (*partition_info)(int, int*); | 85 | u8 bus_width_16; /* buswidth is 16 bit */ |
| 86 | struct mtd_partition* (*partition_info)(int, int*); | ||
| 85 | }; | 87 | }; |
| 86 | extern void __init at91_add_device_nand(struct at91_nand_data *data); | 88 | extern void __init at91_add_device_nand(struct at91_nand_data *data); |
| 87 | 89 | ||
diff --git a/include/asm-arm/arch-at91rm9200/cpu.h b/include/asm-arm/arch-at91rm9200/cpu.h new file mode 100644 index 000000000000..6f8d09b08692 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/cpu.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/cpu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_CPU_H | ||
| 14 | #define __ASM_ARCH_CPU_H | ||
| 15 | |||
| 16 | #include <asm/hardware.h> | ||
| 17 | #include <asm/arch/at91_dbgu.h> | ||
| 18 | |||
| 19 | |||
| 20 | #define ARCH_ID_AT91RM9200 0x09290780 | ||
| 21 | #define ARCH_ID_AT91SAM9260 0x019803a0 | ||
| 22 | #define ARCH_ID_AT91SAM9261 0x019703a0 | ||
| 23 | |||
| 24 | |||
| 25 | static inline unsigned long at91_cpu_identify(void) | ||
| 26 | { | ||
| 27 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); | ||
| 28 | } | ||
| 29 | |||
| 30 | |||
| 31 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
| 32 | #define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) | ||
| 33 | #else | ||
| 34 | #define cpu_is_at91rm9200() (0) | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #ifdef CONFIG_ARCH_AT91SAM9260 | ||
| 38 | #define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260) | ||
| 39 | #else | ||
| 40 | #define cpu_is_at91sam9260() (0) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifdef CONFIG_ARCH_AT91SAM9261 | ||
| 44 | #define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) | ||
| 45 | #else | ||
| 46 | #define cpu_is_at91sam9261() (0) | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S index f496b54c4c3e..85cdadf26634 100644 --- a/include/asm-arm/arch-at91rm9200/debug-macro.S +++ b/include/asm-arm/arch-at91rm9200/debug-macro.S | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
| 15 | #include <asm/arch/at91_dbgu.h> | ||
| 15 | 16 | ||
| 16 | .macro addruart,rx | 17 | .macro addruart,rx |
| 17 | mrc p15, 0, \rx, c1, c0 | 18 | mrc p15, 0, \rx, c1, c0 |
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S index 61a326e94909..57248a796472 100644 --- a/include/asm-arm/arch-at91rm9200/entry-macro.S +++ b/include/asm-arm/arch-at91rm9200/entry-macro.S | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <asm/hardware.h> | 13 | #include <asm/hardware.h> |
| 14 | #include <asm/arch/at91_aic.h> | ||
| 14 | 15 | ||
| 15 | .macro disable_fiq | 16 | .macro disable_fiq |
| 16 | .endm | 17 | .endm |
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h index 9ca4cc9c0b2e..9ea5bfe06320 100644 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ b/include/asm-arm/arch-at91rm9200/hardware.h | |||
| @@ -16,8 +16,16 @@ | |||
| 16 | 16 | ||
| 17 | #include <asm/sizes.h> | 17 | #include <asm/sizes.h> |
| 18 | 18 | ||
| 19 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 19 | #include <asm/arch/at91rm9200.h> | 20 | #include <asm/arch/at91rm9200.h> |
| 20 | #include <asm/arch/at91rm9200_sys.h> | 21 | #elif defined(CONFIG_ARCH_AT91SAM9260) |
| 22 | #include <asm/arch/at91sam9260.h> | ||
| 23 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
| 24 | #include <asm/arch/at91sam9261.h> | ||
| 25 | #else | ||
| 26 | #error "Unsupported AT91 processor" | ||
| 27 | #endif | ||
| 28 | |||
| 21 | 29 | ||
| 22 | /* | 30 | /* |
| 23 | * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF | 31 | * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF |
| @@ -34,29 +42,27 @@ | |||
| 34 | * Virtual to Physical Address mapping for IO devices. | 42 | * Virtual to Physical Address mapping for IO devices. |
| 35 | */ | 43 | */ |
| 36 | #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) | 44 | #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) |
| 37 | #define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI) | ||
| 38 | #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) | 45 | #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) |
| 39 | #define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI) | ||
| 40 | #define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI) | ||
| 41 | #define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP) | ||
| 42 | 46 | ||
| 43 | /* Internal SRAM is mapped below the IO devices */ | 47 | /* Internal SRAM is mapped below the IO devices */ |
| 44 | #define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE) | 48 | #define AT91_SRAM_MAX SZ_1M |
| 49 | #define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) | ||
| 45 | 50 | ||
| 46 | /* Serial ports */ | 51 | /* Serial ports */ |
| 47 | #define ATMEL_MAX_UART 5 /* 4 USART3's and one DBGU port */ | 52 | #define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ |
| 48 | 53 | ||
| 49 | /* FLASH */ | 54 | /* External Memory Map */ |
| 50 | #define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */ | 55 | #define AT91_CHIPSELECT_0 0x10000000 |
| 56 | #define AT91_CHIPSELECT_1 0x20000000 | ||
| 57 | #define AT91_CHIPSELECT_2 0x30000000 | ||
| 58 | #define AT91_CHIPSELECT_3 0x40000000 | ||
| 59 | #define AT91_CHIPSELECT_4 0x50000000 | ||
| 60 | #define AT91_CHIPSELECT_5 0x60000000 | ||
| 61 | #define AT91_CHIPSELECT_6 0x70000000 | ||
| 62 | #define AT91_CHIPSELECT_7 0x80000000 | ||
| 51 | 63 | ||
| 52 | /* SDRAM */ | 64 | /* SDRAM */ |
| 53 | #define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */ | 65 | #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 |
| 54 | |||
| 55 | /* SmartMedia */ | ||
| 56 | #define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */ | ||
| 57 | |||
| 58 | /* Compact Flash */ | ||
| 59 | #define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */ | ||
| 60 | 66 | ||
| 61 | /* Clocks */ | 67 | /* Clocks */ |
| 62 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | 68 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ |
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h index 763cb96c418b..c0679eaefaf2 100644 --- a/include/asm-arm/arch-at91rm9200/irqs.h +++ b/include/asm-arm/arch-at91rm9200/irqs.h | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #ifndef __ASM_ARCH_IRQS_H | 21 | #ifndef __ASM_ARCH_IRQS_H |
| 22 | #define __ASM_ARCH_IRQS_H | 22 | #define __ASM_ARCH_IRQS_H |
| 23 | 23 | ||
| 24 | #include <asm/arch/at91_aic.h> | ||
| 25 | |||
| 24 | #define NR_AIC_IRQS 32 | 26 | #define NR_AIC_IRQS 32 |
| 25 | 27 | ||
| 26 | 28 | ||
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h index 8a2ff472e4cf..9c67130603b2 100644 --- a/include/asm-arm/arch-at91rm9200/system.h +++ b/include/asm-arm/arch-at91rm9200/system.h | |||
| @@ -22,6 +22,8 @@ | |||
| 22 | #define __ASM_ARCH_SYSTEM_H | 22 | #define __ASM_ARCH_SYSTEM_H |
| 23 | 23 | ||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | #include <asm/arch/at91_st.h> | ||
| 26 | #include <asm/arch/at91_dbgu.h> | ||
| 25 | 27 | ||
| 26 | static inline void arch_idle(void) | 28 | static inline void arch_idle(void) |
| 27 | { | 29 | { |
| @@ -39,21 +41,13 @@ static inline void arch_idle(void) | |||
| 39 | cpu_do_idle(); | 41 | cpu_do_idle(); |
| 40 | } | 42 | } |
| 41 | 43 | ||
| 42 | static inline void arch_reset(char mode) | 44 | void (*at91_arch_reset)(void); |
| 43 | { | ||
| 44 | /* | ||
| 45 | * Perform a hardware reset with the use of the Watchdog timer. | ||
| 46 | */ | ||
| 47 | at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); | ||
| 48 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); | ||
| 49 | } | ||
| 50 | |||
| 51 | #define ARCH_ID_AT91RM9200 0x09200080 | ||
| 52 | #define ARCH_ID_AT91SAM9261 0x019000a0 | ||
| 53 | 45 | ||
| 54 | static inline unsigned long arch_identify(void) | 46 | static inline void arch_reset(char mode) |
| 55 | { | 47 | { |
| 56 | return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH); | 48 | /* call the CPU-specific reset function */ |
| 49 | if (at91_arch_reset) | ||
| 50 | (at91_arch_reset)(); | ||
| 57 | } | 51 | } |
| 58 | 52 | ||
| 59 | #endif | 53 | #endif |
diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h index 88687cefe6eb..faeca45a8d44 100644 --- a/include/asm-arm/arch-at91rm9200/timex.h +++ b/include/asm-arm/arch-at91rm9200/timex.h | |||
| @@ -23,6 +23,15 @@ | |||
| 23 | 23 | ||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | 25 | ||
| 26 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 27 | |||
| 26 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) | 28 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) |
| 27 | 29 | ||
| 30 | #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) | ||
| 31 | |||
| 32 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
| 33 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 34 | |||
| 35 | #endif | ||
| 36 | |||
| 28 | #endif | 37 | #endif |
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h index ec7811ab0a52..34b4b93fa015 100644 --- a/include/asm-arm/arch-at91rm9200/uncompress.h +++ b/include/asm-arm/arch-at91rm9200/uncompress.h | |||
| @@ -22,11 +22,11 @@ | |||
| 22 | #define __ASM_ARCH_UNCOMPRESS_H | 22 | #define __ASM_ARCH_UNCOMPRESS_H |
| 23 | 23 | ||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | #include <asm/arch/at91_dbgu.h> | ||
| 25 | 26 | ||
| 26 | /* | 27 | /* |
| 27 | * The following code assumes the serial port has already been | 28 | * The following code assumes the serial port has already been |
| 28 | * initialized by the bootloader. We search for the first enabled | 29 | * initialized by the bootloader. If you didn't setup a port in |
| 29 | * port in the most probable order. If you didn't setup a port in | ||
| 30 | * your bootloader then nothing will appear (which might be desired). | 30 | * your bootloader then nothing will appear (which might be desired). |
| 31 | * | 31 | * |
| 32 | * This does not append a newline | 32 | * This does not append a newline |
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h index 4c367eb57f47..0a23b8c562b9 100644 --- a/include/asm-arm/arch-at91rm9200/vmalloc.h +++ b/include/asm-arm/arch-at91rm9200/vmalloc.h | |||
| @@ -21,6 +21,6 @@ | |||
| 21 | #ifndef __ASM_ARCH_VMALLOC_H | 21 | #ifndef __ASM_ARCH_VMALLOC_H |
| 22 | #define __ASM_ARCH_VMALLOC_H | 22 | #define __ASM_ARCH_VMALLOC_H |
| 23 | 23 | ||
| 24 | #define VMALLOC_END (AT91_SRAM_VIRT_BASE & PGDIR_MASK) | 24 | #define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK) |
| 25 | 25 | ||
| 26 | #endif | 26 | #endif |
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h index c6e8dcf674de..42768cc8bfb4 100644 --- a/include/asm-arm/arch-clps711x/memory.h +++ b/include/asm-arm/arch-clps711x/memory.h | |||
| @@ -62,7 +62,15 @@ | |||
| 62 | * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. | 62 | * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. |
| 63 | */ | 63 | */ |
| 64 | 64 | ||
| 65 | #ifdef CONFIG_DISCONTIGMEM | 65 | /* |
| 66 | * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 | ||
| 67 | * uses only one of the two banks (bank #1). However, even within | ||
| 68 | * bank #1, memory is discontiguous. | ||
| 69 | * | ||
| 70 | * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between | ||
| 71 | * them, so we use 24 for the node max shift to get 16MB node sizes. | ||
| 72 | */ | ||
| 73 | |||
| 66 | /* | 74 | /* |
| 67 | * Because of the wide memory address space between physical RAM banks on the | 75 | * Because of the wide memory address space between physical RAM banks on the |
| 68 | * SA1100, it's much more convenient to use Linux's NUMA support to implement | 76 | * SA1100, it's much more convenient to use Linux's NUMA support to implement |
| @@ -80,48 +88,7 @@ | |||
| 80 | * node 2: 0xd0000000 - 0xd7ffffff | 88 | * node 2: 0xd0000000 - 0xd7ffffff |
| 81 | * node 3: 0xd8000000 - 0xdfffffff | 89 | * node 3: 0xd8000000 - 0xdfffffff |
| 82 | */ | 90 | */ |
| 83 | 91 | #define NODE_MEM_SIZE_BITS 24 | |
| 84 | /* | ||
| 85 | * Given a kernel address, find the home node of the underlying memory. | ||
| 86 | */ | ||
| 87 | #define KVADDR_TO_NID(addr) \ | ||
| 88 | (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT) | ||
| 89 | |||
| 90 | /* | ||
| 91 | * Given a page frame number, convert it to a node id. | ||
| 92 | */ | ||
| 93 | #define PFN_TO_NID(pfn) \ | ||
| 94 | (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT)) | ||
| 95 | |||
| 96 | /* | ||
| 97 | * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory | ||
| 98 | * and returns the mem_map of that node. | ||
| 99 | */ | ||
| 100 | #define ADDR_TO_MAPBASE(kaddr) \ | ||
| 101 | NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) | ||
| 102 | |||
| 103 | #define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) | ||
| 104 | |||
| 105 | /* | ||
| 106 | * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory | ||
| 107 | * and returns the index corresponding to the appropriate page in the | ||
| 108 | * node's mem_map. | ||
| 109 | */ | ||
| 110 | #define LOCAL_MAP_NR(addr) \ | ||
| 111 | (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT) | ||
| 112 | |||
| 113 | /* | ||
| 114 | * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 | ||
| 115 | * uses only one of the two banks (bank #1). However, even within | ||
| 116 | * bank #1, memory is discontiguous. | ||
| 117 | * | ||
| 118 | * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between | ||
| 119 | * them, so we use 24 for the node max shift to get 16MB node sizes. | ||
| 120 | */ | ||
| 121 | #define NODE_MAX_MEM_SHIFT 24 | ||
| 122 | #define NODE_MAX_MEM_SIZE (1<<NODE_MAX_MEM_SHIFT) | ||
| 123 | |||
| 124 | #endif /* CONFIG_DISCONTIGMEM */ | ||
| 125 | 92 | ||
| 126 | #endif | 93 | #endif |
| 127 | 94 | ||
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S new file mode 100644 index 000000000000..788b4e386c16 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/debug-macro.S | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop13xx/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header | ||
| 5 | * | ||
| 6 | * Copyright (C) 1994-1999 Russell King | ||
| 7 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart, rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ mmu enabled? | ||
| 17 | moveq \rx, #0xff000000 @ physical | ||
| 18 | orreq \rx, \rx, #0x00d80000 | ||
| 19 | movne \rx, #0xfe000000 @ virtual | ||
| 20 | orrne \rx, \rx, #0x00e80000 | ||
| 21 | orr \rx, \rx, #0x00002300 | ||
| 22 | orr \rx, \rx, #0x00000040 | ||
| 23 | .endm | ||
| 24 | |||
| 25 | #define UART_SHIFT 2 | ||
| 26 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h new file mode 100644 index 000000000000..2e15da53ff79 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/dma.h | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | #ifndef _IOP13XX_DMA_H | ||
| 2 | #define _IOP13XX_DMA_H_ | ||
| 3 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S new file mode 100644 index 000000000000..94c50283dc56 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/entry-macro.S | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * iop13xx low level irq macros | ||
| 3 | * Copyright (c) 2005-2006, Intel Corporation. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms and conditions of the GNU General Public License, | ||
| 7 | * version 2, as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along with | ||
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | ||
| 16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | .macro disable_fiq | ||
| 20 | .endm | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Note: a 1-cycle window exists where iintvec will return the value | ||
| 24 | * of iintbase, so we explicitly check for "bad zeros" | ||
| 25 | */ | ||
| 26 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 27 | mrc p15, 0, \tmp, c15, c1, 0 | ||
| 28 | orr \tmp, \tmp, #(1 << 6) | ||
| 29 | mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access | ||
| 30 | |||
| 31 | mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC | ||
| 32 | cmp \irqnr, #0 | ||
| 33 | mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero | ||
| 34 | adds \irqstat, \irqnr, #1 @ Check for 0xffffffff | ||
| 35 | movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr | ||
| 36 | |||
| 37 | biceq \tmp, \tmp, #(1 << 6) | ||
| 38 | mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts | ||
| 39 | .endm | ||
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h new file mode 100644 index 000000000000..8e1d56289846 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/hardware.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 2 | #define __ASM_ARCH_HARDWARE_H | ||
| 3 | #include <asm/types.h> | ||
| 4 | |||
| 5 | #define pcibios_assign_all_busses() 1 | ||
| 6 | |||
| 7 | #ifndef __ASSEMBLY__ | ||
| 8 | extern unsigned long iop13xx_pcibios_min_io; | ||
| 9 | extern unsigned long iop13xx_pcibios_min_mem; | ||
| 10 | extern u16 iop13xx_dev_id(void); | ||
| 11 | extern void iop13xx_set_atu_mmr_bases(void); | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io) | ||
| 15 | #define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem) | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Generic chipset bits | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | #include "iop13xx.h" | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Board specific bits | ||
| 25 | */ | ||
| 26 | #include "iq81340.h" | ||
| 27 | |||
| 28 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h new file mode 100644 index 000000000000..db6de2480a24 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/io.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * iop13xx custom ioremap implementation | ||
| 3 | * Copyright (c) 2005-2006, Intel Corporation. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms and conditions of the GNU General Public License, | ||
| 7 | * version 2, as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along with | ||
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | ||
| 16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 20 | #define __ASM_ARM_ARCH_IO_H | ||
| 21 | |||
| 22 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 23 | |||
| 24 | #define __io(a) (a) | ||
| 25 | #define __mem_pci(a) (a) | ||
| 26 | #define __mem_isa(a) (a) | ||
| 27 | |||
| 28 | extern void __iomem * __ioremap(unsigned long, size_t, unsigned long); | ||
| 29 | extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, | ||
| 30 | unsigned long flags); | ||
| 31 | extern void __iop13xx_iounmap(void __iomem *addr); | ||
| 32 | |||
| 33 | extern u32 iop13xx_atue_mem_base; | ||
| 34 | extern u32 iop13xx_atux_mem_base; | ||
| 35 | extern size_t iop13xx_atue_mem_size; | ||
| 36 | extern size_t iop13xx_atux_mem_size; | ||
| 37 | |||
| 38 | #define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f) | ||
| 39 | #define __arch_iounmap(a) __iop13xx_iounmap(a) | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h new file mode 100644 index 000000000000..a88522a0ff8e --- /dev/null +++ b/include/asm-arm/arch-iop13xx/iop13xx.h | |||
| @@ -0,0 +1,492 @@ | |||
| 1 | #ifndef _IOP13XX_HW_H_ | ||
| 2 | #define _IOP13XX_HW_H_ | ||
| 3 | |||
| 4 | #ifndef __ASSEMBLY__ | ||
| 5 | /* The ATU offsets can change based on the strapping */ | ||
| 6 | extern u32 iop13xx_atux_pmmr_offset; | ||
| 7 | extern u32 iop13xx_atue_pmmr_offset; | ||
| 8 | void iop13xx_init_irq(void); | ||
| 9 | void iop13xx_map_io(void); | ||
| 10 | void iop13xx_platform_init(void); | ||
| 11 | void iop13xx_init_irq(void); | ||
| 12 | void iop13xx_init_time(unsigned long tickrate); | ||
| 13 | unsigned long iop13xx_gettimeoffset(void); | ||
| 14 | |||
| 15 | /* handle cp6 access | ||
| 16 | * to do: handle access in entry-armv5.S and unify with | ||
| 17 | * the iop3xx implementation | ||
| 18 | * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h) | ||
| 19 | * when interrupts are enabled | ||
| 20 | */ | ||
| 21 | static inline unsigned long iop13xx_cp6_save(void) | ||
| 22 | { | ||
| 23 | u32 temp, cp_flags; | ||
| 24 | |||
| 25 | asm volatile ( | ||
| 26 | "mrc p15, 0, %1, c15, c1, 0\n\t" | ||
| 27 | "orr %0, %1, #(1 << 6)\n\t" | ||
| 28 | "mcr p15, 0, %0, c15, c1, 0\n\t" | ||
| 29 | : "=r" (temp), "=r"(cp_flags)); | ||
| 30 | |||
| 31 | return cp_flags; | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void iop13xx_cp6_restore(unsigned long cp_flags) | ||
| 35 | { | ||
| 36 | asm volatile ( | ||
| 37 | "mcr p15, 0, %0, c15, c1, 0\n\t" | ||
| 38 | : : "r" (cp_flags) ); | ||
| 39 | } | ||
| 40 | |||
| 41 | /* CPUID CP6 R0 Page 0 */ | ||
| 42 | static inline int iop13xx_cpu_id(void) | ||
| 43 | { | ||
| 44 | int id; | ||
| 45 | asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); | ||
| 46 | return id; | ||
| 47 | } | ||
| 48 | |||
| 49 | #endif | ||
| 50 | |||
| 51 | /* | ||
| 52 | * IOP13XX I/O and Mem space regions for PCI autoconfiguration | ||
| 53 | */ | ||
| 54 | #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */ | ||
| 55 | #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE | ||
| 56 | |||
| 57 | /* PCI MAP | ||
| 58 | * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM | ||
| 59 | * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB) | ||
| 60 | */ | ||
| 61 | #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL | ||
| 62 | #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL | ||
| 63 | #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL | ||
| 64 | #define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL | ||
| 65 | #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ | ||
| 66 | IOP13XX_PCIX_IO_WINDOW_SIZE - 1) | ||
| 67 | #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ | ||
| 68 | IOP13XX_PCIX_IO_WINDOW_SIZE - 1) | ||
| 69 | #define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\ | ||
| 70 | IOP13XX_PCIX_LOWER_IO_BA) | ||
| 71 | #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | ||
| 72 | (IOP13XX_PCIX_LOWER_IO_PA\ | ||
| 73 | - IOP13XX_PCIX_LOWER_IO_VA)) | ||
| 74 | |||
| 75 | #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL | ||
| 76 | #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL | ||
| 77 | #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) | ||
| 78 | #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\ | ||
| 79 | IOP13XX_PCIX_LOWER_MEM_BA) | ||
| 80 | #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\ | ||
| 81 | IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) | ||
| 82 | #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\ | ||
| 83 | IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) | ||
| 84 | |||
| 85 | #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL | ||
| 86 | #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE | ||
| 87 | #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\ | ||
| 88 | IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) | ||
| 89 | #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\ | ||
| 90 | IOP13XX_PCIX_LOWER_MEM_BA) | ||
| 91 | |||
| 92 | /* PCI-E ranges */ | ||
| 93 | #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL | ||
| 94 | #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL | ||
| 95 | #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL | ||
| 96 | #define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL | ||
| 97 | #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ | ||
| 98 | IOP13XX_PCIE_IO_WINDOW_SIZE - 1) | ||
| 99 | #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ | ||
| 100 | IOP13XX_PCIE_IO_WINDOW_SIZE - 1) | ||
| 101 | #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ | ||
| 102 | IOP13XX_PCIE_IO_WINDOW_SIZE - 1) | ||
| 103 | #define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\ | ||
| 104 | IOP13XX_PCIE_LOWER_IO_BA) | ||
| 105 | #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | ||
| 106 | (IOP13XX_PCIE_LOWER_IO_PA\ | ||
| 107 | - IOP13XX_PCIE_LOWER_IO_VA)) | ||
| 108 | |||
| 109 | #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL | ||
| 110 | #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL | ||
| 111 | #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) | ||
| 112 | #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\ | ||
| 113 | IOP13XX_PCIE_LOWER_MEM_BA) | ||
| 114 | #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\ | ||
| 115 | IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) | ||
| 116 | #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\ | ||
| 117 | IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) | ||
| 118 | |||
| 119 | /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */ | ||
| 120 | #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL | ||
| 121 | #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE | ||
| 122 | #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\ | ||
| 123 | IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) | ||
| 124 | #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\ | ||
| 125 | IOP13XX_PCIE_LOWER_MEM_BA) | ||
| 126 | |||
| 127 | /* PBI Ranges */ | ||
| 128 | #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL | ||
| 129 | #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL | ||
| 130 | #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL | ||
| 131 | #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE | ||
| 132 | #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\ | ||
| 133 | IOP13XX_PBI_MEM_WINDOW_SIZE - 1) | ||
| 134 | |||
| 135 | /* | ||
| 136 | * IOP13XX chipset registers | ||
| 137 | */ | ||
| 138 | #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ | ||
| 139 | #define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ | ||
| 140 | #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 | ||
| 141 | #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ | ||
| 142 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) | ||
| 143 | #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ | ||
| 144 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) | ||
| 145 | #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ | ||
| 146 | (IOP13XX_PMMR_PHYS_MEM_BASE\ | ||
| 147 | - IOP13XX_PMMR_VIRT_MEM_BASE)) | ||
| 148 | #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | ||
| 149 | (IOP13XX_PMMR_PHYS_MEM_BASE\ | ||
| 150 | - IOP13XX_PMMR_VIRT_MEM_BASE)) | ||
| 151 | #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | ||
| 152 | #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | ||
| 153 | #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | ||
| 154 | #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) | ||
| 155 | #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) | ||
| 156 | #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) | ||
| 157 | #define IOP13XX_PMMR_SIZE 0x00080000 | ||
| 158 | |||
| 159 | /*=================== Defines for Platform Devices =====================*/ | ||
| 160 | #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) | ||
| 161 | #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) | ||
| 162 | #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) | ||
| 163 | #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) | ||
| 164 | |||
| 165 | #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) | ||
| 166 | #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) | ||
| 167 | #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) | ||
| 168 | #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) | ||
| 169 | #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) | ||
| 170 | #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) | ||
| 171 | |||
| 172 | /* ATU selection flags */ | ||
| 173 | /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */ | ||
| 174 | #define IOP13XX_INIT_ATU_DEFAULT (0) | ||
| 175 | #define IOP13XX_INIT_ATU_ATUX (1 << 0) | ||
| 176 | #define IOP13XX_INIT_ATU_ATUE (1 << 1) | ||
| 177 | #define IOP13XX_INIT_ATU_NONE (1 << 2) | ||
| 178 | |||
| 179 | /* UART selection flags */ | ||
| 180 | /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */ | ||
| 181 | #define IOP13XX_INIT_UART_DEFAULT (0) | ||
| 182 | #define IOP13XX_INIT_UART_0 (1 << 0) | ||
| 183 | #define IOP13XX_INIT_UART_1 (1 << 1) | ||
| 184 | |||
| 185 | /* I2C selection flags */ | ||
| 186 | /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */ | ||
| 187 | #define IOP13XX_INIT_I2C_DEFAULT (0) | ||
| 188 | #define IOP13XX_INIT_I2C_0 (1 << 0) | ||
| 189 | #define IOP13XX_INIT_I2C_1 (1 << 1) | ||
| 190 | #define IOP13XX_INIT_I2C_2 (1 << 2) | ||
| 191 | |||
| 192 | #define IQ81340_NUM_UART 2 | ||
| 193 | #define IQ81340_NUM_I2C 3 | ||
| 194 | #define IQ81340_NUM_PHYS_MAP_FLASH 1 | ||
| 195 | #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\ | ||
| 196 | IQ81340_NUM_I2C +\ | ||
| 197 | IQ81340_NUM_PHYS_MAP_FLASH) | ||
| 198 | |||
| 199 | /*========================== PMMR offsets for key registers ============*/ | ||
| 200 | #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 | ||
| 201 | #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000 | ||
| 202 | #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000 | ||
| 203 | #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000 | ||
| 204 | #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 | ||
| 205 | #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 | ||
| 206 | #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 | ||
| 207 | #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 | ||
| 208 | #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) | ||
| 209 | |||
| 210 | #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */ | ||
| 211 | #define IOP13XX_CONTROLLER_ONLY (1 << 14) | ||
| 212 | #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15) | ||
| 213 | |||
| 214 | #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000 | ||
| 215 | #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\ | ||
| 216 | IOP13XX_PMON_PMMR_OFFSET) | ||
| 217 | #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\ | ||
| 218 | IOP13XX_PMON_PMMR_OFFSET) | ||
| 219 | |||
| 220 | #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0) | ||
| 221 | #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4) | ||
| 222 | #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8) | ||
| 223 | #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC) | ||
| 224 | |||
| 225 | #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30) | ||
| 226 | #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34) | ||
| 227 | #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38) | ||
| 228 | #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C) | ||
| 229 | |||
| 230 | #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70) | ||
| 231 | #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74) | ||
| 232 | #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78) | ||
| 233 | #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C) | ||
| 234 | |||
| 235 | #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040) | ||
| 236 | #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044) | ||
| 237 | |||
| 238 | /*================================ATU===================================*/ | ||
| 239 | #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\ | ||
| 240 | iop13xx_atux_pmmr_offset + (ofs)) | ||
| 241 | |||
| 242 | #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\ | ||
| 243 | iop13xx_atux_pmmr_offset + 0x2) | ||
| 244 | |||
| 245 | #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\ | ||
| 246 | iop13xx_atux_pmmr_offset + 0x4) | ||
| 247 | #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\ | ||
| 248 | iop13xx_atux_pmmr_offset + 0x6) | ||
| 249 | |||
| 250 | #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10) | ||
| 251 | #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14) | ||
| 252 | #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18) | ||
| 253 | #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c) | ||
| 254 | #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20) | ||
| 255 | #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24) | ||
| 256 | #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40) | ||
| 257 | #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44) | ||
| 258 | #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48) | ||
| 259 | #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c) | ||
| 260 | #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50) | ||
| 261 | #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54) | ||
| 262 | #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58) | ||
| 263 | #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c) | ||
| 264 | #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60) | ||
| 265 | #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70) | ||
| 266 | #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74) | ||
| 267 | #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78) | ||
| 268 | #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4) | ||
| 269 | #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200) | ||
| 270 | #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204) | ||
| 271 | #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208) | ||
| 272 | #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c) | ||
| 273 | #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210) | ||
| 274 | |||
| 275 | #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300) | ||
| 276 | #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304) | ||
| 277 | #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308) | ||
| 278 | #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c) | ||
| 279 | #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310) | ||
| 280 | #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314) | ||
| 281 | #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318) | ||
| 282 | #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c) | ||
| 283 | #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320) | ||
| 284 | #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324) | ||
| 285 | #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328) | ||
| 286 | #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c) | ||
| 287 | #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330) | ||
| 288 | #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334) | ||
| 289 | |||
| 290 | #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1) | ||
| 291 | #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25) | ||
| 292 | #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21) | ||
| 293 | #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15) | ||
| 294 | #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14) | ||
| 295 | #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16) | ||
| 296 | |||
| 297 | #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18) | ||
| 298 | #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17) | ||
| 299 | #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16) | ||
| 300 | #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15) | ||
| 301 | #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14) | ||
| 302 | #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13) | ||
| 303 | #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12) | ||
| 304 | #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11) | ||
| 305 | #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10) | ||
| 306 | #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 ) | ||
| 307 | #define IOP13XX_ATUX_STAT_BIST (1 << 8 ) | ||
| 308 | #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 ) | ||
| 309 | #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 ) | ||
| 310 | #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 ) | ||
| 311 | #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 ) | ||
| 312 | #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 ) | ||
| 313 | #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 ) | ||
| 314 | |||
| 315 | #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8) | ||
| 316 | #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3) | ||
| 317 | #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0) | ||
| 318 | |||
| 319 | #define IOP13XX_ATUX_IALR_DISABLE 0x00000001 | ||
| 320 | #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000 | ||
| 321 | |||
| 322 | #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\ | ||
| 323 | iop13xx_atue_pmmr_offset + (ofs)) | ||
| 324 | |||
| 325 | #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\ | ||
| 326 | iop13xx_atue_pmmr_offset + 0x2) | ||
| 327 | #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\ | ||
| 328 | iop13xx_atue_pmmr_offset + 0x4) | ||
| 329 | #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\ | ||
| 330 | iop13xx_atue_pmmr_offset + 0x6) | ||
| 331 | |||
| 332 | #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10) | ||
| 333 | #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14) | ||
| 334 | #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18) | ||
| 335 | #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c) | ||
| 336 | #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20) | ||
| 337 | #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24) | ||
| 338 | #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40) | ||
| 339 | #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44) | ||
| 340 | #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48) | ||
| 341 | #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c) | ||
| 342 | #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50) | ||
| 343 | #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54) | ||
| 344 | #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58) | ||
| 345 | #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c) | ||
| 346 | #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60) | ||
| 347 | #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\ | ||
| 348 | iop13xx_atue_pmmr_offset + 0xe2) | ||
| 349 | #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304) | ||
| 350 | #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308) | ||
| 351 | #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c) | ||
| 352 | #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310) | ||
| 353 | #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314) | ||
| 354 | #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318) | ||
| 355 | #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c) | ||
| 356 | #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320) | ||
| 357 | #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324) | ||
| 358 | |||
| 359 | #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70) | ||
| 360 | #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74) | ||
| 361 | #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78) | ||
| 362 | #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300) | ||
| 363 | #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c) | ||
| 364 | #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330) | ||
| 365 | |||
| 366 | #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384) | ||
| 367 | #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388) | ||
| 368 | |||
| 369 | #define IOP13XX_ATUE_ATUCR_IVM (1 << 6) | ||
| 370 | #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1) | ||
| 371 | #define IOP13XX_ATUE_OCCAR_BUS_NUM (24) | ||
| 372 | #define IOP13XX_ATUE_OCCAR_DEV_NUM (19) | ||
| 373 | #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16) | ||
| 374 | #define IOP13XX_ATUE_OCCAR_EXT_REG (8) | ||
| 375 | #define IOP13XX_ATUE_OCCAR_REG (2) | ||
| 376 | |||
| 377 | #define IOP13XX_ATUE_PCSR_BUS_NUM (24) | ||
| 378 | #define IOP13XX_ATUE_PCSR_DEV_NUM (19) | ||
| 379 | #define IOP13XX_ATUE_PCSR_FUNC_NUM (16) | ||
| 380 | #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15) | ||
| 381 | #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14) | ||
| 382 | #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13) | ||
| 383 | #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12) | ||
| 384 | |||
| 385 | #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff) | ||
| 386 | #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f) | ||
| 387 | #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7) | ||
| 388 | |||
| 389 | #define IOP13XX_ATUE_PCSR_CORE_RESET (8) | ||
| 390 | #define IOP13XX_ATUE_PCSR_FUNC_NUM (16) | ||
| 391 | |||
| 392 | #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11) | ||
| 393 | #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28) | ||
| 394 | #define IOP13XX_ATUE_STAT_PME (1 << 27) | ||
| 395 | #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26) | ||
| 396 | #define IOP13XX_ATUE_STAT_IVM (1 << 25) | ||
| 397 | #define IOP13XX_ATUE_STAT_BIST (1 << 24) | ||
| 398 | #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18) | ||
| 399 | #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17) | ||
| 400 | #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16) | ||
| 401 | #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13) | ||
| 402 | #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12) | ||
| 403 | #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11) | ||
| 404 | #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10) | ||
| 405 | #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 ) | ||
| 406 | #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 ) | ||
| 407 | #define IOP13XX_ATUE_STAT_CRS (1 << 7 ) | ||
| 408 | #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 ) | ||
| 409 | #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 ) | ||
| 410 | #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 ) | ||
| 411 | #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 ) | ||
| 412 | #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 ) | ||
| 413 | #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 ) | ||
| 414 | #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 ) | ||
| 415 | |||
| 416 | #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31) | ||
| 417 | #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30) | ||
| 418 | #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29) | ||
| 419 | #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28) | ||
| 420 | #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20) | ||
| 421 | #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19) | ||
| 422 | #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18) | ||
| 423 | #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17) | ||
| 424 | #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16) | ||
| 425 | #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15) | ||
| 426 | #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14) | ||
| 427 | #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13) | ||
| 428 | #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12) | ||
| 429 | #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 ) | ||
| 430 | #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 ) | ||
| 431 | |||
| 432 | #define IOP13XX_ATUE_IALR_DISABLE (0x00000001) | ||
| 433 | #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000) | ||
| 434 | #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28) | ||
| 435 | #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) | ||
| 436 | /*=======================================================================*/ | ||
| 437 | |||
| 438 | /*==============================ADMA UNITS===============================*/ | ||
| 439 | #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) | ||
| 440 | #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) | ||
| 441 | #define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs)) | ||
| 442 | |||
| 443 | #define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0) | ||
| 444 | #define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4) | ||
| 445 | #define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8) | ||
| 446 | #define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18) | ||
| 447 | #define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c) | ||
| 448 | #define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20) | ||
| 449 | #define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24) | ||
| 450 | #define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28) | ||
| 451 | #define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c) | ||
| 452 | #define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30) | ||
| 453 | #define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34) | ||
| 454 | #define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38) | ||
| 455 | #define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3)) | ||
| 456 | #define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3)) | ||
| 457 | |||
| 458 | /*==============================XSI BRIDGE===============================*/ | ||
| 459 | #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) | ||
| 460 | #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790) | ||
| 461 | #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794) | ||
| 462 | #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ | ||
| 463 | IOP13XX_PMMR_VIRT_TO_PHYS(\ | ||
| 464 | IOP13XX_ATUE_OCCDR))\ | ||
| 465 | && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) | ||
| 466 | #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ | ||
| 467 | IOP13XX_PMMR_VIRT_TO_PHYS(\ | ||
| 468 | IOP13XX_ATUX_OCCDR))\ | ||
| 469 | && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) | ||
| 470 | /*=======================================================================*/ | ||
| 471 | |||
| 472 | #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\ | ||
| 473 | (ofs)) | ||
| 474 | |||
| 475 | #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0) | ||
| 476 | #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4) | ||
| 477 | #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8) | ||
| 478 | #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc) | ||
| 479 | #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) | ||
| 480 | #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) | ||
| 481 | |||
| 482 | #define IOP13XX_TMR_TC 0x01 | ||
| 483 | #define IOP13XX_TMR_EN 0x02 | ||
| 484 | #define IOP13XX_TMR_RELOAD 0x04 | ||
| 485 | #define IOP13XX_TMR_PRIVILEGED 0x08 | ||
| 486 | |||
| 487 | #define IOP13XX_TMR_RATIO_1_1 0x00 | ||
| 488 | #define IOP13XX_TMR_RATIO_4_1 0x10 | ||
| 489 | #define IOP13XX_TMR_RATIO_8_1 0x20 | ||
| 490 | #define IOP13XX_TMR_RATIO_16_1 0x30 | ||
| 491 | |||
| 492 | #endif /* _IOP13XX_HW_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h new file mode 100644 index 000000000000..b98f8f109c22 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/iq81340.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _IQ81340_H_ | ||
| 2 | #define _IQ81340_H_ | ||
| 3 | |||
| 4 | #define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA | ||
| 5 | #define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000) | ||
| 6 | |||
| 7 | #define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */ | ||
| 8 | |||
| 9 | #define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a)) | ||
| 10 | |||
| 11 | #define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0) | ||
| 12 | #define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000) | ||
| 13 | #define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000) | ||
| 14 | #define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000) | ||
| 15 | #define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000) | ||
| 16 | #define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000) | ||
| 17 | #define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000) | ||
| 18 | #define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000) | ||
| 19 | #define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000) | ||
| 20 | #define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000) | ||
| 21 | #define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000) | ||
| 22 | #define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */ | ||
| 23 | |||
| 24 | #define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH) | ||
| 25 | #define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1) | ||
| 26 | |||
| 27 | /* These are the values used in the Machine description */ | ||
| 28 | #define PHYS_IO 0xfeffff00 | ||
| 29 | #define IO_PG_OFFSET 0xffffff00 | ||
| 30 | #define BOOT_PARAM_OFFSET 0x00000100 | ||
| 31 | #endif /* _IQ81340_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h new file mode 100644 index 000000000000..442e35a40359 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/irqs.h | |||
| @@ -0,0 +1,207 @@ | |||
| 1 | #ifndef _IOP13XX_IRQS_H_ | ||
| 2 | #define _IOP13XX_IRQS_H_ | ||
| 3 | |||
| 4 | #ifndef __ASSEMBLER__ | ||
| 5 | #include <linux/types.h> | ||
| 6 | #include <asm/system.h> /* local_irq_save */ | ||
| 7 | #include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */ | ||
| 8 | |||
| 9 | /* INTPND0 CP6 R0 Page 3 | ||
| 10 | */ | ||
| 11 | static inline u32 read_intpnd_0(void) | ||
| 12 | { | ||
| 13 | u32 val; | ||
| 14 | asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); | ||
| 15 | return val; | ||
| 16 | } | ||
| 17 | |||
| 18 | /* INTPND1 CP6 R1 Page 3 | ||
| 19 | */ | ||
| 20 | static inline u32 read_intpnd_1(void) | ||
| 21 | { | ||
| 22 | u32 val; | ||
| 23 | asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); | ||
| 24 | return val; | ||
| 25 | } | ||
| 26 | |||
| 27 | /* INTPND2 CP6 R2 Page 3 | ||
| 28 | */ | ||
| 29 | static inline u32 read_intpnd_2(void) | ||
| 30 | { | ||
| 31 | u32 val; | ||
| 32 | asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); | ||
| 33 | return val; | ||
| 34 | } | ||
| 35 | |||
| 36 | /* INTPND3 CP6 R3 Page 3 | ||
| 37 | */ | ||
| 38 | static inline u32 read_intpnd_3(void) | ||
| 39 | { | ||
| 40 | u32 val; | ||
| 41 | asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); | ||
| 42 | return val; | ||
| 43 | } | ||
| 44 | |||
| 45 | static inline void | ||
| 46 | iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags) | ||
| 47 | { | ||
| 48 | local_irq_save(*irq_flags); | ||
| 49 | *cp_flags = iop13xx_cp6_save(); | ||
| 50 | } | ||
| 51 | |||
| 52 | static inline void | ||
| 53 | iop13xx_cp6_irq_restore(unsigned long *cp_flags, | ||
| 54 | unsigned long *irq_flags) | ||
| 55 | { | ||
| 56 | iop13xx_cp6_restore(*cp_flags); | ||
| 57 | local_irq_restore(*irq_flags); | ||
| 58 | } | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #define INTBASE 0 | ||
| 62 | #define INTSIZE_4 1 | ||
| 63 | |||
| 64 | /* | ||
| 65 | * iop34x chipset interrupts | ||
| 66 | */ | ||
| 67 | #define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x)) | ||
| 68 | |||
| 69 | /* | ||
| 70 | * On IRQ or FIQ register | ||
| 71 | */ | ||
| 72 | #define IRQ_IOP13XX_ADMA0_EOT (0) | ||
| 73 | #define IRQ_IOP13XX_ADMA0_EOC (1) | ||
| 74 | #define IRQ_IOP13XX_ADMA1_EOT (2) | ||
| 75 | #define IRQ_IOP13XX_ADMA1_EOC (3) | ||
| 76 | #define IRQ_IOP13XX_ADMA2_EOT (4) | ||
| 77 | #define IRQ_IOP13XX_ADMA2_EOC (5) | ||
| 78 | #define IRQ_IOP134_WATCHDOG (6) | ||
| 79 | #define IRQ_IOP13XX_RSVD_7 (7) | ||
| 80 | #define IRQ_IOP13XX_TIMER0 (8) | ||
| 81 | #define IRQ_IOP13XX_TIMER1 (9) | ||
| 82 | #define IRQ_IOP13XX_I2C_0 (10) | ||
| 83 | #define IRQ_IOP13XX_I2C_1 (11) | ||
| 84 | #define IRQ_IOP13XX_MSG (12) | ||
| 85 | #define IRQ_IOP13XX_MSGIBQ (13) | ||
| 86 | #define IRQ_IOP13XX_ATU_IM (14) | ||
| 87 | #define IRQ_IOP13XX_ATU_BIST (15) | ||
| 88 | #define IRQ_IOP13XX_PPMU (16) | ||
| 89 | #define IRQ_IOP13XX_COREPMU (17) | ||
| 90 | #define IRQ_IOP13XX_CORECACHE (18) | ||
| 91 | #define IRQ_IOP13XX_RSVD_19 (19) | ||
| 92 | #define IRQ_IOP13XX_RSVD_20 (20) | ||
| 93 | #define IRQ_IOP13XX_RSVD_21 (21) | ||
| 94 | #define IRQ_IOP13XX_RSVD_22 (22) | ||
| 95 | #define IRQ_IOP13XX_RSVD_23 (23) | ||
| 96 | #define IRQ_IOP13XX_XINT0 (24) | ||
| 97 | #define IRQ_IOP13XX_XINT1 (25) | ||
| 98 | #define IRQ_IOP13XX_XINT2 (26) | ||
| 99 | #define IRQ_IOP13XX_XINT3 (27) | ||
| 100 | #define IRQ_IOP13XX_XINT4 (28) | ||
| 101 | #define IRQ_IOP13XX_XINT5 (29) | ||
| 102 | #define IRQ_IOP13XX_XINT6 (30) | ||
| 103 | #define IRQ_IOP13XX_XINT7 (31) | ||
| 104 | /* IINTSRC1 bit */ | ||
| 105 | #define IRQ_IOP13XX_XINT8 (32) /* 0 */ | ||
| 106 | #define IRQ_IOP13XX_XINT9 (33) /* 1 */ | ||
| 107 | #define IRQ_IOP13XX_XINT10 (34) /* 2 */ | ||
| 108 | #define IRQ_IOP13XX_XINT11 (35) /* 3 */ | ||
| 109 | #define IRQ_IOP13XX_XINT12 (36) /* 4 */ | ||
| 110 | #define IRQ_IOP13XX_XINT13 (37) /* 5 */ | ||
| 111 | #define IRQ_IOP13XX_XINT14 (38) /* 6 */ | ||
| 112 | #define IRQ_IOP13XX_XINT15 (39) /* 7 */ | ||
| 113 | #define IRQ_IOP13XX_RSVD_40 (40) /* 8 */ | ||
| 114 | #define IRQ_IOP13XX_RSVD_41 (41) /* 9 */ | ||
| 115 | #define IRQ_IOP13XX_RSVD_42 (42) /* 10 */ | ||
| 116 | #define IRQ_IOP13XX_RSVD_43 (43) /* 11 */ | ||
| 117 | #define IRQ_IOP13XX_RSVD_44 (44) /* 12 */ | ||
| 118 | #define IRQ_IOP13XX_RSVD_45 (45) /* 13 */ | ||
| 119 | #define IRQ_IOP13XX_RSVD_46 (46) /* 14 */ | ||
| 120 | #define IRQ_IOP13XX_RSVD_47 (47) /* 15 */ | ||
| 121 | #define IRQ_IOP13XX_RSVD_48 (48) /* 16 */ | ||
| 122 | #define IRQ_IOP13XX_RSVD_49 (49) /* 17 */ | ||
| 123 | #define IRQ_IOP13XX_RSVD_50 (50) /* 18 */ | ||
| 124 | #define IRQ_IOP13XX_UART0 (51) /* 19 */ | ||
| 125 | #define IRQ_IOP13XX_UART1 (52) /* 20 */ | ||
| 126 | #define IRQ_IOP13XX_PBIE (53) /* 21 */ | ||
| 127 | #define IRQ_IOP13XX_ATU_CRW (54) /* 22 */ | ||
| 128 | #define IRQ_IOP13XX_ATU_ERR (55) /* 23 */ | ||
| 129 | #define IRQ_IOP13XX_MCU_ERR (56) /* 24 */ | ||
| 130 | #define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */ | ||
| 131 | #define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */ | ||
| 132 | #define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */ | ||
| 133 | #define IRQ_IOP13XX_RSVD_60 (60) /* 28 */ | ||
| 134 | #define IRQ_IOP13XX_RSVD_61 (61) /* 29 */ | ||
| 135 | #define IRQ_IOP13XX_MSG_ERR (62) /* 30 */ | ||
| 136 | #define IRQ_IOP13XX_RSVD_63 (63) /* 31 */ | ||
| 137 | /* IINTSRC2 bit */ | ||
| 138 | #define IRQ_IOP13XX_INTERPROC (64) /* 0 */ | ||
| 139 | #define IRQ_IOP13XX_RSVD_65 (65) /* 1 */ | ||
| 140 | #define IRQ_IOP13XX_RSVD_66 (66) /* 2 */ | ||
| 141 | #define IRQ_IOP13XX_RSVD_67 (67) /* 3 */ | ||
| 142 | #define IRQ_IOP13XX_RSVD_68 (68) /* 4 */ | ||
| 143 | #define IRQ_IOP13XX_RSVD_69 (69) /* 5 */ | ||
| 144 | #define IRQ_IOP13XX_RSVD_70 (70) /* 6 */ | ||
| 145 | #define IRQ_IOP13XX_RSVD_71 (71) /* 7 */ | ||
| 146 | #define IRQ_IOP13XX_RSVD_72 (72) /* 8 */ | ||
| 147 | #define IRQ_IOP13XX_RSVD_73 (73) /* 9 */ | ||
| 148 | #define IRQ_IOP13XX_RSVD_74 (74) /* 10 */ | ||
| 149 | #define IRQ_IOP13XX_RSVD_75 (75) /* 11 */ | ||
| 150 | #define IRQ_IOP13XX_RSVD_76 (76) /* 12 */ | ||
| 151 | #define IRQ_IOP13XX_RSVD_77 (77) /* 13 */ | ||
| 152 | #define IRQ_IOP13XX_RSVD_78 (78) /* 14 */ | ||
| 153 | #define IRQ_IOP13XX_RSVD_79 (79) /* 15 */ | ||
| 154 | #define IRQ_IOP13XX_RSVD_80 (80) /* 16 */ | ||
| 155 | #define IRQ_IOP13XX_RSVD_81 (81) /* 17 */ | ||
| 156 | #define IRQ_IOP13XX_RSVD_82 (82) /* 18 */ | ||
| 157 | #define IRQ_IOP13XX_RSVD_83 (83) /* 19 */ | ||
| 158 | #define IRQ_IOP13XX_RSVD_84 (84) /* 20 */ | ||
| 159 | #define IRQ_IOP13XX_RSVD_85 (85) /* 21 */ | ||
| 160 | #define IRQ_IOP13XX_RSVD_86 (86) /* 22 */ | ||
| 161 | #define IRQ_IOP13XX_RSVD_87 (87) /* 23 */ | ||
| 162 | #define IRQ_IOP13XX_RSVD_88 (88) /* 24 */ | ||
| 163 | #define IRQ_IOP13XX_RSVD_89 (89) /* 25 */ | ||
| 164 | #define IRQ_IOP13XX_RSVD_90 (90) /* 26 */ | ||
| 165 | #define IRQ_IOP13XX_RSVD_91 (91) /* 27 */ | ||
| 166 | #define IRQ_IOP13XX_RSVD_92 (92) /* 28 */ | ||
| 167 | #define IRQ_IOP13XX_RSVD_93 (93) /* 29 */ | ||
| 168 | #define IRQ_IOP13XX_SIB_ERR (94) /* 30 */ | ||
| 169 | #define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */ | ||
| 170 | /* IINTSRC3 bit */ | ||
| 171 | #define IRQ_IOP13XX_I2C_2 (96) /* 0 */ | ||
| 172 | #define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */ | ||
| 173 | #define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */ | ||
| 174 | #define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */ | ||
| 175 | #define IRQ_IOP13XX_IMU (100) /* 4 */ | ||
| 176 | #define IRQ_IOP13XX_RSVD_101 (101) /* 5 */ | ||
| 177 | #define IRQ_IOP13XX_RSVD_102 (102) /* 6 */ | ||
| 178 | #define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */ | ||
| 179 | #define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */ | ||
| 180 | #define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */ | ||
| 181 | #define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */ | ||
| 182 | #define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */ | ||
| 183 | #define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */ | ||
| 184 | #define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */ | ||
| 185 | #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ | ||
| 186 | #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ | ||
| 187 | #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ | ||
| 188 | #define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ | ||
| 189 | #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ | ||
| 190 | #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ | ||
| 191 | #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ | ||
| 192 | #define IRQ_IOP13XX_RSVD_117 (117) /* 21 */ | ||
| 193 | #define IRQ_IOP13XX_RSVD_118 (118) /* 22 */ | ||
| 194 | #define IRQ_IOP13XX_RSVD_119 (119) /* 23 */ | ||
| 195 | #define IRQ_IOP13XX_RSVD_120 (120) /* 24 */ | ||
| 196 | #define IRQ_IOP13XX_RSVD_121 (121) /* 25 */ | ||
| 197 | #define IRQ_IOP13XX_RSVD_122 (122) /* 26 */ | ||
| 198 | #define IRQ_IOP13XX_RSVD_123 (123) /* 27 */ | ||
| 199 | #define IRQ_IOP13XX_RSVD_124 (124) /* 28 */ | ||
| 200 | #define IRQ_IOP13XX_RSVD_125 (125) /* 29 */ | ||
| 201 | #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ | ||
| 202 | #define IRQ_IOP13XX_HPI (127) /* 31 */ | ||
| 203 | |||
| 204 | #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) | ||
| 205 | #define NR_IRQS NR_IOP13XX_IRQS | ||
| 206 | |||
| 207 | #endif /* _IOP13XX_IRQ_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h new file mode 100644 index 000000000000..031a0fa78eff --- /dev/null +++ b/include/asm-arm/arch-iop13xx/memory.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 2 | #define __ASM_ARCH_MEMORY_H | ||
| 3 | |||
| 4 | #include <asm/arch/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Physical DRAM offset. | ||
| 8 | */ | ||
| 9 | #define PHYS_OFFSET UL(0x00000000) | ||
| 10 | #define TASK_SIZE UL(0x3f000000) | ||
| 11 | #define PAGE_OFFSET UL(0x40000000) | ||
| 12 | #define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3) | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | #if defined(CONFIG_ARCH_IOP13XX) | ||
| 17 | #define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE) | ||
| 18 | #define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE) | ||
| 19 | #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) | ||
| 20 | #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Virtual view <-> PCI DMA view memory address translations | ||
| 24 | * virt_to_bus: Used to translate the virtual address to an | ||
| 25 | * address suitable to be passed to set_dma_addr | ||
| 26 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 27 | * to an address that the kernel can use. | ||
| 28 | */ | ||
| 29 | |||
| 30 | /* RAM has 1:1 mapping on the PCIe/x Busses */ | ||
| 31 | #define __virt_to_bus(x) (__virt_to_phys(x)) | ||
| 32 | #define __bus_to_virt(x) (__phys_to_virt(x)) | ||
| 33 | |||
| 34 | #define virt_to_lbus(x) \ | ||
| 35 | (( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \ | ||
| 36 | ((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \ | ||
| 37 | ((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \ | ||
| 38 | ((x) - PAGE_OFFSET + PHYS_OFFSET)) | ||
| 39 | |||
| 40 | #define lbus_to_virt(x) \ | ||
| 41 | (( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \ | ||
| 42 | ((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \ | ||
| 43 | ((x) - PHYS_OFFSET + PAGE_OFFSET)) | ||
| 44 | |||
| 45 | /* Device is an lbus device if it is on the platform bus of the IOP13XX */ | ||
| 46 | #define is_lbus_device(dev) (dev &&\ | ||
| 47 | (strncmp(dev->bus->name, "platform", 8) == 0)) | ||
| 48 | |||
| 49 | #define __arch_page_to_dma(dev, page) \ | ||
| 50 | ({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \ | ||
| 51 | (dma_addr_t)__virt_to_bus(page_address(page));}) | ||
| 52 | |||
| 53 | #define __arch_dma_to_virt(dev, addr) \ | ||
| 54 | ({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);}) | ||
| 55 | |||
| 56 | #define __arch_virt_to_dma(dev, addr) \ | ||
| 57 | ({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);}) | ||
| 58 | |||
| 59 | #endif /* CONFIG_ARCH_IOP13XX */ | ||
| 60 | #endif /* !ASSEMBLY */ | ||
| 61 | |||
| 62 | #define PFN_TO_NID(addr) (0) | ||
| 63 | |||
| 64 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h new file mode 100644 index 000000000000..4041f30d4cd3 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/pci.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | #ifndef _IOP13XX_PCI_H_ | ||
| 2 | #define _IOP13XX_PCI_H_ | ||
| 3 | #include <asm/arch/irqs.h> | ||
| 4 | #include <asm/io.h> | ||
| 5 | |||
| 6 | struct pci_sys_data; | ||
| 7 | struct hw_pci; | ||
| 8 | int iop13xx_pci_setup(int nr, struct pci_sys_data *sys); | ||
| 9 | struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *); | ||
| 10 | void iop13xx_atu_select(struct hw_pci *plat_pci); | ||
| 11 | void iop13xx_pci_init(void); | ||
| 12 | void iop13xx_map_pci_memory(void); | ||
| 13 | |||
| 14 | #define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \ | ||
| 15 | PCI_STATUS_SIG_TARGET_ABORT | \ | ||
| 16 | PCI_STATUS_REC_TARGET_ABORT | \ | ||
| 17 | PCI_STATUS_REC_TARGET_ABORT | \ | ||
| 18 | PCI_STATUS_REC_MASTER_ABORT | \ | ||
| 19 | PCI_STATUS_SIG_SYSTEM_ERROR | \ | ||
| 20 | PCI_STATUS_DETECTED_PARITY) | ||
| 21 | |||
| 22 | #define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \ | ||
| 23 | IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \ | ||
| 24 | IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \ | ||
| 25 | IOP13XX_ATUE_STAT_ERR_COR | \ | ||
| 26 | IOP13XX_ATUE_STAT_ERR_UNCOR | \ | ||
| 27 | IOP13XX_ATUE_STAT_CRS | \ | ||
| 28 | IOP13XX_ATUE_STAT_DET_PAR_ERR | \ | ||
| 29 | IOP13XX_ATUE_STAT_EXT_REC_MABORT | \ | ||
| 30 | IOP13XX_ATUE_STAT_SIG_TABORT | \ | ||
| 31 | IOP13XX_ATUE_STAT_EXT_REC_TABORT | \ | ||
| 32 | IOP13XX_ATUE_STAT_MASTER_DATA_PAR) | ||
| 33 | |||
| 34 | #define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \ | ||
| 35 | IOP13XX_ATUX_STAT_REC_SCEM | \ | ||
| 36 | IOP13XX_ATUX_STAT_TX_SERR | \ | ||
| 37 | IOP13XX_ATUX_STAT_DET_PAR_ERR | \ | ||
| 38 | IOP13XX_ATUX_STAT_INT_REC_MABORT | \ | ||
| 39 | IOP13XX_ATUX_STAT_REC_SERR | \ | ||
| 40 | IOP13XX_ATUX_STAT_EXT_REC_MABORT | \ | ||
| 41 | IOP13XX_ATUX_STAT_EXT_REC_TABORT | \ | ||
| 42 | IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \ | ||
| 43 | IOP13XX_ATUX_STAT_MASTER_DATA_PAR) | ||
| 44 | |||
| 45 | /* PCI interrupts | ||
| 46 | */ | ||
| 47 | #define ATUX_INTA IRQ_IOP13XX_XINT0 | ||
| 48 | #define ATUX_INTB IRQ_IOP13XX_XINT1 | ||
| 49 | #define ATUX_INTC IRQ_IOP13XX_XINT2 | ||
| 50 | #define ATUX_INTD IRQ_IOP13XX_XINT3 | ||
| 51 | |||
| 52 | #define ATUE_INTA IRQ_IOP13XX_ATUE_IMA | ||
| 53 | #define ATUE_INTB IRQ_IOP13XX_ATUE_IMB | ||
| 54 | #define ATUE_INTC IRQ_IOP13XX_ATUE_IMC | ||
| 55 | #define ATUE_INTD IRQ_IOP13XX_ATUE_IMD | ||
| 56 | |||
| 57 | #endif /* _IOP13XX_PCI_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h new file mode 100644 index 000000000000..ee3a62530af2 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/system.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-iop13xx/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Intel Corp. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/iop13xx.h> | ||
| 11 | static inline void arch_idle(void) | ||
| 12 | { | ||
| 13 | cpu_do_idle(); | ||
| 14 | } | ||
| 15 | |||
| 16 | /* WDTCR CP6 R7 Page 9 */ | ||
| 17 | static inline u32 read_wdtcr(void) | ||
| 18 | { | ||
| 19 | u32 val; | ||
| 20 | asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); | ||
| 21 | return val; | ||
| 22 | } | ||
| 23 | static inline void write_wdtcr(u32 val) | ||
| 24 | { | ||
| 25 | asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); | ||
| 26 | } | ||
| 27 | |||
| 28 | /* WDTSR CP6 R8 Page 9 */ | ||
| 29 | static inline u32 read_wdtsr(void) | ||
| 30 | { | ||
| 31 | u32 val; | ||
| 32 | asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); | ||
| 33 | return val; | ||
| 34 | } | ||
| 35 | static inline void write_wdtsr(u32 val) | ||
| 36 | { | ||
| 37 | asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); | ||
| 38 | } | ||
| 39 | |||
| 40 | #define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e | ||
| 41 | #define IOP13XX_WDTCR_EN 0xe1e1e1e1 | ||
| 42 | #define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f | ||
| 43 | #define IOP13XX_WDTCR_DIS 0xf1f1f1f1 | ||
| 44 | #define IOP13XX_WDTSR_WRITE_EN (1 << 31) | ||
| 45 | #define IOP13XX_WDTCR_IB_RESET (1 << 0) | ||
| 46 | static inline void arch_reset(char mode) | ||
| 47 | { | ||
| 48 | /* | ||
| 49 | * Reset the internal bus (warning both cores are reset) | ||
| 50 | */ | ||
| 51 | u32 cp_flags = iop13xx_cp6_save(); | ||
| 52 | write_wdtcr(IOP13XX_WDTCR_EN_ARM); | ||
| 53 | write_wdtcr(IOP13XX_WDTCR_EN); | ||
| 54 | write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); | ||
| 55 | write_wdtcr(0x1000); | ||
| 56 | iop13xx_cp6_restore(cp_flags); | ||
| 57 | |||
| 58 | for(;;); | ||
| 59 | } | ||
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h new file mode 100644 index 000000000000..f0c51dd97ed8 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/timex.h | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | #include <asm/hardware.h> | ||
| 2 | |||
| 3 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h new file mode 100644 index 000000000000..b9525d59b7ad --- /dev/null +++ b/include/asm-arm/arch-iop13xx/uncompress.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | #include <asm/types.h> | ||
| 2 | #include <linux/serial_reg.h> | ||
| 3 | #include <asm/hardware.h> | ||
| 4 | #include <asm/processor.h> | ||
| 5 | |||
| 6 | #define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) | ||
| 7 | #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) | ||
| 8 | |||
| 9 | static inline void putc(char c) | ||
| 10 | { | ||
| 11 | while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) | ||
| 12 | cpu_relax(); | ||
| 13 | UART_BASE[UART_TX] = c; | ||
| 14 | } | ||
| 15 | |||
| 16 | static inline void flush(void) | ||
| 17 | { | ||
| 18 | } | ||
| 19 | |||
| 20 | /* | ||
| 21 | * nothing to do | ||
| 22 | */ | ||
| 23 | #define arch_decomp_setup() | ||
| 24 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h new file mode 100644 index 000000000000..c53456740345 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/vmalloc.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef _VMALLOC_H_ | ||
| 2 | #define _VMALLOC_H_ | ||
| 3 | #define VMALLOC_END 0xfa000000UL | ||
| 4 | #endif | ||
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h index 9f1a58cbf407..9b0c8012e713 100644 --- a/include/asm-arm/arch-lh7a40x/memory.h +++ b/include/asm-arm/arch-lh7a40x/memory.h | |||
| @@ -58,18 +58,6 @@ | |||
| 58 | #endif | 58 | #endif |
| 59 | 59 | ||
| 60 | /* | 60 | /* |
| 61 | * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory | ||
| 62 | * and return the mem_map of that node. | ||
| 63 | */ | ||
| 64 | # define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) | ||
| 65 | |||
| 66 | /* | ||
| 67 | * Given a page frame number, find the owning node of the memory | ||
| 68 | * and return the mem_map of that node. | ||
| 69 | */ | ||
| 70 | # define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | 61 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory |
| 74 | * and returns the index corresponding to the appropriate page in the | 62 | * and returns the index corresponding to the appropriate page in the |
| 75 | * node's mem_map. | 63 | * node's mem_map. |
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h index eaf6d43939e9..e17f9881faf0 100644 --- a/include/asm-arm/arch-pxa/memory.h +++ b/include/asm-arm/arch-pxa/memory.h | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #define __virt_to_bus(x) __virt_to_phys(x) | 27 | #define __virt_to_bus(x) __virt_to_phys(x) |
| 28 | #define __bus_to_virt(x) __phys_to_virt(x) | 28 | #define __bus_to_virt(x) __phys_to_virt(x) |
| 29 | 29 | ||
| 30 | #ifdef CONFIG_DISCONTIGMEM | ||
| 31 | /* | 30 | /* |
| 32 | * The nodes are matched with the physical SDRAM banks as follows: | 31 | * The nodes are matched with the physical SDRAM banks as follows: |
| 33 | * | 32 | * |
| @@ -35,38 +34,9 @@ | |||
| 35 | * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff | 34 | * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff |
| 36 | * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff | 35 | * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff |
| 37 | * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff | 36 | * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff |
| 37 | * | ||
| 38 | * This needs a node mem size of 26 bits. | ||
| 38 | */ | 39 | */ |
| 39 | 40 | #define NODE_MEM_SIZE_BITS 26 | |
| 40 | /* | ||
| 41 | * Given a kernel address, find the home node of the underlying memory. | ||
| 42 | */ | ||
| 43 | #define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26) | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Given a page frame number, convert it to a node id. | ||
| 47 | */ | ||
| 48 | #define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory | ||
| 52 | * and returns the mem_map of that node. | ||
| 53 | */ | ||
| 54 | #define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) | ||
| 55 | |||
| 56 | /* | ||
| 57 | * Given a page frame number, find the owning node of the memory | ||
| 58 | * and returns the mem_map of that node. | ||
| 59 | */ | ||
| 60 | #define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | ||
| 64 | * and returns the index corresponding to the appropriate page in the | ||
| 65 | * node's mem_map. | ||
| 66 | */ | ||
| 67 | #define LOCAL_MAP_NR(addr) \ | ||
| 68 | (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT) | ||
| 69 | |||
| 70 | #endif | ||
| 71 | 41 | ||
| 72 | #endif | 42 | #endif |
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h index 1ff172dc8e33..0e907fc6d42a 100644 --- a/include/asm-arm/arch-sa1100/memory.h +++ b/include/asm-arm/arch-sa1100/memory.h | |||
| @@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); | |||
| 39 | #define __virt_to_bus(x) __virt_to_phys(x) | 39 | #define __virt_to_bus(x) __virt_to_phys(x) |
| 40 | #define __bus_to_virt(x) __phys_to_virt(x) | 40 | #define __bus_to_virt(x) __phys_to_virt(x) |
| 41 | 41 | ||
| 42 | #ifdef CONFIG_DISCONTIGMEM | ||
| 43 | /* | 42 | /* |
| 44 | * Because of the wide memory address space between physical RAM banks on the | 43 | * Because of the wide memory address space between physical RAM banks on the |
| 45 | * SA1100, it's much convenient to use Linux's NUMA support to implement our | 44 | * SA1100, it's much convenient to use Linux's NUMA support to implement our |
| @@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); | |||
| 57 | * node 2: 0xd0000000 - 0xd7ffffff | 56 | * node 2: 0xd0000000 - 0xd7ffffff |
| 58 | * node 3: 0xd8000000 - 0xdfffffff | 57 | * node 3: 0xd8000000 - 0xdfffffff |
| 59 | */ | 58 | */ |
| 60 | 59 | #define NODE_MEM_SIZE_BITS 27 | |
| 61 | /* | ||
| 62 | * Given a kernel address, find the home node of the underlying memory. | ||
| 63 | */ | ||
| 64 | #define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27) | ||
| 65 | |||
| 66 | /* | ||
| 67 | * Given a page frame number, convert it to a node id. | ||
| 68 | */ | ||
| 69 | #define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT)) | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory | ||
| 73 | * and return the mem_map of that node. | ||
| 74 | */ | ||
| 75 | #define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) | ||
| 76 | |||
| 77 | /* | ||
| 78 | * Given a page frame number, find the owning node of the memory | ||
| 79 | * and return the mem_map of that node. | ||
| 80 | */ | ||
| 81 | #define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | ||
| 85 | * and returns the index corresponding to the appropriate page in the | ||
| 86 | * node's mem_map. | ||
| 87 | */ | ||
| 88 | #define LOCAL_MAP_NR(addr) \ | ||
| 89 | (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT) | ||
| 90 | |||
| 91 | #endif | ||
| 92 | 60 | ||
| 93 | /* | 61 | /* |
| 94 | * Cache flushing area - SA1100 zero bank | 62 | * Cache flushing area - SA1100 zero bank |
diff --git a/include/asm-arm/cnt32_to_63.h b/include/asm-arm/cnt32_to_63.h new file mode 100644 index 000000000000..480c873fa746 --- /dev/null +++ b/include/asm-arm/cnt32_to_63.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: December 3, 2006 | ||
| 6 | * Copyright: MontaVista Software, Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 | ||
| 10 | * as published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __INCLUDE_CNT32_TO_63_H__ | ||
| 14 | #define __INCLUDE_CNT32_TO_63_H__ | ||
| 15 | |||
| 16 | #include <linux/compiler.h> | ||
| 17 | #include <asm/types.h> | ||
| 18 | #include <asm/byteorder.h> | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Prototype: u64 cnt32_to_63(u32 cnt) | ||
| 22 | * Many hardware clock counters are only 32 bits wide and therefore have | ||
| 23 | * a relatively short period making wrap-arounds rather frequent. This | ||
| 24 | * is a problem when implementing sched_clock() for example, where a 64-bit | ||
| 25 | * non-wrapping monotonic value is expected to be returned. | ||
| 26 | * | ||
| 27 | * To overcome that limitation, let's extend a 32-bit counter to 63 bits | ||
| 28 | * in a completely lock free fashion. Bits 0 to 31 of the clock are provided | ||
| 29 | * by the hardware while bits 32 to 62 are stored in memory. The top bit in | ||
| 30 | * memory is used to synchronize with the hardware clock half-period. When | ||
| 31 | * the top bit of both counters (hardware and in memory) differ then the | ||
| 32 | * memory is updated with a new value, incrementing it when the hardware | ||
| 33 | * counter wraps around. | ||
| 34 | * | ||
| 35 | * Because a word store in memory is atomic then the incremented value will | ||
| 36 | * always be in synch with the top bit indicating to any potential concurrent | ||
| 37 | * reader if the value in memory is up to date or not with regards to the | ||
| 38 | * needed increment. And any race in updating the value in memory is harmless | ||
| 39 | * as the same value would simply be stored more than once. | ||
| 40 | * | ||
| 41 | * The only restriction for the algorithm to work properly is that this | ||
| 42 | * code must be executed at least once per each half period of the 32-bit | ||
| 43 | * counter to properly update the state bit in memory. This is usually not a | ||
| 44 | * problem in practice, but if it is then a kernel timer could be scheduled | ||
| 45 | * to manage for this code to be executed often enough. | ||
| 46 | * | ||
| 47 | * Note that the top bit (bit 63) in the returned value should be considered | ||
| 48 | * as garbage. It is not cleared here because callers are likely to use a | ||
| 49 | * multiplier on the returned value which can get rid of the top bit | ||
| 50 | * implicitly by making the multiplier even, therefore saving on a runtime | ||
| 51 | * clear-bit instruction. Otherwise caller must remember to clear the top | ||
| 52 | * bit explicitly. | ||
| 53 | */ | ||
| 54 | |||
| 55 | /* this is used only to give gcc a clue about good code generation */ | ||
| 56 | typedef union { | ||
| 57 | struct { | ||
| 58 | #if defined(__LITTLE_ENDIAN) | ||
| 59 | u32 lo, hi; | ||
| 60 | #elif defined(__BIG_ENDIAN) | ||
| 61 | u32 hi, lo; | ||
| 62 | #endif | ||
| 63 | }; | ||
| 64 | u64 val; | ||
| 65 | } cnt32_to_63_t; | ||
| 66 | |||
| 67 | #define cnt32_to_63(cnt_lo) \ | ||
| 68 | ({ \ | ||
| 69 | static volatile u32 __m_cnt_hi = 0; \ | ||
| 70 | cnt32_to_63_t __x; \ | ||
| 71 | __x.hi = __m_cnt_hi; \ | ||
| 72 | __x.lo = (cnt_lo); \ | ||
| 73 | if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \ | ||
| 74 | __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \ | ||
| 75 | __x.val; \ | ||
| 76 | }) | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/include/asm-arm/div64.h b/include/asm-arm/div64.h index 3682616804ca..37e0a96e8789 100644 --- a/include/asm-arm/div64.h +++ b/include/asm-arm/div64.h | |||
| @@ -27,7 +27,7 @@ | |||
| 27 | #define __xh "r1" | 27 | #define __xh "r1" |
| 28 | #endif | 28 | #endif |
| 29 | 29 | ||
| 30 | #define do_div(n,base) \ | 30 | #define __do_div_asm(n, base) \ |
| 31 | ({ \ | 31 | ({ \ |
| 32 | register unsigned int __base asm("r4") = base; \ | 32 | register unsigned int __base asm("r4") = base; \ |
| 33 | register unsigned long long __n asm("r0") = n; \ | 33 | register unsigned long long __n asm("r0") = n; \ |
| @@ -45,4 +45,182 @@ | |||
| 45 | __rem; \ | 45 | __rem; \ |
| 46 | }) | 46 | }) |
| 47 | 47 | ||
| 48 | #if __GNUC__ < 4 | ||
| 49 | |||
| 50 | /* | ||
| 51 | * gcc versions earlier than 4.0 are simply too problematic for the | ||
| 52 | * optimized implementation below. First there is gcc PR 15089 that | ||
| 53 | * tend to trig on more complex constructs, spurious .global __udivsi3 | ||
| 54 | * are inserted even if none of those symbols are referenced in the | ||
| 55 | * generated code, and those gcc versions are not able to do constant | ||
| 56 | * propagation on long long values anyway. | ||
| 57 | */ | ||
| 58 | #define do_div(n, base) __do_div_asm(n, base) | ||
| 59 | |||
| 60 | #elif __GNUC__ >= 4 | ||
| 61 | |||
| 62 | #include <asm/bug.h> | ||
| 63 | |||
| 64 | /* | ||
| 65 | * If the divisor happens to be constant, we determine the appropriate | ||
| 66 | * inverse at compile time to turn the division into a few inline | ||
| 67 | * multiplications instead which is much faster. And yet only if compiling | ||
| 68 | * for ARMv4 or higher (we need umull/umlal) and if the gcc version is | ||
| 69 | * sufficiently recent to perform proper long long constant propagation. | ||
| 70 | * (It is unfortunate that gcc doesn't perform all this internally.) | ||
| 71 | */ | ||
| 72 | #define do_div(n, base) \ | ||
| 73 | ({ \ | ||
| 74 | unsigned int __r, __b = (base); \ | ||
| 75 | if (!__builtin_constant_p(__b) || __b == 0 || \ | ||
| 76 | (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) { \ | ||
| 77 | /* non-constant divisor (or zero): slow path */ \ | ||
| 78 | __r = __do_div_asm(n, __b); \ | ||
| 79 | } else if ((__b & (__b - 1)) == 0) { \ | ||
| 80 | /* Trivial: __b is constant and a power of 2 */ \ | ||
| 81 | /* gcc does the right thing with this code. */ \ | ||
| 82 | __r = n; \ | ||
| 83 | __r &= (__b - 1); \ | ||
| 84 | n /= __b; \ | ||
| 85 | } else { \ | ||
| 86 | /* Multiply by inverse of __b: n/b = n*(p/b)/p */ \ | ||
| 87 | /* We rely on the fact that most of this code gets */ \ | ||
| 88 | /* optimized away at compile time due to constant */ \ | ||
| 89 | /* propagation and only a couple inline assembly */ \ | ||
| 90 | /* instructions should remain. Better avoid any */ \ | ||
| 91 | /* code construct that might prevent that. */ \ | ||
| 92 | unsigned long long __res, __x, __t, __m, __n = n; \ | ||
| 93 | unsigned int __c, __p, __z = 0; \ | ||
| 94 | /* preserve low part of n for reminder computation */ \ | ||
| 95 | __r = __n; \ | ||
| 96 | /* determine number of bits to represent __b */ \ | ||
| 97 | __p = 1 << __div64_fls(__b); \ | ||
| 98 | /* compute __m = ((__p << 64) + __b - 1) / __b */ \ | ||
| 99 | __m = (~0ULL / __b) * __p; \ | ||
| 100 | __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \ | ||
| 101 | /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \ | ||
| 102 | __x = ~0ULL / __b * __b - 1; \ | ||
| 103 | __res = (__m & 0xffffffff) * (__x & 0xffffffff); \ | ||
| 104 | __res >>= 32; \ | ||
| 105 | __res += (__m & 0xffffffff) * (__x >> 32); \ | ||
| 106 | __t = __res; \ | ||
| 107 | __res += (__x & 0xffffffff) * (__m >> 32); \ | ||
| 108 | __t = (__res < __t) ? (1ULL << 32) : 0; \ | ||
| 109 | __res = (__res >> 32) + __t; \ | ||
| 110 | __res += (__m >> 32) * (__x >> 32); \ | ||
| 111 | __res /= __p; \ | ||
| 112 | /* Now sanitize and optimize what we've got. */ \ | ||
| 113 | if (~0ULL % (__b / (__b & -__b)) == 0) { \ | ||
| 114 | /* those cases can be simplified with: */ \ | ||
| 115 | __n /= (__b & -__b); \ | ||
| 116 | __m = ~0ULL / (__b / (__b & -__b)); \ | ||
| 117 | __p = 1; \ | ||
| 118 | __c = 1; \ | ||
| 119 | } else if (__res != __x / __b) { \ | ||
| 120 | /* We can't get away without a correction */ \ | ||
| 121 | /* to compensate for bit truncation errors. */ \ | ||
| 122 | /* To avoid it we'd need an additional bit */ \ | ||
| 123 | /* to represent __m which would overflow it. */ \ | ||
| 124 | /* Instead we do m=p/b and n/b=(n*m+m)/p. */ \ | ||
| 125 | __c = 1; \ | ||
| 126 | /* Compute __m = (__p << 64) / __b */ \ | ||
| 127 | __m = (~0ULL / __b) * __p; \ | ||
| 128 | __m += ((~0ULL % __b + 1) * __p) / __b; \ | ||
| 129 | } else { \ | ||
| 130 | /* Reduce __m/__p, and try to clear bit 31 */ \ | ||
| 131 | /* of __m when possible otherwise that'll */ \ | ||
| 132 | /* need extra overflow handling later. */ \ | ||
| 133 | unsigned int __bits = -(__m & -__m); \ | ||
| 134 | __bits |= __m >> 32; \ | ||
| 135 | __bits = (~__bits) << 1; \ | ||
| 136 | /* If __bits == 0 then setting bit 31 is */ \ | ||
| 137 | /* unavoidable. Simply apply the maximum */ \ | ||
| 138 | /* possible reduction in that case. */ \ | ||
| 139 | /* Otherwise the MSB of __bits indicates the */ \ | ||
| 140 | /* best reduction we should apply. */ \ | ||
| 141 | if (!__bits) { \ | ||
| 142 | __p /= (__m & -__m); \ | ||
| 143 | __m /= (__m & -__m); \ | ||
| 144 | } else { \ | ||
| 145 | __p >>= __div64_fls(__bits); \ | ||
| 146 | __m >>= __div64_fls(__bits); \ | ||
| 147 | } \ | ||
| 148 | /* No correction needed. */ \ | ||
| 149 | __c = 0; \ | ||
| 150 | } \ | ||
| 151 | /* Now we have a combination of 2 conditions: */ \ | ||
| 152 | /* 1) whether or not we need a correction (__c), and */ \ | ||
| 153 | /* 2) whether or not there might be an overflow in */ \ | ||
| 154 | /* the cross product (__m & ((1<<63) | (1<<31))) */ \ | ||
| 155 | /* Select the best insn combination to perform the */ \ | ||
| 156 | /* actual __m * __n / (__p << 64) operation. */ \ | ||
| 157 | if (!__c) { \ | ||
| 158 | asm ( "umull %Q0, %R0, %1, %Q2\n\t" \ | ||
| 159 | "mov %Q0, #0" \ | ||
| 160 | : "=&r" (__res) \ | ||
| 161 | : "r" (__m), "r" (__n) \ | ||
| 162 | : "cc" ); \ | ||
| 163 | } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ | ||
| 164 | __res = __m; \ | ||
| 165 | asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \ | ||
| 166 | "mov %Q0, #0" \ | ||
| 167 | : "+r" (__res) \ | ||
| 168 | : "r" (__m), "r" (__n) \ | ||
| 169 | : "cc" ); \ | ||
| 170 | } else { \ | ||
| 171 | asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \ | ||
| 172 | "cmn %Q0, %Q1\n\t" \ | ||
| 173 | "adcs %R0, %R0, %R1\n\t" \ | ||
| 174 | "adc %Q0, %3, #0" \ | ||
| 175 | : "=&r" (__res) \ | ||
| 176 | : "r" (__m), "r" (__n), "r" (__z) \ | ||
| 177 | : "cc" ); \ | ||
| 178 | } \ | ||
| 179 | if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ | ||
| 180 | asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \ | ||
| 181 | "umlal %R0, %Q0, %Q1, %R2\n\t" \ | ||
| 182 | "mov %R0, #0\n\t" \ | ||
| 183 | "umlal %Q0, %R0, %R1, %R2" \ | ||
| 184 | : "+r" (__res) \ | ||
| 185 | : "r" (__m), "r" (__n) \ | ||
| 186 | : "cc" ); \ | ||
| 187 | } else { \ | ||
| 188 | asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \ | ||
| 189 | "umlal %R0, %1, %Q2, %R3\n\t" \ | ||
| 190 | "mov %R0, #0\n\t" \ | ||
| 191 | "adds %Q0, %1, %Q0\n\t" \ | ||
| 192 | "adc %R0, %R0, #0\n\t" \ | ||
| 193 | "umlal %Q0, %R0, %R2, %R3" \ | ||
| 194 | : "+r" (__res), "+r" (__z) \ | ||
| 195 | : "r" (__m), "r" (__n) \ | ||
| 196 | : "cc" ); \ | ||
| 197 | } \ | ||
| 198 | __res /= __p; \ | ||
| 199 | /* The reminder can be computed with 32-bit regs */ \ | ||
| 200 | /* only, and gcc is good at that. */ \ | ||
| 201 | { \ | ||
| 202 | unsigned int __res0 = __res; \ | ||
| 203 | unsigned int __b0 = __b; \ | ||
| 204 | __r -= __res0 * __b0; \ | ||
| 205 | } \ | ||
| 206 | /* BUG_ON(__r >= __b || __res * __b + __r != n); */ \ | ||
| 207 | n = __res; \ | ||
| 208 | } \ | ||
| 209 | __r; \ | ||
| 210 | }) | ||
| 211 | |||
| 212 | /* our own fls implementation to make sure constant propagation is fine */ | ||
| 213 | #define __div64_fls(bits) \ | ||
| 214 | ({ \ | ||
| 215 | unsigned int __left = (bits), __nr = 0; \ | ||
| 216 | if (__left & 0xffff0000) __nr += 16, __left >>= 16; \ | ||
| 217 | if (__left & 0x0000ff00) __nr += 8, __left >>= 8; \ | ||
| 218 | if (__left & 0x000000f0) __nr += 4, __left >>= 4; \ | ||
| 219 | if (__left & 0x0000000c) __nr += 2, __left >>= 2; \ | ||
| 220 | if (__left & 0x00000002) __nr += 1; \ | ||
| 221 | __nr; \ | ||
| 222 | }) | ||
| 223 | |||
| 224 | #endif | ||
| 225 | |||
| 48 | #endif | 226 | #endif |
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index 91d536c215d7..d9bfb39adabf 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h | |||
| @@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x) | |||
| 215 | * virt_addr_valid(k) indicates whether a virtual address is valid | 215 | * virt_addr_valid(k) indicates whether a virtual address is valid |
| 216 | */ | 216 | */ |
| 217 | #ifndef CONFIG_DISCONTIGMEM | 217 | #ifndef CONFIG_DISCONTIGMEM |
| 218 | |||
| 218 | #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET | 219 | #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET |
| 219 | #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) | 220 | #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) |
| 220 | 221 | ||
| @@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x) | |||
| 230 | * around in memory. | 231 | * around in memory. |
| 231 | */ | 232 | */ |
| 232 | #include <linux/numa.h> | 233 | #include <linux/numa.h> |
| 234 | |||
| 233 | #define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) | 235 | #define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) |
| 234 | #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) | 236 | #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) |
| 235 | 237 | ||
| @@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x) | |||
| 256 | */ | 258 | */ |
| 257 | #define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) | 259 | #define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) |
| 258 | 260 | ||
| 261 | /* | ||
| 262 | * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory | ||
| 263 | * and returns the mem_map of that node. | ||
| 264 | */ | ||
| 265 | #define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) | ||
| 266 | |||
| 267 | /* | ||
| 268 | * Given a page frame number, find the owning node of the memory | ||
| 269 | * and returns the mem_map of that node. | ||
| 270 | */ | ||
| 271 | #define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) | ||
| 272 | |||
| 273 | #ifdef NODE_MEM_SIZE_BITS | ||
| 274 | #define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1) | ||
| 275 | |||
| 276 | /* | ||
| 277 | * Given a kernel address, find the home node of the underlying memory. | ||
| 278 | */ | ||
| 279 | #define KVADDR_TO_NID(addr) \ | ||
| 280 | (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS) | ||
| 281 | |||
| 282 | /* | ||
| 283 | * Given a page frame number, convert it to a node id. | ||
| 284 | */ | ||
| 285 | #define PFN_TO_NID(pfn) \ | ||
| 286 | (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT)) | ||
| 287 | |||
| 288 | /* | ||
| 289 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | ||
| 290 | * and returns the index corresponding to the appropriate page in the | ||
| 291 | * node's mem_map. | ||
| 292 | */ | ||
| 293 | #define LOCAL_MAP_NR(addr) \ | ||
| 294 | (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT) | ||
| 295 | |||
| 296 | #endif /* NODE_MEM_SIZE_BITS */ | ||
| 297 | |||
| 259 | #endif /* !CONFIG_DISCONTIGMEM */ | 298 | #endif /* !CONFIG_DISCONTIGMEM */ |
| 260 | 299 | ||
| 261 | /* | 300 | /* |