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-rw-r--r--include/asm-arm/arch-at91/at91_ecc.h38
-rw-r--r--include/asm-arm/arch-at91/board.h4
-rw-r--r--include/asm-arm/arch-iop13xx/adma.h18
-rw-r--r--include/asm-arm/arch-pnx4008/irqs.h48
-rw-r--r--include/asm-arm/arch-pxa/cm-x270.h50
-rw-r--r--include/asm-arm/arch-pxa/eseries-gpio.h50
-rw-r--r--include/asm-arm/arch-pxa/eseries-irq.h27
-rw-r--r--include/asm-arm/arch-pxa/hardware.h33
-rw-r--r--include/asm-arm/arch-pxa/idp.h10
-rw-r--r--include/asm-arm/arch-pxa/irqs.h3
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa2xx.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa930.h491
-rw-r--r--include/asm-arm/arch-pxa/mfp.h8
-rw-r--r--include/asm-arm/arch-pxa/palmtx.h106
-rw-r--r--include/asm-arm/arch-pxa/pcm990_baseboard.h14
-rw-r--r--include/asm-arm/arch-pxa/pxa25x-udc.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa27x-udc.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx_spi.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx_nand.h2
-rw-r--r--include/asm-arm/arch-pxa/pxafb.h3
-rw-r--r--include/asm-arm/arch-pxa/regs-lcd.h6
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h16
-rw-r--r--include/asm-arm/arch-pxa/system.h17
-rw-r--r--include/asm-arm/arch-pxa/tosa.h50
-rw-r--r--include/asm-arm/arch-pxa/tosa_bt.h22
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h13
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h2
-rw-r--r--include/asm-arm/arch-sa1100/h3600.h5
-rw-r--r--include/asm-arm/arch-sa1100/ide.h2
-rw-r--r--include/asm-arm/bitops.h9
-rw-r--r--include/asm-arm/cacheflush.h21
-rw-r--r--include/asm-arm/dma-mapping.h2
-rw-r--r--include/asm-arm/hardware/iop3xx-adma.h4
-rw-r--r--include/asm-arm/ide.h4
-rw-r--r--include/asm-arm/irq.h17
-rw-r--r--include/asm-arm/kgdb.h104
-rw-r--r--include/asm-arm/kvm.h6
-rw-r--r--include/asm-arm/mach/udc_pxa2xx.h1
-rw-r--r--include/asm-arm/namei.h25
-rw-r--r--include/asm-arm/page-nommu.h4
-rw-r--r--include/asm-arm/page.h3
-rw-r--r--include/asm-arm/pci.h8
-rw-r--r--include/asm-arm/plat-orion/mv_xor.h28
-rw-r--r--include/asm-arm/plat-s3c/iic.h1
-rw-r--r--include/asm-arm/ptrace.h6
-rw-r--r--include/asm-arm/semaphore.h1
-rw-r--r--include/asm-arm/thread_info.h13
-rw-r--r--include/asm-arm/traps.h2
48 files changed, 1039 insertions, 265 deletions
diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h
deleted file mode 100644
index 1e5a8caca2d1..000000000000
--- a/include/asm-arm/arch-at91/at91_ecc.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * include/asm-arm/arch-at91/at91_ecc.h
3 *
4 * Error Corrected Code Controller (ECC) - System peripherals regsters.
5 * Based on AT91SAM9260 datasheet revision B.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef AT91_ECC_H
14#define AT91_ECC_H
15
16#define AT91_ECC_CR 0x00 /* Control register */
17#define AT91_ECC_RST (1 << 0) /* Reset parity */
18
19#define AT91_ECC_MR 0x04 /* Mode register */
20#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
21#define AT91_ECC_PAGESIZE_528 (0)
22#define AT91_ECC_PAGESIZE_1056 (1)
23#define AT91_ECC_PAGESIZE_2112 (2)
24#define AT91_ECC_PAGESIZE_4224 (3)
25
26#define AT91_ECC_SR 0x08 /* Status register */
27#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
28#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
29#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
30
31#define AT91_ECC_PR 0x0c /* Parity register */
32#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
33#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
34
35#define AT91_ECC_NPR 0x10 /* NParity register */
36#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
37
38#endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 94de788da76e..48bbd854f57d 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -89,7 +89,7 @@ struct at91_usbh_data {
89extern void __init at91_add_device_usbh(struct at91_usbh_data *data); 89extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
90 90
91 /* NAND / SmartMedia */ 91 /* NAND / SmartMedia */
92struct at91_nand_data { 92struct atmel_nand_data {
93 u8 enable_pin; /* chip enable */ 93 u8 enable_pin; /* chip enable */
94 u8 det_pin; /* card detect */ 94 u8 det_pin; /* card detect */
95 u8 rdy_pin; /* ready/busy */ 95 u8 rdy_pin; /* ready/busy */
@@ -98,7 +98,7 @@ struct at91_nand_data {
98 u8 bus_width_16; /* buswidth is 16 bit */ 98 u8 bus_width_16; /* buswidth is 16 bit */
99 struct mtd_partition* (*partition_info)(int, int*); 99 struct mtd_partition* (*partition_info)(int, int*);
100}; 100};
101extern void __init at91_add_device_nand(struct at91_nand_data *data); 101extern void __init at91_add_device_nand(struct atmel_nand_data *data);
102 102
103 /* I2C*/ 103 /* I2C*/
104extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); 104extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h
index 90d14ee564f5..ef4f5da2029f 100644
--- a/include/asm-arm/arch-iop13xx/adma.h
+++ b/include/asm-arm/arch-iop13xx/adma.h
@@ -198,17 +198,13 @@ iop_chan_memset_slot_count(size_t len, int *slots_per_op)
198static inline int 198static inline int
199iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) 199iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
200{ 200{
201 int num_slots; 201 static const char slot_count_table[] = { 1, 2, 2, 2,
202 /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1 202 2, 3, 3, 3,
203 * (1 source => 8 bytes) (1 slot => 32 bytes) 203 3, 4, 4, 4,
204 */ 204 4, 5, 5, 5,
205 num_slots = 1 + (((src_cnt - 1) << 3) >> 5); 205 };
206 if (((src_cnt - 1) << 3) & 0x1f) 206 *slots_per_op = slot_count_table[src_cnt - 1];
207 num_slots++; 207 return *slots_per_op;
208
209 *slots_per_op = num_slots;
210
211 return num_slots;
212} 208}
213 209
214#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) 210#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h
index 13ec7ed0f501..a25d18f2d87a 100644
--- a/include/asm-arm/arch-pnx4008/irqs.h
+++ b/include/asm-arm/arch-pnx4008/irqs.h
@@ -135,30 +135,30 @@
135 135
136#define PNX4008_IRQ_TYPES \ 136#define PNX4008_IRQ_TYPES \
137{ /*IRQ #'s: */ \ 137{ /*IRQ #'s: */ \
138IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \ 138IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \
139IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \ 139IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \
140IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \ 140IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \
141IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \ 141IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \
142IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \ 142IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \
143IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \ 143IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \
144IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \ 144IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \
145IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \ 145IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \
146IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \ 146IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \
147IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \ 147IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \
148IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \ 148IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \
149IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \ 149IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \
150IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \ 150IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \
151IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \ 151IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \
152IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \ 152IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \
153IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \ 153IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \
154IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \ 154IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \
155IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \ 155IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \
156IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \ 156IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \
157IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \ 157IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \
158IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \ 158IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \
159IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \ 159IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \
160IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \ 160IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \
161IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \ 161IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \
162} 162}
163 163
164/* Start Enable Pin Interrupts - table 58 page 66 */ 164/* Start Enable Pin Interrupts - table 58 page 66 */
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
deleted file mode 100644
index f8fac9e18009..000000000000
--- a/include/asm-arm/arch-pxa/cm-x270.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * linux/include/asm/arch-pxa/cm-x270.h
3 *
4 * Copyright Compulab Ltd., 2003, 2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12
13/* CM-x270 device physical addresses */
14#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
15#define MARATHON_PHYS (PXA_CS2_PHYS)
16#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
17#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
18
19/* Statically mapped regions */
20#define CMX270_VIRT_BASE (0xe8000000)
21#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
22#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M)
23
24/* GPIO related definitions */
25#define GPIO_IT8152_IRQ (22)
26
27#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
28#define PME_IRQ IRQ_GPIO(0)
29#define CMX270_IDE_IRQ IRQ_GPIO(100)
30#define CMX270_GPIRQ1 IRQ_GPIO(101)
31#define CMX270_TOUCHIRQ IRQ_GPIO(96)
32#define CMX270_ETHIRQ IRQ_GPIO(10)
33#define CMX270_GFXIRQ IRQ_GPIO(95)
34#define CMX270_NANDIRQ IRQ_GPIO(89)
35#define CMX270_MMC_IRQ IRQ_GPIO(83)
36
37/* PCMCIA related definitions */
38#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
39#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
40
41#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
42#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
43
44#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
45#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
46
47#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
48#define PCMCIA_S1_RDYINT IRQ_GPIO(81)
49
50#define PCMCIA_RESET_GPIO 53
diff --git a/include/asm-arm/arch-pxa/eseries-gpio.h b/include/asm-arm/arch-pxa/eseries-gpio.h
new file mode 100644
index 000000000000..4c90b1310270
--- /dev/null
+++ b/include/asm-arm/arch-pxa/eseries-gpio.h
@@ -0,0 +1,50 @@
1/*
2 * eseries-gpio.h
3 *
4 * Copyright (C) Ian Molton <spyro@f2s.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/* e-series power button */
13#define GPIO_ESERIES_POWERBTN 0
14
15/* UDC GPIO definitions */
16#define GPIO_E7XX_USB_DISC 13
17#define GPIO_E7XX_USB_PULLUP 3
18
19#define GPIO_E800_USB_DISC 4
20#define GPIO_E800_USB_PULLUP 84
21
22/* e740 PCMCIA GPIO definitions */
23/* Note: PWR1 seems to be inverted */
24#define GPIO_E740_PCMCIA_CD0 8
25#define GPIO_E740_PCMCIA_CD1 44
26#define GPIO_E740_PCMCIA_RDY0 11
27#define GPIO_E740_PCMCIA_RDY1 6
28#define GPIO_E740_PCMCIA_RST0 27
29#define GPIO_E740_PCMCIA_RST1 24
30#define GPIO_E740_PCMCIA_PWR0 20
31#define GPIO_E740_PCMCIA_PWR1 23
32
33/* e750 PCMCIA GPIO definitions */
34#define GPIO_E750_PCMCIA_CD0 8
35#define GPIO_E750_PCMCIA_RDY0 12
36#define GPIO_E750_PCMCIA_RST0 27
37#define GPIO_E750_PCMCIA_PWR0 20
38
39/* e800 PCMCIA GPIO definitions */
40#define GPIO_E800_PCMCIA_RST0 69
41#define GPIO_E800_PCMCIA_RST1 72
42#define GPIO_E800_PCMCIA_PWR0 20
43#define GPIO_E800_PCMCIA_PWR1 73
44
45/* e7xx IrDA power control */
46#define GPIO_E7XX_IR_ON 38
47
48/* ASIC related GPIOs */
49#define GPIO_ESERIES_TMIO_IRQ 5
50#define GPIO_E800_ANGELX_IRQ 8
diff --git a/include/asm-arm/arch-pxa/eseries-irq.h b/include/asm-arm/arch-pxa/eseries-irq.h
new file mode 100644
index 000000000000..f2a93d5e31d3
--- /dev/null
+++ b/include/asm-arm/arch-pxa/eseries-irq.h
@@ -0,0 +1,27 @@
1/*
2 * eseries-irq.h
3 *
4 * Copyright (C) Ian Molton <spyro@f2s.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8)
13#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n))
14
15#define ANGELX_RDY0_IRQ IRQ_ANGELX(0)
16#define ANGELX_ST0_IRQ IRQ_ANGELX(1)
17#define ANGELX_CD0_IRQ IRQ_ANGELX(2)
18#define ANGELX_RDY1_IRQ IRQ_ANGELX(3)
19#define ANGELX_ST1_IRQ IRQ_ANGELX(4)
20#define ANGELX_CD1_IRQ IRQ_ANGELX(5)
21
22#define TMIO_IRQ_BASE (IRQ_BOARD_START+0)
23#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n))
24
25#define TMIO_SD_IRQ IRQ_TMIO(1)
26#define TMIO_USB_IRQ IRQ_TMIO(2)
27
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index d9af6dabc899..979a45695d7d 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -69,6 +69,12 @@
69 _id == 0x212; \ 69 _id == 0x212; \
70 }) 70 })
71 71
72#define __cpu_is_pxa255(id) \
73 ({ \
74 unsigned int _id = (id) >> 4 & 0xfff; \
75 _id == 0x2d0; \
76 })
77
72#define __cpu_is_pxa25x(id) \ 78#define __cpu_is_pxa25x(id) \
73 ({ \ 79 ({ \
74 unsigned int _id = (id) >> 4 & 0xfff; \ 80 unsigned int _id = (id) >> 4 & 0xfff; \
@@ -76,6 +82,7 @@
76 }) 82 })
77#else 83#else
78#define __cpu_is_pxa21x(id) (0) 84#define __cpu_is_pxa21x(id) (0)
85#define __cpu_is_pxa255(id) (0)
79#define __cpu_is_pxa25x(id) (0) 86#define __cpu_is_pxa25x(id) (0)
80#endif 87#endif
81 88
@@ -119,11 +126,26 @@
119#define __cpu_is_pxa320(id) (0) 126#define __cpu_is_pxa320(id) (0)
120#endif 127#endif
121 128
129#ifdef CONFIG_CPU_PXA930
130#define __cpu_is_pxa930(id) \
131 ({ \
132 unsigned int _id = (id) >> 4 & 0xfff; \
133 _id == 0x683; \
134 })
135#else
136#define __cpu_is_pxa930(id) (0)
137#endif
138
122#define cpu_is_pxa21x() \ 139#define cpu_is_pxa21x() \
123 ({ \ 140 ({ \
124 __cpu_is_pxa21x(read_cpuid_id()); \ 141 __cpu_is_pxa21x(read_cpuid_id()); \
125 }) 142 })
126 143
144#define cpu_is_pxa255() \
145 ({ \
146 __cpu_is_pxa255(read_cpuid_id()); \
147 })
148
127#define cpu_is_pxa25x() \ 149#define cpu_is_pxa25x() \
128 ({ \ 150 ({ \
129 __cpu_is_pxa25x(read_cpuid_id()); \ 151 __cpu_is_pxa25x(read_cpuid_id()); \
@@ -149,6 +171,12 @@
149 __cpu_is_pxa320(read_cpuid_id()); \ 171 __cpu_is_pxa320(read_cpuid_id()); \
150 }) 172 })
151 173
174#define cpu_is_pxa930() \
175 ({ \
176 unsigned int id = read_cpuid(CPUID_ID); \
177 __cpu_is_pxa930(id); \
178 })
179
152/* 180/*
153 * CPUID Core Generation Bit 181 * CPUID Core Generation Bit
154 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x 182 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
@@ -196,6 +224,11 @@ extern void pxa_gpio_set_value(unsigned gpio, int value);
196 */ 224 */
197extern unsigned int get_memclk_frequency_10khz(void); 225extern unsigned int get_memclk_frequency_10khz(void);
198 226
227/*
228 * register GPIO as reset generator
229 */
230extern int init_gpio_reset(int gpio);
231
199#endif 232#endif
200 233
201#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 234#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h
index b6952534a4e1..21aa8ac35c1c 100644
--- a/include/asm-arm/arch-pxa/idp.h
+++ b/include/asm-arm/arch-pxa/idp.h
@@ -138,18 +138,18 @@
138#define TOUCH_PANEL_IRQ IRQ_GPIO(5) 138#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
139#define IDE_IRQ IRQ_GPIO(21) 139#define IDE_IRQ IRQ_GPIO(21)
140 140
141#define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING 141#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
142 142
143#define ETHERNET_IRQ IRQ_GPIO(4) 143#define ETHERNET_IRQ IRQ_GPIO(4)
144#define ETHERNET_IRQ_EDGE IRQT_RISING 144#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
145 145
146#define IDE_IRQ_EDGE IRQT_RISING 146#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
147 147
148#define PCMCIA_S0_CD_VALID IRQ_GPIO(7) 148#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
149#define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE 149#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
150 150
151#define PCMCIA_S1_CD_VALID IRQ_GPIO(8) 151#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
152#define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE 152#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
153 153
154#define PCMCIA_S0_RDYINT IRQ_GPIO(19) 154#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
155#define PCMCIA_S1_RDYINT IRQ_GPIO(22) 155#define PCMCIA_S1_RDYINT IRQ_GPIO(22)
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index b6c8fe377683..9413121b0ed9 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -180,10 +180,13 @@
180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
181#elif defined(CONFIG_ARCH_LUBBOCK) || \ 181#elif defined(CONFIG_ARCH_LUBBOCK) || \
182 defined(CONFIG_MACH_LOGICPD_PXA270) || \ 182 defined(CONFIG_MACH_LOGICPD_PXA270) || \
183 defined(CONFIG_MACH_TOSA) || \
183 defined(CONFIG_MACH_MAINSTONE) || \ 184 defined(CONFIG_MACH_MAINSTONE) || \
184 defined(CONFIG_MACH_PCM027) || \ 185 defined(CONFIG_MACH_PCM027) || \
185 defined(CONFIG_MACH_MAGICIAN) 186 defined(CONFIG_MACH_MAGICIAN)
186#define NR_IRQS (IRQ_BOARD_END) 187#define NR_IRQS (IRQ_BOARD_END)
188#elif defined(CONFIG_MACH_ZYLONITE)
189#define NR_IRQS (IRQ_BOARD_START + 32)
187#else 190#else
188#define NR_IRQS (IRQ_BOARD_START) 191#define NR_IRQS (IRQ_BOARD_START)
189#endif 192#endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
index db8d890d237c..8de1c0dae624 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa2xx.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
@@ -128,5 +128,6 @@
128#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) 128#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0)
129 129
130extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); 130extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
131extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
131extern int gpio_set_wake(unsigned int gpio, unsigned int on); 132extern int gpio_set_wake(unsigned int gpio, unsigned int on);
132#endif /* __ASM_ARCH_MFP_PXA2XX_H */ 133#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa930.h b/include/asm-arm/arch-pxa/mfp-pxa930.h
new file mode 100644
index 000000000000..c4e945ab1923
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa930.h
@@ -0,0 +1,491 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa930.h
3 *
4 * PXA930 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007-2008 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_MFP_PXA9xx_H
14#define __ASM_ARCH_MFP_PXA9xx_H
15
16#include <asm/arch/mfp.h>
17#include <asm/arch/mfp-pxa3xx.h>
18
19/* GPIO */
20#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
21#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
22#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
23#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
24#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
25#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
26#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
27#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
28#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
29#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
30#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
31
32#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0)
33#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0)
34#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0)
35#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0)
36
37#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0)
38#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0)
39#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0)
40#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0)
41#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0)
42#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0)
43#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0)
44#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0)
45#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0)
46#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0)
47#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0)
48#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0)
49#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0)
50#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0)
51#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0)
52#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0)
53#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0)
54#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0)
55#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0)
56#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0)
57#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0)
58#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0)
59#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0)
60#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0)
61#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0)
62
63#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0)
64#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0)
65#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0)
66#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0)
67#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0)
68#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0)
69#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0)
70#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0)
71#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0)
72#define RDY_GPIO_62 MFP_CFG(RDY, AF0)
73
74/* Chip Select */
75#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
76#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
77
78/* AC97 */
79#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3)
80#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3)
81#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3)
82#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3)
83#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3)
84#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3)
85
86/* I2C */
87#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
88#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
89
90#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
91#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
92
93#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
94#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
95
96#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
97#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
98
99#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
100#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
101
102#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
103#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
104
105#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
106#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
107
108/* QCI */
109#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
110#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
111#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
112#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
113#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
114#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
115#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
116#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
117#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
118#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
119#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
120#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
121#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
122#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
123
124/* KEYPAD */
125#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT)
126#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT)
127#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT)
128#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT)
129#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT)
130#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
131#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
132#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT)
133
134#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT)
135#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT)
136#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT)
137#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT)
138
139#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT)
140#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT)
141#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT)
142#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT)
143#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT)
144#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT)
145
146#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT)
147#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT)
148#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT)
149#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT)
150#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT)
151#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT)
152#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT)
153#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1)
154#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4)
155
156#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
157#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
158#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
159#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
160#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
161#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
162#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
163#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
164#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
165
166/* LCD */
167#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1)
168#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1)
169#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1)
170#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1)
171#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1)
172#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2)
173#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1)
174#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1)
175#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1)
176#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1)
177#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1)
178#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1)
179#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1)
180#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1)
181#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1)
182#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1)
183#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1)
184#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1)
185#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1)
186#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1)
187#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1)
188#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1)
189#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1)
190#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1)
191#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1)
192#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3)
193#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3)
194#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1)
195
196/* Mini-LCD */
197#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3)
198#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3)
199#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3)
200#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3)
201#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3)
202#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3)
203#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3)
204#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3)
205#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3)
206#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3)
207#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3)
208#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3)
209#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3)
210#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3)
211#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3)
212#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3)
213#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3)
214#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3)
215#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3)
216#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3)
217#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5)
218
219/* MMC1 */
220#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4)
221#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4)
222#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4)
223#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4)
224#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4)
225#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4)
226#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3)
227#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3)
228#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3)
229#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3)
230#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3)
231#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3)
232
233#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2)
234#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2)
235#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2)
236#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3)
237#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2)
238
239/* MMC2 */
240#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7)
241#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7)
242#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7)
243#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7)
244#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7)
245#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7)
246
247#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1)
248#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1)
249#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1)
250#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1)
251#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1)
252#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1)
253
254#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3)
255#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3)
256#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3)
257#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3)
258#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3)
259#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3)
260
261/* BSSP1 */
262#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3)
263#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3)
264#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3)
265#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3)
266#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5)
267#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5)
268
269/* BSSP2 */
270#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1)
271#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1)
272#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1)
273#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1)
274#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1)
275#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4)
276
277/* BSSP3 */
278#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1)
279#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1)
280#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1)
281#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1)
282#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1)
283
284/* BSSP4 */
285#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4)
286#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4)
287#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4)
288#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4)
289
290#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4)
291#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4)
292#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4)
293#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4)
294
295/* GSSP1 */
296#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2)
297#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2)
298#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2)
299#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2)
300#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2)
301
302#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4)
303#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4)
304#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4)
305#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4)
306
307/* GSSP2 */
308#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4)
309#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4)
310#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4)
311#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4)
312
313#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4)
314#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4)
315#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4)
316#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4)
317
318#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2)
319#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2)
320#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2)
321#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2)
322#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2)
323#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5)
324
325#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2)
326#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2)
327#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2)
328#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2)
329
330/* UART1 - FFUART */
331#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1)
332#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1)
333#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1)
334#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1)
335#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1)
336#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1)
337#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1)
338#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1)
339
340#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2)
341#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2)
342#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2)
343#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2)
344#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2)
345#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2)
346#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2)
347#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2)
348
349/* UART2 - BTUART */
350#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1)
351#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1)
352#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1)
353#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1)
354
355/* UART3 - STUART */
356#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3)
357#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3)
358#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3)
359#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3)
360
361#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5)
362#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5)
363#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5)
364#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5)
365
366/* DFI */
367#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2)
368#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2)
369#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2)
370#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2)
371#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2)
372#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2)
373#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2)
374#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2)
375#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2)
376#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2)
377#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2)
378#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2)
379#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2)
380#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2)
381#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2)
382#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2)
383#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2)
384#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2)
385#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2)
386#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2)
387#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2)
388#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2)
389
390/* DFI - NAND */
391#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
392#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
393#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
394#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
395#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
396#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
397#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
398#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
399#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
400#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
401#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
402#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
403#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
404#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
405#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
406#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
407#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
408#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
409#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
410#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
411#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
412#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
413#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
414#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
415#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
416
417/* PWM */
418#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
419#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
420#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
421#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
422#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
423#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
424
425/* CIR */
426#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1)
427#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3)
428
429/* USB P2 */
430#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3)
431#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5)
432#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2)
433#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7)
434#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6)
435#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3)
436
437#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2)
438#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
439#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2)
440#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2)
441#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2)
442#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2)
443#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2)
444#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2)
445
446#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3)
447#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3)
448#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3)
449#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3)
450#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3)
451#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3)
452#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3)
453#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3)
454
455/* ULPI */
456#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4)
457#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7)
458#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5)
459#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5)
460#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5)
461#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5)
462#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5)
463#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5)
464#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4)
465#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4)
466#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4)
467#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4)
468
469#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3)
470#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7)
471#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5)
472#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4)
473#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3)
474#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3)
475
476#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5)
477#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7)
478#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5)
479#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4)
480
481#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3)
482#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7)
483#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3)
484#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5)
485#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4)
486#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3)
487
488/* 1 wire */
489#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5)
490
491#endif /* __ASM_ARCH_MFP_PXA9xx_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
index 02f6157396d3..e7d58798da67 100644
--- a/include/asm-arm/arch-pxa/mfp.h
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -210,6 +210,14 @@ enum {
210 MFP_PIN_DF_IO14, 210 MFP_PIN_DF_IO14,
211 MFP_PIN_DF_IO15, 211 MFP_PIN_DF_IO15,
212 212
213 /* additional pins on PXA930 */
214 MFP_PIN_GSIM_UIO,
215 MFP_PIN_GSIM_UCLK,
216 MFP_PIN_GSIM_UDET,
217 MFP_PIN_GSIM_nURST,
218 MFP_PIN_PMIC_INT,
219 MFP_PIN_RDY,
220
213 MFP_PIN_MAX, 221 MFP_PIN_MAX,
214}; 222};
215 223
diff --git a/include/asm-arm/arch-pxa/palmtx.h b/include/asm-arm/arch-pxa/palmtx.h
new file mode 100644
index 000000000000..1e8bccbda510
--- /dev/null
+++ b/include/asm-arm/arch-pxa/palmtx.h
@@ -0,0 +1,106 @@
1/*
2 * GPIOs and interrupts for Palm T|X Handheld Computer
3 *
4 * Based on palmld-gpio.h by Alex Osborne
5 *
6 * Authors: Marek Vasut <marek.vasut@gmail.com>
7 * Cristiano P. <cristianop@users.sourceforge.net>
8 * Jan Herman <2hp@seznam.cz>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#ifndef _INCLUDE_PALMTX_H_
17#define _INCLUDE_PALMTX_H_
18
19/** HERE ARE GPIOs **/
20
21/* GPIOs */
22#define GPIO_NR_PALMTX_GPIO_RESET 1
23
24#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */
25#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10
26#define GPIO_NR_PALMTX_EARPHONE_DETECT 107
27
28/* SD/MMC */
29#define GPIO_NR_PALMTX_SD_DETECT_N 14
30#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */
31#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */
32
33/* TOUCHSCREEN */
34#define GPIO_NR_PALMTX_WM9712_IRQ 27
35
36/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
37#define GPIO_NR_PALMTX_IR_DISABLE 40
38
39/* USB */
40#define GPIO_NR_PALMTX_USB_DETECT_N 13
41#define GPIO_NR_PALMTX_USB_POWER 95
42#define GPIO_NR_PALMTX_USB_PULLUP 93
43
44/* LCD/BACKLIGHT */
45#define GPIO_NR_PALMTX_BL_POWER 84
46#define GPIO_NR_PALMTX_LCD_POWER 96
47
48/* LCD BORDER */
49#define GPIO_NR_PALMTX_BORDER_SWITCH 98
50#define GPIO_NR_PALMTX_BORDER_SELECT 22
51
52/* BLUETOOTH */
53#define GPIO_NR_PALMTX_BT_POWER 17
54#define GPIO_NR_PALMTX_BT_RESET 83
55
56/* PCMCIA (WiFi) */
57#define GPIO_NR_PALMTX_PCMCIA_POWER1 94
58#define GPIO_NR_PALMTX_PCMCIA_POWER2 108
59#define GPIO_NR_PALMTX_PCMCIA_RESET 79
60#define GPIO_NR_PALMTX_PCMCIA_READY 116
61
62/* NAND Flash ... this GPIO may be incorrect! */
63#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79
64
65/* INTERRUPTS */
66#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)
67#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ)
68#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT)
69#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET)
70
71/** HERE ARE INIT VALUES **/
72
73/* Various addresses */
74#define PALMTX_PCMCIA_PHYS 0x28000000
75#define PALMTX_PCMCIA_VIRT 0xf0000000
76#define PALMTX_PCMCIA_SIZE 0x100000
77
78#define PALMTX_PHYS_RAM_START 0xa0000000
79#define PALMTX_PHYS_IO_START 0x40000000
80
81#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
82#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */
83
84/* TOUCHSCREEN */
85#define AC97_LINK_FRAME 21
86
87
88/* BATTERY */
89#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
90#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
91#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */
92#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */
93#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */
94#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */
95#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */
96
97#define PALMTX_BAT_MEASURE_DELAY (HZ * 1)
98
99/* BACKLIGHT */
100#define PALMTX_MAX_INTENSITY 0xFE
101#define PALMTX_DEFAULT_INTENSITY 0x7E
102#define PALMTX_LIMIT_MASK 0x7F
103#define PALMTX_PRESCALER 0x3F
104#define PALMTX_PERIOD_NS 3500
105
106#endif
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
index b699d0d7bdb2..2e2013179063 100644
--- a/include/asm-arm/arch-pxa/pcm990_baseboard.h
+++ b/include/asm-arm/arch-pxa/pcm990_baseboard.h
@@ -29,14 +29,14 @@
29/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ 29/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
30#define PCM990_CTRL_INT_IRQ_GPIO 9 30#define PCM990_CTRL_INT_IRQ_GPIO 9
31#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) 31#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
32#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING 32#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ 33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
34#define PCM990_CTRL_BASE 0xea000000 34#define PCM990_CTRL_BASE 0xea000000
35#define PCM990_CTRL_SIZE (1*1024*1024) 35#define PCM990_CTRL_SIZE (1*1024*1024)
36 36
37#define PCM990_CTRL_PWR_IRQ_GPIO 14 37#define PCM990_CTRL_PWR_IRQ_GPIO 14
38#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) 38#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
39#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING 39#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING
40 40
41/* visible CPLD (U7) registers */ 41/* visible CPLD (U7) registers */
42#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ 42#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
@@ -133,7 +133,7 @@
133 */ 133 */
134#define PCM990_IDE_IRQ_GPIO 13 134#define PCM990_IDE_IRQ_GPIO 13
135#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) 135#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
136#define PCM990_IDE_IRQ_EDGE IRQT_RISING 136#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
137#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ 137#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
138#define PCM990_IDE_PLD_BASE 0xee000000 138#define PCM990_IDE_PLD_BASE 0xee000000
139#define PCM990_IDE_PLD_SIZE (1*1024*1024) 139#define PCM990_IDE_PLD_SIZE (1*1024*1024)
@@ -189,11 +189,11 @@
189 */ 189 */
190#define PCM990_CF_IRQ_GPIO 11 190#define PCM990_CF_IRQ_GPIO 11
191#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) 191#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
192#define PCM990_CF_IRQ_EDGE IRQT_RISING 192#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING
193 193
194#define PCM990_CF_CD_GPIO 12 194#define PCM990_CF_CD_GPIO 12
195#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) 195#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
196#define PCM990_CF_CD_EDGE IRQT_RISING 196#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
197 197
198#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ 198#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
199#define PCM990_CF_PLD_BASE 0xef000000 199#define PCM990_CF_PLD_BASE 0xef000000
@@ -259,14 +259,14 @@
259 */ 259 */
260#define PCM990_AC97_IRQ_GPIO 10 260#define PCM990_AC97_IRQ_GPIO 10
261#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) 261#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
262#define PCM990_AC97_IRQ_EDGE IRQT_RISING 262#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING
263 263
264/* 264/*
265 * MMC phyCORE 265 * MMC phyCORE
266 */ 266 */
267#define PCM990_MMC0_IRQ_GPIO 9 267#define PCM990_MMC0_IRQ_GPIO 9
268#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) 268#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
269#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING 269#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
270 270
271/* 271/*
272 * USB phyCore 272 * USB phyCore
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
index 840305916b6d..1b80a4805a60 100644
--- a/include/asm-arm/arch-pxa/pxa25x-udc.h
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -2,7 +2,7 @@
2#define _ASM_ARCH_PXA25X_UDC_H 2#define _ASM_ARCH_PXA25X_UDC_H
3 3
4#ifdef _ASM_ARCH_PXA27X_UDC_H 4#ifdef _ASM_ARCH_PXA27X_UDC_H
5#error You can't include both PXA25x and PXA27x UDC support 5#error "You can't include both PXA25x and PXA27x UDC support"
6#endif 6#endif
7 7
8#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ 8#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
index bc1cf7d0773a..ab1443f8bd89 100644
--- a/include/asm-arm/arch-pxa/pxa27x-udc.h
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -97,7 +97,7 @@
97#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ 97#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
98#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ 98#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
99#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ 99#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
100#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ 100#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */
101 101
102#define UDCCSN(x) __REG2(0x40600100, (x) << 2) 102#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
103#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ 103#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index 3459fb26ce97..2206cb61a9f9 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -41,4 +41,6 @@ struct pxa2xx_spi_chip {
41 void (*cs_control)(u32 command); 41 void (*cs_control)(u32 command);
42}; 42};
43 43
44extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
45
44#endif /*PXA2XX_SPI_H_*/ 46#endif /*PXA2XX_SPI_H_*/
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h
index 81a8937486cb..eb4b190b6657 100644
--- a/include/asm-arm/arch-pxa/pxa3xx_nand.h
+++ b/include/asm-arm/arch-pxa/pxa3xx_nand.h
@@ -15,4 +15,6 @@ struct pxa3xx_nand_platform_data {
15 struct mtd_partition *parts; 15 struct mtd_partition *parts;
16 unsigned int nr_parts; 16 unsigned int nr_parts;
17}; 17};
18
19extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
18#endif /* __ASM_ARCH_PXA3XX_NAND_H */ 20#endif /* __ASM_ARCH_PXA3XX_NAND_H */
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
index bbd22396841a..daf018d0c604 100644
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ b/include/asm-arm/arch-pxa/pxafb.h
@@ -71,7 +71,8 @@ struct pxafb_mode_info {
71 71
72 u_char bpp; 72 u_char bpp;
73 u_int cmap_greyscale:1, 73 u_int cmap_greyscale:1,
74 unused:31; 74 depth:8,
75 unused:23;
75 76
76 /* Parallel Mode Timing */ 77 /* Parallel Mode Timing */
77 u_char hsync_len; 78 u_char hsync_len;
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h
index 3ba464c913a5..820a189684a9 100644
--- a/include/asm-arm/arch-pxa/regs-lcd.h
+++ b/include/asm-arm/arch-pxa/regs-lcd.h
@@ -27,6 +27,12 @@
27#define LCCR3_4BPP (2 << 24) 27#define LCCR3_4BPP (2 << 24)
28#define LCCR3_8BPP (3 << 24) 28#define LCCR3_8BPP (3 << 24)
29#define LCCR3_16BPP (4 << 24) 29#define LCCR3_16BPP (4 << 24)
30#define LCCR3_18BPP (5 << 24)
31#define LCCR3_18BPP_P (6 << 24)
32#define LCCR3_19BPP (7 << 24)
33#define LCCR3_19BPP_P (1 << 29)
34#define LCCR3_24BPP ((1 << 29) | (1 << 24))
35#define LCCR3_25BPP ((1 << 29) | (2 << 24))
30 36
31#define LCCR3_PDFOR_0 (0 << 30) 37#define LCCR3_PDFOR_0 (0 << 30)
32#define LCCR3_PDFOR_1 (1 << 30) 38#define LCCR3_PDFOR_1 (1 << 30)
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 0255328c3c18..3c04cde2cf1f 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -20,6 +20,10 @@
20#define SSTSS (0x38) /* SSP Timeslot Status */ 20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */ 21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22 22
23#if defined(CONFIG_PXA3xx)
24#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
25#endif
26
23/* Common PXA2xx bits first */ 27/* Common PXA2xx bits first */
24#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ 28#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
25#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 29#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
@@ -29,10 +33,12 @@
29#define SSCR0_National (0x2 << 4) /* National Microwire */ 33#define SSCR0_National (0x2 << 4) /* National Microwire */
30#define SSCR0_ECS (1 << 6) /* External clock select */ 34#define SSCR0_ECS (1 << 6) /* External clock select */
31#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ 35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
36
32#if defined(CONFIG_PXA25x) 37#if defined(CONFIG_PXA25x)
33#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ 38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
34#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ 39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
35#elif defined(CONFIG_PXA27x) 40
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
36#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ 42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
37#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ 43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
38#define SSCR0_EDSS (1 << 20) /* Extended data size select */ 44#define SSCR0_EDSS (1 << 20) /* Extended data size select */
@@ -45,6 +51,10 @@
45#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 51#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
46#endif 52#endif
47 53
54#if defined(CONFIG_PXA3xx)
55#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
56#endif
57
48#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 58#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
49#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 59#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
50#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 60#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
@@ -109,5 +119,9 @@
109#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ 119#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
110#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ 120#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
111#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ 121#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
122#if defined(CONFIG_PXA3xx)
123#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
124#endif
125
112 126
113#endif /* __ASM_ARCH_REGS_SSP_H */ 127#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index ba7e132de1b3..6956fc5235f8 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -21,19 +21,4 @@ static inline void arch_idle(void)
21} 21}
22 22
23 23
24static inline void arch_reset(char mode) 24void arch_reset(char mode);
25{
26 if (cpu_is_pxa2xx())
27 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
28
29 if (mode == 's') {
30 /* Jump into ROM at address 0 */
31 cpu_reset(0);
32 } else {
33 /* Initialize the watchdog and let it fire */
34 OWER = OWER_WME;
35 OSSR = OSSR_M3;
36 OSMR3 = OSCR + 368640; /* ... in 100 ms */
37 }
38}
39
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h
index c5b6fde6907c..a72803f0461b 100644
--- a/include/asm-arm/arch-pxa/tosa.h
+++ b/include/asm-arm/arch-pxa/tosa.h
@@ -25,21 +25,18 @@
25 */ 25 */
26#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO 26#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO
27#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 27#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
28#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 28#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1)
29#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) 29#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
30#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) 30#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
31#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) 31#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
32#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 32#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
33#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17 33#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6)
34#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18 34#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7)
35#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 35#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19
36 36
37/* GPIO Direction 1 : output mode / 0:input mode */ 37/* GPIO Direction 1 : output mode / 0:input mode */
38#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ 38#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \
39 TOSA_SCOOP_AUD_PWR_ON |\ 39 TOSA_SCOOP_AUD_PWR_ON)
40 TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
41/* GPIO out put level when init 1: Hi */
42#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN )
43 40
44/* 41/*
45 * SCOOP2 jacket GPIOs 42 * SCOOP2 jacket GPIOs
@@ -49,16 +46,34 @@
49#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) 46#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
50#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) 47#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
51#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) 48#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3)
52#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 49#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4)
53#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 50#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5)
54#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 51#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
55#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) 52#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
56#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 53#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
57 54
58/* GPIO Direction 1 : output mode / 0:input mode */ 55/* GPIO Direction 1 : output mode / 0:input mode */
59#define TOSA_SCOOP_JC_IO_DIR ( \ 56#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL)
60 TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ 57
61 TOSA_SCOOP_JC_CARD_LIMIT_SEL ) 58/*
59 * TC6393XB GPIOs
60 */
61#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12)
62#define TOSA_TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i))
63#define TOSA_TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE))
64
65#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0)
66#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1)
67#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3)
68#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4)
69#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6)
70#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7)
71#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9)
72#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10)
73#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11)
74#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12)
75#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14)
76#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15)
62 77
63/* 78/*
64 * Timing Generator 79 * Timing Generator
@@ -84,13 +99,13 @@
84#define TOSA_GPIO_JACKET_DETECT (7) 99#define TOSA_GPIO_JACKET_DETECT (7)
85#define TOSA_GPIO_nSD_DETECT (9) 100#define TOSA_GPIO_nSD_DETECT (9)
86#define TOSA_GPIO_nSD_INT (10) 101#define TOSA_GPIO_nSD_INT (10)
87#define TOSA_GPIO_TC6393_CLK (11) 102#define TOSA_GPIO_TC6393XB_CLK (11)
88#define TOSA_GPIO_BAT1_CRG (12) 103#define TOSA_GPIO_BAT1_CRG (12)
89#define TOSA_GPIO_CF_CD (13) 104#define TOSA_GPIO_CF_CD (13)
90#define TOSA_GPIO_BAT0_CRG (14) 105#define TOSA_GPIO_BAT0_CRG (14)
91#define TOSA_GPIO_TC6393_INT (15) 106#define TOSA_GPIO_TC6393XB_INT (15)
92#define TOSA_GPIO_BAT0_LOW (17) 107#define TOSA_GPIO_BAT0_LOW (17)
93#define TOSA_GPIO_TC6393_RDY (18) 108#define TOSA_GPIO_TC6393XB_RDY (18)
94#define TOSA_GPIO_ON_RESET (19) 109#define TOSA_GPIO_ON_RESET (19)
95#define TOSA_GPIO_EAR_IN (20) 110#define TOSA_GPIO_EAR_IN (20)
96#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ 111#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
@@ -99,6 +114,7 @@
99#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ 114#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */
100#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ 115#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
101#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ 116#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */
117#define TOSA_GPIO_IRDA_TX (47)
102#define TOSA_GPIO_TG_SPI_SCLK (81) 118#define TOSA_GPIO_TG_SPI_SCLK (81)
103#define TOSA_GPIO_TG_SPI_CS (82) 119#define TOSA_GPIO_TG_SPI_CS (82)
104#define TOSA_GPIO_TG_SPI_MOSI (83) 120#define TOSA_GPIO_TG_SPI_MOSI (83)
@@ -137,7 +153,7 @@
137#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) 153#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
138#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) 154#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD)
139#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) 155#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
140#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT) 156#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT)
141#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) 157#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
142#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) 158#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN)
143#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) 159#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ)
diff --git a/include/asm-arm/arch-pxa/tosa_bt.h b/include/asm-arm/arch-pxa/tosa_bt.h
new file mode 100644
index 000000000000..efc3c3d3b75d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/tosa_bt.h
@@ -0,0 +1,22 @@
1/*
2 * Tosa bluetooth built-in chip control.
3 *
4 * Later it may be shared with some other platforms.
5 *
6 * Copyright (c) 2008 Dmitry Baryshkov
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#ifndef TOSA_BT_H
14#define TOSA_BT_H
15
16struct tosa_bt_data {
17 int gpio_pwr;
18 int gpio_reset;
19};
20
21#endif
22
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index dadf4c20b622..f4551269aaf2 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -11,11 +11,11 @@
11 11
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13#include <asm/arch/pxa-regs.h> 13#include <asm/arch/pxa-regs.h>
14#include <asm/mach-types.h>
14 15
15#define __REG(x) ((volatile unsigned long *)x) 16#define __REG(x) ((volatile unsigned long *)x)
16
17#define UART FFUART
18 17
18static volatile unsigned long *UART = FFUART;
19 19
20static inline void putc(char c) 20static inline void putc(char c)
21{ 21{
@@ -33,8 +33,13 @@ static inline void flush(void)
33{ 33{
34} 34}
35 35
36static inline void arch_decomp_setup(void)
37{
38 if (machine_is_littleton())
39 UART = STUART;
40}
41
36/* 42/*
37 * nothing to do 43 * nothing to do
38 */ 44 */
39#define arch_decomp_setup()
40#define arch_decomp_wdog() 45#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index de577de8d18c..0d35ca04731e 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -16,6 +16,8 @@ struct platform_mmc_slot {
16extern struct platform_mmc_slot zylonite_mmc_slot[]; 16extern struct platform_mmc_slot zylonite_mmc_slot[];
17 17
18extern int gpio_eth_irq; 18extern int gpio_eth_irq;
19extern int gpio_debug_led1;
20extern int gpio_debug_led2;
19 21
20extern int wm9713_irq; 22extern int wm9713_irq;
21 23
diff --git a/include/asm-arm/arch-sa1100/h3600.h b/include/asm-arm/arch-sa1100/h3600.h
index 1b6355971574..3ca0ecf095e6 100644
--- a/include/asm-arm/arch-sa1100/h3600.h
+++ b/include/asm-arm/arch-sa1100/h3600.h
@@ -23,6 +23,11 @@
23#ifndef _INCLUDE_H3600_H_ 23#ifndef _INCLUDE_H3600_H_
24#define _INCLUDE_H3600_H_ 24#define _INCLUDE_H3600_H_
25 25
26typedef int __bitwise pm_request_t;
27
28#define PM_SUSPEND ((__force pm_request_t) 1) /* enter D1-D3 */
29#define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */
30
26/* generalized support for H3xxx series Compaq Pocket PC's */ 31/* generalized support for H3xxx series Compaq Pocket PC's */
27#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) 32#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800())
28 33
diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h
index b14cbda01dc3..193f6c15f4dd 100644
--- a/include/asm-arm/arch-sa1100/ide.h
+++ b/include/asm-arm/arch-sa1100/ide.h
@@ -61,7 +61,7 @@ ide_init_default_hwifs(void)
61 61
62 /* Enable GPIO as interrupt line */ 62 /* Enable GPIO as interrupt line */
63 GPDR &= ~LART_GPIO_IDE; 63 GPDR &= ~LART_GPIO_IDE;
64 set_irq_type(LART_IRQ_IDE, IRQT_RISING); 64 set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING);
65 65
66 /* set PCMCIA interface timing */ 66 /* set PCMCIA interface timing */
67 MECR = 0x00060006; 67 MECR = 0x00060006;
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 5c60bfc1a84d..9a1db20e032a 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -277,9 +277,16 @@ static inline int constant_fls(int x)
277 * the clz instruction for much better code efficiency. 277 * the clz instruction for much better code efficiency.
278 */ 278 */
279 279
280#define fls(x) \ 280#define __fls(x) \
281 ( __builtin_constant_p(x) ? constant_fls(x) : \ 281 ( __builtin_constant_p(x) ? constant_fls(x) : \
282 ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) ) 282 ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
283
284/* Implement fls() in C so that 64-bit args are suitably truncated */
285static inline int fls(int x)
286{
287 return __fls(x);
288}
289
283#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) 290#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
284#define __ffs(x) (ffs(x) - 1) 291#define __ffs(x) (ffs(x) - 1)
285#define ffz(x) __ffs( ~(x) ) 292#define ffz(x) __ffs( ~(x) )
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 70b0fe724b62..e68a1cbcc852 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -424,9 +424,9 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
424} 424}
425 425
426#define flush_dcache_mmap_lock(mapping) \ 426#define flush_dcache_mmap_lock(mapping) \
427 write_lock_irq(&(mapping)->tree_lock) 427 spin_lock_irq(&(mapping)->tree_lock)
428#define flush_dcache_mmap_unlock(mapping) \ 428#define flush_dcache_mmap_unlock(mapping) \
429 write_unlock_irq(&(mapping)->tree_lock) 429 spin_unlock_irq(&(mapping)->tree_lock)
430 430
431#define flush_icache_user_range(vma,page,addr,len) \ 431#define flush_icache_user_range(vma,page,addr,len) \
432 flush_dcache_page(page) 432 flush_dcache_page(page)
@@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
459#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0) 459#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
460 460
461#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) 461#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
462 462/*
463 * VIVT caches only
464 */
463#define cache_is_vivt() 1 465#define cache_is_vivt() 1
464#define cache_is_vipt() 0 466#define cache_is_vipt() 0
465#define cache_is_vipt_nonaliasing() 0 467#define cache_is_vipt_nonaliasing() 0
466#define cache_is_vipt_aliasing() 0 468#define cache_is_vipt_aliasing() 0
467#define icache_is_vivt_asid_tagged() 0 469#define icache_is_vivt_asid_tagged() 0
468 470
469#elif defined(CONFIG_CPU_CACHE_VIPT) 471#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
470 472/*
473 * VIPT caches only
474 */
471#define cache_is_vivt() 0 475#define cache_is_vivt() 0
472#define cache_is_vipt() 1 476#define cache_is_vipt() 1
473#define cache_is_vipt_nonaliasing() \ 477#define cache_is_vipt_nonaliasing() \
@@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
489 }) 493 })
490 494
491#else 495#else
492 496/*
497 * VIVT or VIPT caches. Note that this is unreliable since ARM926
498 * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
499 * There's no way to tell from the CacheType register what type (!)
500 * the cache is.
501 */
493#define cache_is_vivt() \ 502#define cache_is_vivt() \
494 ({ \ 503 ({ \
495 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 504 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index 943f23bc99a2..45329fca1b64 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -58,7 +58,7 @@ static inline int dma_is_consistent(struct device *dev, dma_addr_t handle)
58/* 58/*
59 * DMA errors are defined by all-bits-set in the DMA address. 59 * DMA errors are defined by all-bits-set in the DMA address.
60 */ 60 */
61static inline int dma_mapping_error(dma_addr_t dma_addr) 61static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
62{ 62{
63 return dma_addr == ~0; 63 return dma_addr == ~0;
64} 64}
diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h
index a32b86ac62aa..af64676650a2 100644
--- a/include/asm-arm/hardware/iop3xx-adma.h
+++ b/include/asm-arm/hardware/iop3xx-adma.h
@@ -260,7 +260,7 @@ static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
260static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, 260static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
261 int *slots_per_op) 261 int *slots_per_op)
262{ 262{
263 static const int slot_count_table[] = { 0, 263 static const char slot_count_table[] = {
264 1, 1, 1, 1, /* 01 - 04 */ 264 1, 1, 1, 1, /* 01 - 04 */
265 2, 2, 2, 2, /* 05 - 08 */ 265 2, 2, 2, 2, /* 05 - 08 */
266 4, 4, 4, 4, /* 09 - 12 */ 266 4, 4, 4, 4, /* 09 - 12 */
@@ -270,7 +270,7 @@ static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
270 8, 8, 8, 8, /* 25 - 28 */ 270 8, 8, 8, 8, /* 25 - 28 */
271 8, 8, 8, 8, /* 29 - 32 */ 271 8, 8, 8, 8, /* 29 - 32 */
272 }; 272 };
273 *slots_per_op = slot_count_table[src_cnt]; 273 *slots_per_op = slot_count_table[src_cnt - 1];
274 return *slots_per_op; 274 return *slots_per_op;
275} 275}
276 276
diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h
index 88f4d231ce4f..a48019f99d08 100644
--- a/include/asm-arm/ide.h
+++ b/include/asm-arm/ide.h
@@ -13,10 +13,6 @@
13 13
14#ifdef __KERNEL__ 14#ifdef __KERNEL__
15 15
16#ifndef MAX_HWIFS
17#define MAX_HWIFS 4
18#endif
19
20#define __ide_mm_insw(port,addr,len) readsw(port,addr,len) 16#define __ide_mm_insw(port,addr,len) readsw(port,addr,len)
21#define __ide_mm_insl(port,addr,len) readsl(port,addr,len) 17#define __ide_mm_insl(port,addr,len) readsl(port,addr,len)
22#define __ide_mm_outsw(port,addr,len) writesw(port,addr,len) 18#define __ide_mm_outsw(port,addr,len) writesw(port,addr,len)
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
index 1b882a255e35..9cb01907e43b 100644
--- a/include/asm-arm/irq.h
+++ b/include/asm-arm/irq.h
@@ -19,23 +19,6 @@
19#define NO_IRQ ((unsigned int)(-1)) 19#define NO_IRQ ((unsigned int)(-1))
20#endif 20#endif
21 21
22
23/*
24 * Migration helpers
25 */
26#define __IRQT_FALEDGE IRQ_TYPE_EDGE_FALLING
27#define __IRQT_RISEDGE IRQ_TYPE_EDGE_RISING
28#define __IRQT_LOWLVL IRQ_TYPE_LEVEL_LOW
29#define __IRQT_HIGHLVL IRQ_TYPE_LEVEL_HIGH
30
31#define IRQT_NOEDGE (0)
32#define IRQT_RISING (__IRQT_RISEDGE)
33#define IRQT_FALLING (__IRQT_FALEDGE)
34#define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE)
35#define IRQT_LOW (__IRQT_LOWLVL)
36#define IRQT_HIGH (__IRQT_HIGHLVL)
37#define IRQT_PROBE IRQ_TYPE_PROBE
38
39#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
40struct irqaction; 23struct irqaction;
41extern void migrate_irqs(void); 24extern void migrate_irqs(void);
diff --git a/include/asm-arm/kgdb.h b/include/asm-arm/kgdb.h
new file mode 100644
index 000000000000..67af4b841984
--- /dev/null
+++ b/include/asm-arm/kgdb.h
@@ -0,0 +1,104 @@
1/*
2 * ARM KGDB support
3 *
4 * Author: Deepak Saxena <dsaxena@mvista.com>
5 *
6 * Copyright (C) 2002 MontaVista Software Inc.
7 *
8 */
9
10#ifndef __ARM_KGDB_H__
11#define __ARM_KGDB_H__
12
13#include <linux/ptrace.h>
14
15/*
16 * GDB assumes that we're a user process being debugged, so
17 * it will send us an SWI command to write into memory as the
18 * debug trap. When an SWI occurs, the next instruction addr is
19 * placed into R14_svc before jumping to the vector trap.
20 * This doesn't work for kernel debugging as we are already in SVC
21 * we would loose the kernel's LR, which is a bad thing. This
22 * is bad thing.
23 *
24 * By doing this as an undefined instruction trap, we force a mode
25 * switch from SVC to UND mode, allowing us to save full kernel state.
26 *
27 * We also define a KGDB_COMPILED_BREAK which can be used to compile
28 * in breakpoints. This is important for things like sysrq-G and for
29 * the initial breakpoint from trap_init().
30 *
31 * Note to ARM HW designers: Add real trap support like SH && PPC to
32 * make our lives much much simpler. :)
33 */
34#define BREAK_INSTR_SIZE 4
35#define GDB_BREAKINST 0xef9f0001
36#define KGDB_BREAKINST 0xe7ffdefe
37#define KGDB_COMPILED_BREAK 0xe7ffdeff
38#define CACHE_FLUSH_IS_SAFE 1
39
40#ifndef __ASSEMBLY__
41
42static inline void arch_kgdb_breakpoint(void)
43{
44 asm(".word 0xe7ffdeff");
45}
46
47extern void kgdb_handle_bus_error(void);
48extern int kgdb_fault_expected;
49
50#endif /* !__ASSEMBLY__ */
51
52/*
53 * From Kevin Hilman:
54 *
55 * gdb is expecting the following registers layout.
56 *
57 * r0-r15: 1 long word each
58 * f0-f7: unused, 3 long words each !!
59 * fps: unused, 1 long word
60 * cpsr: 1 long word
61 *
62 * Even though f0-f7 and fps are not used, they need to be
63 * present in the registers sent for correct processing in
64 * the host-side gdb.
65 *
66 * In particular, it is crucial that CPSR is in the right place,
67 * otherwise gdb will not be able to correctly interpret stepping over
68 * conditional branches.
69 */
70#define _GP_REGS 16
71#define _FP_REGS 8
72#define _EXTRA_REGS 2
73#define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
74
75#define KGDB_MAX_NO_CPUS 1
76#define BUFMAX 400
77#define NUMREGBYTES (GDB_MAX_REGS << 2)
78#define NUMCRITREGBYTES (32 << 2)
79
80#define _R0 0
81#define _R1 1
82#define _R2 2
83#define _R3 3
84#define _R4 4
85#define _R5 5
86#define _R6 6
87#define _R7 7
88#define _R8 8
89#define _R9 9
90#define _R10 10
91#define _FP 11
92#define _IP 12
93#define _SPT 13
94#define _LR 14
95#define _PC 15
96#define _CPSR (GDB_MAX_REGS - 1)
97
98/*
99 * So that we can denote the end of a frame for tracing,
100 * in the simple case:
101 */
102#define CFI_END_FRAME(func) __CFI_END_FRAME(_PC, _SPT, func)
103
104#endif /* __ASM_KGDB_H__ */
diff --git a/include/asm-arm/kvm.h b/include/asm-arm/kvm.h
deleted file mode 100644
index cb3c08cbcb9e..000000000000
--- a/include/asm-arm/kvm.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __LINUX_KVM_ARM_H
2#define __LINUX_KVM_ARM_H
3
4/* arm does not support KVM */
5
6#endif
diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h
index f9f3606986c2..9e5ed7c0f27f 100644
--- a/include/asm-arm/mach/udc_pxa2xx.h
+++ b/include/asm-arm/mach/udc_pxa2xx.h
@@ -23,6 +23,7 @@ struct pxa2xx_udc_mach_info {
23 */ 23 */
24 bool gpio_vbus_inverted; 24 bool gpio_vbus_inverted;
25 u16 gpio_vbus; /* high == vbus present */ 25 u16 gpio_vbus; /* high == vbus present */
26 bool gpio_pullup_inverted;
26 u16 gpio_pullup; /* high == pullup activated */ 27 u16 gpio_pullup; /* high == pullup activated */
27}; 28};
28 29
diff --git a/include/asm-arm/namei.h b/include/asm-arm/namei.h
deleted file mode 100644
index a402d3b9d0f7..000000000000
--- a/include/asm-arm/namei.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * linux/include/asm-arm/namei.h
3 *
4 * Routines to handle famous /usr/gnemul
5 * Derived from the Sparc version of this file
6 *
7 * Included from linux/fs/namei.c
8 */
9
10#ifndef __ASMARM_NAMEI_H
11#define __ASMARM_NAMEI_H
12
13#define ARM_BSD_EMUL "usr/gnemul/bsd/"
14
15static inline char *__emul_prefix(void)
16{
17 switch (current->personality) {
18 case PER_BSD:
19 return ARM_BSD_EMUL;
20 default:
21 return NULL;
22 }
23}
24
25#endif /* __ASMARM_NAMEI_H */
diff --git a/include/asm-arm/page-nommu.h b/include/asm-arm/page-nommu.h
index a1bcad060480..ea1cde84f500 100644
--- a/include/asm-arm/page-nommu.h
+++ b/include/asm-arm/page-nommu.h
@@ -7,6 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10
10#ifndef _ASMARM_PAGE_NOMMU_H 11#ifndef _ASMARM_PAGE_NOMMU_H
11#define _ASMARM_PAGE_NOMMU_H 12#define _ASMARM_PAGE_NOMMU_H
12 13
@@ -42,9 +43,6 @@ typedef unsigned long pgprot_t;
42#define __pmd(x) (x) 43#define __pmd(x) (x)
43#define __pgprot(x) (x) 44#define __pgprot(x) (x)
44 45
45/* to align the pointer to the (next) page boundary */
46#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
47
48extern unsigned long memory_start; 46extern unsigned long memory_start;
49extern unsigned long memory_end; 47extern unsigned long memory_end;
50 48
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 8e05bdb5f12f..7c5fc5582e5d 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -15,9 +15,6 @@
15#define PAGE_SIZE (1UL << PAGE_SHIFT) 15#define PAGE_SIZE (1UL << PAGE_SHIFT)
16#define PAGE_MASK (~(PAGE_SIZE-1)) 16#define PAGE_MASK (~(PAGE_SIZE-1))
17 17
18/* to align the pointer to the (next) page boundary */
19#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
20
21#ifndef __ASSEMBLY__ 18#ifndef __ASSEMBLY__
22 19
23#ifndef CONFIG_MMU 20#ifndef CONFIG_MMU
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index 75feb1574a69..2d84792f2e12 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -78,6 +78,14 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res)
78 return root; 78 return root;
79} 79}
80 80
81/*
82 * Dummy implementation; always return 0.
83 */
84static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
85{
86 return 0;
87}
88
81#endif /* __KERNEL__ */ 89#endif /* __KERNEL__ */
82 90
83#endif 91#endif
diff --git a/include/asm-arm/plat-orion/mv_xor.h b/include/asm-arm/plat-orion/mv_xor.h
new file mode 100644
index 000000000000..c349e8ff5cc0
--- /dev/null
+++ b/include/asm-arm/plat-orion/mv_xor.h
@@ -0,0 +1,28 @@
1/*
2 * Marvell XOR platform device data definition file.
3 */
4
5#ifndef __ASM_PLAT_ORION_MV_XOR_H
6#define __ASM_PLAT_ORION_MV_XOR_H
7
8#include <linux/dmaengine.h>
9#include <linux/mbus.h>
10
11#define MV_XOR_SHARED_NAME "mv_xor_shared"
12#define MV_XOR_NAME "mv_xor"
13
14struct mbus_dram_target_info;
15
16struct mv_xor_platform_shared_data {
17 struct mbus_dram_target_info *dram;
18};
19
20struct mv_xor_platform_data {
21 struct platform_device *shared;
22 int hw_id;
23 dma_cap_mask_t cap_mask;
24 size_t pool_size;
25};
26
27
28#endif
diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h
index 71211c8b5384..d08a1f2863e4 100644
--- a/include/asm-arm/plat-s3c/iic.h
+++ b/include/asm-arm/plat-s3c/iic.h
@@ -21,6 +21,7 @@
21*/ 21*/
22 22
23struct s3c2410_platform_i2c { 23struct s3c2410_platform_i2c {
24 int bus_num; /* bus number to use */
24 unsigned int flags; 25 unsigned int flags;
25 unsigned int slave_addr; /* slave address for controller */ 26 unsigned int slave_addr; /* slave address for controller */
26 unsigned long bus_freq; /* standard bus frequency */ 27 unsigned long bus_freq; /* standard bus frequency */
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index 7aaa206cb54e..8382b7510f94 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -139,8 +139,6 @@ static inline int valid_user_regs(struct pt_regs *regs)
139 return 0; 139 return 0;
140} 140}
141 141
142#endif /* __KERNEL__ */
143
144#define pc_pointer(v) \ 142#define pc_pointer(v) \
145 ((v) & ~PCMASK) 143 ((v) & ~PCMASK)
146 144
@@ -153,10 +151,10 @@ extern unsigned long profile_pc(struct pt_regs *regs);
153#define profile_pc(regs) instruction_pointer(regs) 151#define profile_pc(regs) instruction_pointer(regs)
154#endif 152#endif
155 153
156#ifdef __KERNEL__
157#define predicate(x) ((x) & 0xf0000000) 154#define predicate(x) ((x) & 0xf0000000)
158#define PREDICATE_ALWAYS 0xe0000000 155#define PREDICATE_ALWAYS 0xe0000000
159#endif 156
157#endif /* __KERNEL__ */
160 158
161#endif /* __ASSEMBLY__ */ 159#endif /* __ASSEMBLY__ */
162 160
diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h
deleted file mode 100644
index d9b2034ed1d2..000000000000
--- a/include/asm-arm/semaphore.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <linux/semaphore.h>
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index f5a664786311..d4be2d646160 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -97,19 +97,6 @@ static inline struct thread_info *current_thread_info(void)
97 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); 97 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
98} 98}
99 99
100/* thread information allocation */
101#ifdef CONFIG_DEBUG_STACK_USAGE
102#define alloc_thread_info(tsk) \
103 ((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \
104 THREAD_SIZE_ORDER))
105#else
106#define alloc_thread_info(tsk) \
107 ((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER))
108#endif
109
110#define free_thread_info(info) \
111 free_pages((unsigned long)info, THREAD_SIZE_ORDER);
112
113#define thread_saved_pc(tsk) \ 100#define thread_saved_pc(tsk) \
114 ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc))) 101 ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
115#define thread_saved_fp(tsk) \ 102#define thread_saved_fp(tsk) \
diff --git a/include/asm-arm/traps.h b/include/asm-arm/traps.h
index f1541afcf85c..aa399aec568e 100644
--- a/include/asm-arm/traps.h
+++ b/include/asm-arm/traps.h
@@ -24,4 +24,6 @@ static inline int in_exception_text(unsigned long ptr)
24 ptr < (unsigned long)&__exception_text_end; 24 ptr < (unsigned long)&__exception_text_end;
25} 25}
26 26
27extern void __init early_trap_init(void);
28
27#endif 29#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 20:48:02 -0500