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-rw-r--r--include/asm-arm/Kbuild2
-rw-r--r--include/asm-arm/arch-at91/at91_dbgu.h13
-rw-r--r--include/asm-arm/arch-at91/at91x40.h55
-rw-r--r--include/asm-arm/arch-at91/cpu.h5
-rw-r--r--include/asm-arm/arch-at91/hardware.h17
-rw-r--r--include/asm-arm/arch-at91/timex.h5
-rw-r--r--include/asm-arm/arch-at91/uncompress.h4
-rw-r--r--include/asm-arm/arch-davinci/clock.h22
-rw-r--r--include/asm-arm/arch-davinci/gpio.h156
-rw-r--r--include/asm-arm/arch-davinci/hardware.h38
-rw-r--r--include/asm-arm/arch-davinci/mux.h55
-rw-r--r--include/asm-arm/arch-imx/gpio.h102
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h2
-rw-r--r--include/asm-arm/arch-ixp4xx/ixdp425.h4
-rw-r--r--include/asm-arm/arch-ixp4xx/uncompress.h5
-rw-r--r--include/asm-arm/arch-pxa/dma.h22
-rw-r--r--include/asm-arm/arch-pxa/entry-macro.S30
-rw-r--r--include/asm-arm/arch-pxa/hardware.h36
-rw-r--r--include/asm-arm/arch-pxa/irqs.h26
-rw-r--r--include/asm-arm/arch-pxa/pm.h1
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h22
-rw-r--r--include/asm-arm/elf.h23
-rw-r--r--include/asm-arm/hwcap.h28
-rw-r--r--include/asm-arm/ptrace.h16
24 files changed, 594 insertions, 95 deletions
diff --git a/include/asm-arm/Kbuild b/include/asm-arm/Kbuild
index c68e1680da01..73237bd130a2 100644
--- a/include/asm-arm/Kbuild
+++ b/include/asm-arm/Kbuild
@@ -1 +1,3 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2
3unifdef-y += hwcap.h
diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h
index b0369e176f7b..8019ffd0ad3b 100644
--- a/include/asm-arm/arch-at91/at91_dbgu.h
+++ b/include/asm-arm/arch-at91/at91_dbgu.h
@@ -16,6 +16,7 @@
16#ifndef AT91_DBGU_H 16#ifndef AT91_DBGU_H
17#define AT91_DBGU_H 17#define AT91_DBGU_H
18 18
19#ifdef AT91_DBGU
19#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ 20#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
20#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ 21#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
21#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ 22#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
@@ -30,6 +31,15 @@
30 31
31#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ 32#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
32#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ 33#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
34#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
35#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
36
37#endif /* AT91_DBGU */
38
39/*
40 * Some AT91 parts that don't have full DEBUG units still support the ID
41 * and extensions register.
42 */
33#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ 43#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
34#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ 44#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
35#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ 45#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
@@ -53,7 +63,4 @@
53#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ 63#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
54#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ 64#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
55 65
56#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
57#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
58
59#endif 66#endif
diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h
new file mode 100644
index 000000000000..612203e0177f
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91x40.h
@@ -0,0 +1,55 @@
1/*
2 * include/asm-arm/arch-at91/at91x40.h
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef AT91X40_H
13#define AT91X40_H
14
15/*
16 * IRQ list.
17 */
18#define AT91_ID_FIQ 0 /* FIQ */
19#define AT91_ID_SYS 1 /* System Peripheral */
20#define AT91X40_ID_USART0 2 /* USART port 0 */
21#define AT91X40_ID_USART1 3 /* USART port 1 */
22#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
23#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/
24#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/
25#define AT91X40_ID_WD 7 /* Watchdog? */
26#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */
27
28#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */
29#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */
30#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
31
32/*
33 * System Peripherals (offset from AT91_BASE_SYS)
34 */
35#define AT91_BASE_SYS 0xffc00000
36
37#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */
38#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */
39#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */
40#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */
41#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */
42#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */
43#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */
44#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */
45#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
46
47/*
48 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
49 * But it does have a chip identify register and extension ID, so define at
50 * least these here.
51 */
52#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
53#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
54
55#endif /* AT91X40_H */
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index ef93c30a9c5f..080cbb401a87 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -28,6 +28,11 @@
28 28
29#define ARCH_ID_AT91SAM9RL64 0x019b03a0 29#define ARCH_ID_AT91SAM9RL64 0x019b03a0
30 30
31#define ARCH_ID_AT91M40800 0x14080044
32#define ARCH_ID_AT91R40807 0x44080746
33#define ARCH_ID_AT91M40807 0x14080745
34#define ARCH_ID_AT91R40008 0x44000840
35
31static inline unsigned long at91_cpu_identify(void) 36static inline unsigned long at91_cpu_identify(void)
32{ 37{
33 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); 38 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 46835e945aea..8f1cdd38a969 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -26,18 +26,29 @@
26#include <asm/arch/at91sam9263.h> 26#include <asm/arch/at91sam9263.h>
27#elif defined(CONFIG_ARCH_AT91SAM9RL) 27#elif defined(CONFIG_ARCH_AT91SAM9RL)
28#include <asm/arch/at91sam9rl.h> 28#include <asm/arch/at91sam9rl.h>
29#elif defined(CONFIG_ARCH_AT91X40)
30#include <asm/arch/at91x40.h>
29#else 31#else
30#error "Unsupported AT91 processor" 32#error "Unsupported AT91 processor"
31#endif 33#endif
32 34
33 35
36#ifdef CONFIG_MMU
34/* 37/*
35 * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF 38 * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
36 * to 0xFEF78000 .. 0xFF000000. (544Kb) 39 * to 0xFEF78000 .. 0xFF000000. (544Kb)
37 */ 40 */
38#define AT91_IO_PHYS_BASE 0xFFF78000 41#define AT91_IO_PHYS_BASE 0xFFF78000
39#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
40#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) 42#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
43#else
44/*
45 * Identity mapping for the non MMU case.
46 */
47#define AT91_IO_PHYS_BASE AT91_BASE_SYS
48#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE
49#endif
50
51#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
41 52
42 /* Convert a physical IO address to virtual IO address */ 53 /* Convert a physical IO address to virtual IO address */
43#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) 54#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
@@ -66,7 +77,11 @@
66#define AT91_CHIPSELECT_7 0x80000000 77#define AT91_CHIPSELECT_7 0x80000000
67 78
68/* SDRAM */ 79/* SDRAM */
80#ifdef CONFIG_DRAM_BASE
81#define AT91_SDRAM_BASE CONFIG_DRAM_BASE
82#else
69#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 83#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
84#endif
70 85
71/* Clocks */ 86/* Clocks */
72#define AT91_SLOW_CLOCK 32768 /* slow clock */ 87#define AT91_SLOW_CLOCK 32768 /* slow clock */
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index 2df1ee12dfb7..a310698fb4da 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -42,6 +42,11 @@
42#define AT91SAM9_MASTER_CLOCK 100000000 42#define AT91SAM9_MASTER_CLOCK 100000000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44 44
45#elif defined(CONFIG_ARCH_AT91X40)
46
47#define AT91X40_MASTER_CLOCK 40000000
48#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
49
45#endif 50#endif
46 51
47#endif 52#endif
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h
index 30ac587b3b41..272a7e0dc6cf 100644
--- a/include/asm-arm/arch-at91/uncompress.h
+++ b/include/asm-arm/arch-at91/uncompress.h
@@ -33,20 +33,24 @@
33 */ 33 */
34static void putc(int c) 34static void putc(int c)
35{ 35{
36#ifdef AT91_DBGU
36 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 37 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
37 38
38 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) 39 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY))
39 barrier(); 40 barrier();
40 __raw_writel(c, sys + AT91_DBGU_THR); 41 __raw_writel(c, sys + AT91_DBGU_THR);
42#endif
41} 43}
42 44
43static inline void flush(void) 45static inline void flush(void)
44{ 46{
47#ifdef AT91_DBGU
45 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 48 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
46 49
47 /* wait for transmission to complete */ 50 /* wait for transmission to complete */
48 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) 51 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY))
49 barrier(); 52 barrier();
53#endif
50} 54}
51 55
52#define arch_decomp_setup() 56#define arch_decomp_setup()
diff --git a/include/asm-arm/arch-davinci/clock.h b/include/asm-arm/arch-davinci/clock.h
new file mode 100644
index 000000000000..cc168b7a14f2
--- /dev/null
+++ b/include/asm-arm/arch-davinci/clock.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-arm/arch-davinci/clock.h
3 *
4 * Clock control driver for DaVinci - header file
5 *
6 * Authors: Vladimir Barinov <source@mvista.com>
7 *
8 * 2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __ASM_ARCH_DAVINCI_CLOCK_H
14#define __ASM_ARCH_DAVINCI_CLOCK_H
15
16struct clk;
17
18extern int clk_register(struct clk *clk);
19extern void clk_unregister(struct clk *clk);
20extern int davinci_clk_init(void);
21
22#endif
diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h
new file mode 100644
index 000000000000..ea24a0e0bfd6
--- /dev/null
+++ b/include/asm-arm/arch-davinci/gpio.h
@@ -0,0 +1,156 @@
1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef __DAVINCI_GPIO_H
14#define __DAVINCI_GPIO_H
15
16/*
17 * basic gpio routines
18 *
19 * board-specific init should be done by arch/.../.../board-XXX.c (maybe
20 * initializing banks together) rather than boot loaders; kexec() won't
21 * go through boot loaders.
22 *
23 * the gpio clock will be turned on when gpios are used, and you may also
24 * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
25 * used as gpios, not with other peripherals.
26 *
27 * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe
28 * for later updates, code should write GPIO(N) or:
29 * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
30 * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
31 *
32 * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
33 * for now, that's != GPIO(N)
34 */
35#define GPIO(X) (X) /* 0 <= X <= 70 */
36#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
37#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
38
39struct gpio_controller {
40 u32 dir;
41 u32 out_data;
42 u32 set_data;
43 u32 clr_data;
44 u32 in_data;
45 u32 set_rising;
46 u32 clr_rising;
47 u32 set_falling;
48 u32 clr_falling;
49 u32 intstat;
50};
51
52/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
53 * with constant parameters; or in outlined code they execute at runtime.
54 *
55 * You'd access the controller directly when reading or writing more than
56 * one gpio value at a time, and to support wired logic where the value
57 * being driven by the cpu need not match the value read back.
58 *
59 * These are NOT part of the cross-platform GPIO interface
60 */
61static inline struct gpio_controller *__iomem
62__gpio_to_controller(unsigned gpio)
63{
64 void *__iomem ptr;
65
66 if (gpio < 32)
67 ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
68 else if (gpio < 64)
69 ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
70 else if (gpio < DAVINCI_N_GPIO)
71 ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
72 else
73 ptr = NULL;
74 return ptr;
75}
76
77static inline u32 __gpio_mask(unsigned gpio)
78{
79 return 1 << (gpio % 32);
80}
81
82/* The get/set/clear functions will inline when called with constant
83 * parameters, for low-overhead bitbanging. Illegal constant parameters
84 * cause link-time errors.
85 *
86 * Otherwise, calls with variable parameters use outlined functions.
87 */
88extern int __error_inval_gpio(void);
89
90extern void __gpio_set(unsigned gpio, int value);
91extern int __gpio_get(unsigned gpio);
92
93static inline void gpio_set_value(unsigned gpio, int value)
94{
95 if (__builtin_constant_p(value)) {
96 struct gpio_controller *__iomem g;
97 u32 mask;
98
99 if (gpio >= DAVINCI_N_GPIO)
100 __error_inval_gpio();
101
102 g = __gpio_to_controller(gpio);
103 mask = __gpio_mask(gpio);
104 if (value)
105 __raw_writel(mask, &g->set_data);
106 else
107 __raw_writel(mask, &g->clr_data);
108 return;
109 }
110
111 __gpio_set(gpio, value);
112}
113
114/* Returns zero or nonzero; works for gpios configured as inputs OR
115 * as outputs.
116 *
117 * NOTE: changes in reported values are synchronized to the GPIO clock.
118 * This is most easily seen after calling gpio_set_value() and then immediatly
119 * gpio_get_value(), where the gpio_get_value() would return the old value
120 * until the GPIO clock ticks and the new value gets latched.
121 */
122
123static inline int gpio_get_value(unsigned gpio)
124{
125 struct gpio_controller *__iomem g;
126
127 if (!__builtin_constant_p(gpio))
128 return __gpio_get(gpio);
129
130 if (gpio >= DAVINCI_N_GPIO)
131 return __error_inval_gpio();
132
133 g = __gpio_to_controller(gpio);
134 return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
135}
136
137/* powerup default direction is IN */
138extern int gpio_direction_input(unsigned gpio);
139extern int gpio_direction_output(unsigned gpio, int value);
140
141#include <asm-generic/gpio.h> /* cansleep wrappers */
142
143extern int gpio_request(unsigned gpio, const char *tag);
144extern void gpio_free(unsigned gpio);
145
146static inline int gpio_to_irq(unsigned gpio)
147{
148 return DAVINCI_N_AINTC_IRQ + gpio;
149}
150
151static inline int irq_to_gpio(unsigned irq)
152{
153 return irq - DAVINCI_N_AINTC_IRQ;
154}
155
156#endif /* __DAVINCI_GPIO_H */
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index 60362d80229e..a2e8969afaca 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -11,4 +11,42 @@
11#ifndef __ASM_ARCH_HARDWARE_H 11#ifndef __ASM_ARCH_HARDWARE_H
12#define __ASM_ARCH_HARDWARE_H 12#define __ASM_ARCH_HARDWARE_H
13 13
14/*
15 * Base register addresses
16 */
17#define DAVINCI_DMA_3PCC_BASE (0x01C00000)
18#define DAVINCI_DMA_3PTC0_BASE (0x01C10000)
19#define DAVINCI_DMA_3PTC1_BASE (0x01C10400)
20#define DAVINCI_I2C_BASE (0x01C21000)
21#define DAVINCI_PWM0_BASE (0x01C22000)
22#define DAVINCI_PWM1_BASE (0x01C22400)
23#define DAVINCI_PWM2_BASE (0x01C22800)
24#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
25#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
26#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
27#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
28#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
29#define DAVINCI_IEEE1394_BASE (0x01C60000)
30#define DAVINCI_USB_OTG_BASE (0x01C64000)
31#define DAVINCI_CFC_ATA_BASE (0x01C66000)
32#define DAVINCI_SPI_BASE (0x01C66800)
33#define DAVINCI_GPIO_BASE (0x01C67000)
34#define DAVINCI_UHPI_BASE (0x01C67800)
35#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
36#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
37#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
38#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
39#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
40#define DAVINCI_IMCOP_BASE (0x01CC0000)
41#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
42#define DAVINCI_VLYNQ_BASE (0x01E01000)
43#define DAVINCI_MCBSP_BASE (0x01E02000)
44#define DAVINCI_MMC_SD_BASE (0x01E10000)
45#define DAVINCI_MS_BASE (0x01E20000)
46#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
47#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
48#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
49#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
50#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
51
14#endif /* __ASM_ARCH_HARDWARE_H */ 52#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-davinci/mux.h b/include/asm-arm/arch-davinci/mux.h
new file mode 100644
index 000000000000..c24b6782804d
--- /dev/null
+++ b/include/asm-arm/arch-davinci/mux.h
@@ -0,0 +1,55 @@
1/*
2 * DaVinci pin multiplexing defines
3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_MUX_H
12#define __ASM_ARCH_MUX_H
13
14#define DAVINCI_MUX_AEAW0 0
15#define DAVINCI_MUX_AEAW1 1
16#define DAVINCI_MUX_AEAW2 2
17#define DAVINCI_MUX_AEAW3 3
18#define DAVINCI_MUX_AEAW4 4
19#define DAVINCI_MUX_AECS4 10
20#define DAVINCI_MUX_AECS5 11
21#define DAVINCI_MUX_VLYNQWD0 12
22#define DAVINCI_MUX_VLYNQWD1 13
23#define DAVINCI_MUX_VLSCREN 14
24#define DAVINCI_MUX_VLYNQEN 15
25#define DAVINCI_MUX_HDIREN 16
26#define DAVINCI_MUX_ATAEN 17
27#define DAVINCI_MUX_RGB666 22
28#define DAVINCI_MUX_RGB888 23
29#define DAVINCI_MUX_LOEEN 24
30#define DAVINCI_MUX_LFLDEN 25
31#define DAVINCI_MUX_CWEN 26
32#define DAVINCI_MUX_CFLDEN 27
33#define DAVINCI_MUX_HPIEN 29
34#define DAVINCI_MUX_1394EN 30
35#define DAVINCI_MUX_EMACEN 31
36
37#define DAVINCI_MUX_LEVEL2 32
38#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0)
39#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1)
40#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2)
41#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3)
42#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4)
43#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5)
44#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6)
45#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7)
46#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8)
47#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9)
48#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10)
49#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16)
50#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17)
51#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18)
52
53extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
54
55#endif /* __ASM_ARCH_MUX_H */
diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h
new file mode 100644
index 000000000000..486023263f32
--- /dev/null
+++ b/include/asm-arm/arch-imx/gpio.h
@@ -0,0 +1,102 @@
1#ifndef _IMX_GPIO_H
2
3#include <asm/arch/imx-regs.h>
4
5#define IMX_GPIO_ALLOC_MODE_NORMAL 0
6#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1
7#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2
8#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4
9#define IMX_GPIO_ALLOC_MODE_RELEASE 8
10
11extern int imx_gpio_request(unsigned gpio, const char *label);
12
13extern void imx_gpio_free(unsigned gpio);
14
15extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
16 int alloc_mode, const char *label);
17
18extern int imx_gpio_direction_input(unsigned gpio);
19
20extern int imx_gpio_direction_output(unsigned gpio, int value);
21
22extern void __imx_gpio_set_value(unsigned gpio, int value);
23
24static inline int imx_gpio_get_value(unsigned gpio)
25{
26 return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
27}
28
29static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
30{
31 unsigned long flags;
32
33 raw_local_irq_save(flags);
34 if(value)
35 DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
36 else
37 DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
38 raw_local_irq_restore(flags);
39}
40
41static inline void imx_gpio_set_value(unsigned gpio, int value)
42{
43 if(__builtin_constant_p(gpio))
44 imx_gpio_set_value_inline(gpio, value);
45 else
46 __imx_gpio_set_value(gpio, value);
47}
48
49extern int imx_gpio_to_irq(unsigned gpio);
50
51extern int imx_irq_to_gpio(unsigned irq);
52
53/*-------------------------------------------------------------------------*/
54
55/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
56 * to allow future extension of GPIO logic.
57 */
58
59static inline int gpio_request(unsigned gpio, const char *label)
60{
61 return imx_gpio_request(gpio, label);
62}
63
64static inline void gpio_free(unsigned gpio)
65{
66 imx_gpio_free(gpio);
67}
68
69static inline int gpio_direction_input(unsigned gpio)
70{
71 return imx_gpio_direction_input(gpio);
72}
73
74static inline int gpio_direction_output(unsigned gpio, int value)
75{
76 return imx_gpio_direction_output(gpio, value);
77}
78
79static inline int gpio_get_value(unsigned gpio)
80{
81 return imx_gpio_get_value(gpio);
82}
83
84static inline void gpio_set_value(unsigned gpio, int value)
85{
86 imx_gpio_set_value(gpio, value);
87}
88
89#include <asm-generic/gpio.h> /* cansleep wrappers */
90
91static inline int gpio_to_irq(unsigned gpio)
92{
93 return imx_gpio_to_irq(gpio);
94}
95
96static inline int irq_to_gpio(unsigned irq)
97{
98 return imx_irq_to_gpio(irq);
99}
100
101
102#endif
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index 30de404c61f5..fb9de2733879 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -77,6 +77,8 @@
77#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) 77#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
78#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) 78#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
79 79
80#define GPIO_PORT_MAX 3
81
80#define GPIO_PIN_MASK 0x1f 82#define GPIO_PIN_MASK 0x1f
81#define GPIO_PORT_MASK (0x3 << 5) 83#define GPIO_PORT_MASK (0x3 << 5)
82 84
diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h
index 3d3820d7ba09..e0791af3bfea 100644
--- a/include/asm-arm/arch-ixp4xx/ixdp425.h
+++ b/include/asm-arm/arch-ixp4xx/ixdp425.h
@@ -32,4 +32,8 @@
32#define IXDP425_PCI_INTC_PIN 9 32#define IXDP425_PCI_INTC_PIN 9
33#define IXDP425_PCI_INTD_PIN 8 33#define IXDP425_PCI_INTD_PIN 8
34 34
35/* NAND Flash pins */
36#define IXDP425_NAND_NCE_PIN 12
35 37
38#define IXDP425_NAND_CMD_BYTE 0x01
39#define IXDP425_NAND_ADDR_BYTE 0x02
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
index 09ae6c91be60..f7a35b78823f 100644
--- a/include/asm-arm/arch-ixp4xx/uncompress.h
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -38,9 +38,10 @@ static void flush(void)
38static __inline__ void __arch_decomp_setup(unsigned long arch_id) 38static __inline__ void __arch_decomp_setup(unsigned long arch_id)
39{ 39{
40 /* 40 /*
41 * Coyote and gtwx5715 only have UART2 connected 41 * Some boards are using UART2 as console
42 */ 42 */
43 if (machine_is_adi_coyote() || machine_is_gtwx5715()) 43 if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
44 machine_is_gateway7001() || machine_is_wg302v2())
44 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; 45 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
45 else 46 else
46 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; 47 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index bed042d71d68..3280ee2ddfa5 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -30,30 +30,12 @@ typedef enum {
30 DMA_PRIO_LOW = 2 30 DMA_PRIO_LOW = 2
31} pxa_dma_prio; 31} pxa_dma_prio;
32 32
33#if defined(CONFIG_PXA27x)
34
35#define PXA_DMA_CHANNELS 32
36
37#define pxa_for_each_dma_prio(ch, prio) \
38for ( \
39 ch = prio * 4; \
40 ch != (4 << prio) + 16; \
41 ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
42)
43
44#elif defined(CONFIG_PXA25x)
45
46#define PXA_DMA_CHANNELS 16
47
48#define pxa_for_each_dma_prio(ch, prio) \
49 for (ch = prio * 4; ch != (4 << prio); ch++)
50
51#endif
52
53/* 33/*
54 * DMA registration 34 * DMA registration
55 */ 35 */
56 36
37int __init pxa_init_dma(int num_ch);
38
57int pxa_request_dma (char *name, 39int pxa_request_dma (char *name,
58 pxa_dma_prio prio, 40 pxa_dma_prio prio,
59 void (*irq_handler)(int, void *), 41 void (*irq_handler)(int, void *),
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
index 1d5fbb9b379a..b7e730851461 100644
--- a/include/asm-arm/arch-pxa/entry-macro.S
+++ b/include/asm-arm/arch-pxa/entry-macro.S
@@ -20,20 +20,38 @@
20 .endm 20 .endm
21 21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23#ifdef CONFIG_PXA27x 23 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
24 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP 24 mov \tmp, \tmp, lsr #13
25 mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR 25 and \tmp, \tmp, #0x7 @ Core G
26#else 26 cmp \tmp, #1
27 bhi 1004f
28
27 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 29 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
28 add \base, \base, #0x00d00000 30 add \base, \base, #0x00d00000
29 ldr \irqstat, [\base, #0] @ ICIP 31 ldr \irqstat, [\base, #0] @ ICIP
30 ldr \irqnr, [\base, #4] @ ICMR 32 ldr \irqnr, [\base, #4] @ ICMR
31#endif 33 b 1002f
34
351004:
36 mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
37 mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
38 ands \irqstat, \irqstat, \irqnr
39 beq 1003f
40 rsb \irqstat, \irqnr, #0
41 and \irqstat, \irqstat, \irqnr
42 clz \irqnr, \irqstat
43 rsb \irqnr, \irqnr, #31
44 add \irqnr, \irqnr, #32
45 b 1001f
461003:
47 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
48 mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
491002:
32 ands \irqnr, \irqstat, \irqnr 50 ands \irqnr, \irqstat, \irqnr
33 beq 1001f 51 beq 1001f
34 rsb \irqstat, \irqnr, #0 52 rsb \irqstat, \irqnr, #0
35 and \irqstat, \irqstat, \irqnr 53 and \irqstat, \irqstat, \irqnr
36 clz \irqnr, \irqstat 54 clz \irqnr, \irqstat
37 rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP) 55 rsb \irqnr, \irqnr, #31
381001: 561001:
39 .endm 57 .endm
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e2bdc2fbede1..386121746417 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -62,6 +62,42 @@
62 62
63#ifndef __ASSEMBLY__ 63#ifndef __ASSEMBLY__
64 64
65#define __cpu_is_pxa21x(id) \
66 ({ \
67 unsigned int _id = (id) >> 4 & 0xf3f; \
68 _id == 0x212; \
69 })
70
71#define __cpu_is_pxa25x(id) \
72 ({ \
73 unsigned int _id = (id) >> 4 & 0xfff; \
74 _id == 0x2d0 || _id == 0x290; \
75 })
76
77#define __cpu_is_pxa27x(id) \
78 ({ \
79 unsigned int _id = (id) >> 4 & 0xfff; \
80 _id == 0x411; \
81 })
82
83#define cpu_is_pxa21x() \
84 ({ \
85 unsigned int id = read_cpuid(CPUID_ID); \
86 __cpu_is_pxa21x(id); \
87 })
88
89#define cpu_is_pxa25x() \
90 ({ \
91 unsigned int id = read_cpuid(CPUID_ID); \
92 __cpu_is_pxa25x(id); \
93 })
94
95#define cpu_is_pxa27x() \
96 ({ \
97 unsigned int id = read_cpuid(CPUID_ID); \
98 __cpu_is_pxa27x(id); \
99 })
100
65/* 101/*
66 * Handy routine to set GPIO alternate functions 102 * Handy routine to set GPIO alternate functions
67 */ 103 */
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index 67ed43674c63..a07fe0f928cd 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -11,14 +11,9 @@
11 */ 11 */
12 12
13 13
14#ifdef CONFIG_PXA27x 14#define PXA_IRQ(x) (x)
15#define PXA_IRQ_SKIP 0
16#else
17#define PXA_IRQ_SKIP 7
18#endif
19
20#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP)
21 15
16#ifdef CONFIG_PXA27x
22#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ 17#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
23#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ 18#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
24#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ 19#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
@@ -26,6 +21,8 @@
26#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ 21#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
27#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ 22#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
28#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ 23#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
24#endif
25
29#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ 26#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
30#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ 27#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
31#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ 28#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
@@ -58,18 +55,15 @@
58#ifdef CONFIG_PXA27x 55#ifdef CONFIG_PXA27x
59#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ 56#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
60#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ 57#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
61
62#define PXA_INTERNAL_IRQS 34
63#else
64#define PXA_INTERNAL_IRQS 32
65#endif 58#endif
66 59
67#define GPIO_2_x_TO_IRQ(x) \ 60#define PXA_GPIO_IRQ_BASE (64)
68 PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS) 61#define PXA_GPIO_IRQ_NUM (128)
62
63#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
69#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) 64#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
70 65
71#define IRQ_TO_GPIO_2_x(i) \ 66#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
72 ((i) - IRQ_GPIO(2) + 2)
73#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) 67#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
74 68
75#if defined(CONFIG_PXA25x) 69#if defined(CONFIG_PXA25x)
@@ -84,7 +78,7 @@
84 * these. If you need more, increase IRQ_BOARD_END, but keep it 78 * these. If you need more, increase IRQ_BOARD_END, but keep it
85 * within sensible limits. 79 * within sensible limits.
86 */ 80 */
87#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1) 81#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
88#define IRQ_BOARD_END (IRQ_BOARD_START + 16) 82#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
89 83
90#define IRQ_SA1111_START (IRQ_BOARD_END) 84#define IRQ_SA1111_START (IRQ_BOARD_END)
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
index 7a8a1cdf430d..52243a62c4e7 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -9,4 +9,3 @@
9 9
10extern int pxa_pm_prepare(suspend_state_t state); 10extern int pxa_pm_prepare(suspend_state_t state);
11extern int pxa_pm_enter(suspend_state_t state); 11extern int pxa_pm_enter(suspend_state_t state);
12extern int pxa_pm_finish(suspend_state_t state);
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index dbcc9298b0c8..e68b593d69da 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1765,29 +1765,9 @@
1765#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) 1765#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
1766 1766
1767/* 1767/*
1768 * MultiMediaCard (MMC) controller 1768 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
1769 */ 1769 */
1770 1770
1771#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
1772#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
1773#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
1774#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
1775#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
1776#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
1777#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
1778#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
1779#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
1780#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
1781#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
1782#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
1783#define MMC_CMD __REG(0x41100030) /* Index of current command */
1784#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
1785#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
1786#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
1787#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
1788#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
1789
1790
1791/* 1771/*
1792 * Core Clock 1772 * Core Clock
1793 */ 1773 */
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index 3679a8a8922e..d7a777f05088 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -7,6 +7,7 @@
7 */ 7 */
8#include <asm/ptrace.h> 8#include <asm/ptrace.h>
9#include <asm/user.h> 9#include <asm/user.h>
10#include <asm/hwcap.h>
10 11
11typedef unsigned long elf_greg_t; 12typedef unsigned long elf_greg_t;
12typedef unsigned long elf_freg_t[3]; 13typedef unsigned long elf_freg_t[3];
@@ -39,31 +40,9 @@ typedef struct user_fp elf_fpregset_t;
39#endif 40#endif
40#define ELF_ARCH EM_ARM 41#define ELF_ARCH EM_ARM
41 42
42/*
43 * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
44 */
45#define HWCAP_SWP 1
46#define HWCAP_HALF 2
47#define HWCAP_THUMB 4
48#define HWCAP_26BIT 8 /* Play it safe */
49#define HWCAP_FAST_MULT 16
50#define HWCAP_FPA 32
51#define HWCAP_VFP 64
52#define HWCAP_EDSP 128
53#define HWCAP_JAVA 256
54#define HWCAP_IWMMXT 512
55#define HWCAP_CRUNCH 1024
56
57#ifdef __KERNEL__ 43#ifdef __KERNEL__
58#ifndef __ASSEMBLY__ 44#ifndef __ASSEMBLY__
59/* 45/*
60 * This yields a mask that user programs can use to figure out what
61 * instruction set this cpu supports.
62 */
63#define ELF_HWCAP (elf_hwcap)
64extern unsigned int elf_hwcap;
65
66/*
67 * This yields a string that ld.so will use to load implementation 46 * This yields a string that ld.so will use to load implementation
68 * specific libraries for optimization. This is more specific in 47 * specific libraries for optimization. This is more specific in
69 * intent than poking at uname or /proc/cpuinfo. 48 * intent than poking at uname or /proc/cpuinfo.
diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h
new file mode 100644
index 000000000000..01a1391d3014
--- /dev/null
+++ b/include/asm-arm/hwcap.h
@@ -0,0 +1,28 @@
1#ifndef __ASMARM_HWCAP_H
2#define __ASMARM_HWCAP_H
3
4/*
5 * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
6 */
7#define HWCAP_SWP 1
8#define HWCAP_HALF 2
9#define HWCAP_THUMB 4
10#define HWCAP_26BIT 8 /* Play it safe */
11#define HWCAP_FAST_MULT 16
12#define HWCAP_FPA 32
13#define HWCAP_VFP 64
14#define HWCAP_EDSP 128
15#define HWCAP_JAVA 256
16#define HWCAP_IWMMXT 512
17#define HWCAP_CRUNCH 1024
18
19#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
20/*
21 * This yields a mask that user programs can use to figure out what
22 * instruction set this cpu supports.
23 */
24#define ELF_HWCAP (elf_hwcap)
25extern unsigned int elf_hwcap;
26#endif
27
28#endif
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index ee3d93c281d8..7aaa206cb54e 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -10,6 +10,8 @@
10#ifndef __ASM_ARM_PTRACE_H 10#ifndef __ASM_ARM_PTRACE_H
11#define __ASM_ARM_PTRACE_H 11#define __ASM_ARM_PTRACE_H
12 12
13#include <asm/hwcap.h>
14
13#define PTRACE_GETREGS 12 15#define PTRACE_GETREGS 12
14#define PTRACE_SETREGS 13 16#define PTRACE_SETREGS 13
15#define PTRACE_GETFPREGS 14 17#define PTRACE_GETFPREGS 14
@@ -45,6 +47,7 @@
45#define PSR_T_BIT 0x00000020 47#define PSR_T_BIT 0x00000020
46#define PSR_F_BIT 0x00000040 48#define PSR_F_BIT 0x00000040
47#define PSR_I_BIT 0x00000080 49#define PSR_I_BIT 0x00000080
50#define PSR_A_BIT 0x00000100
48#define PSR_J_BIT 0x01000000 51#define PSR_J_BIT 0x01000000
49#define PSR_Q_BIT 0x08000000 52#define PSR_Q_BIT 0x08000000
50#define PSR_V_BIT 0x10000000 53#define PSR_V_BIT 0x10000000
@@ -103,6 +106,10 @@ struct pt_regs {
103#define thumb_mode(regs) (0) 106#define thumb_mode(regs) (0)
104#endif 107#endif
105 108
109#define isa_mode(regs) \
110 ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
111 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
112
106#define processor_mode(regs) \ 113#define processor_mode(regs) \
107 ((regs)->ARM_cpsr & MODE_MASK) 114 ((regs)->ARM_cpsr & MODE_MASK)
108 115
@@ -117,14 +124,17 @@ struct pt_regs {
117 */ 124 */
118static inline int valid_user_regs(struct pt_regs *regs) 125static inline int valid_user_regs(struct pt_regs *regs)
119{ 126{
120 if (user_mode(regs) && 127 if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
121 (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0) 128 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
122 return 1; 129 return 1;
130 }
123 131
124 /* 132 /*
125 * Force CPSR to something logical... 133 * Force CPSR to something logical...
126 */ 134 */
127 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; 135 regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
136 if (!(elf_hwcap & HWCAP_26BIT))
137 regs->ARM_cpsr |= USR_MODE;
128 138
129 return 0; 139 return 0;
130} 140}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 13:31:00 -0500