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-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h89
1 files changed, 14 insertions, 75 deletions
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 687ade109113..991cb688db75 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -7,7 +7,20 @@
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits. 7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
8 */ 8 */
9 9
10 /* Common PXA2xx bits first */ 10#define SSCR0 (0x00) /* SSP Control Register 0 */
11#define SSCR1 (0x04) /* SSP Control Register 1 */
12#define SSSR (0x08) /* SSP Status Register */
13#define SSITR (0x0C) /* SSP Interrupt Test Register */
14#define SSDR (0x10) /* SSP Data Write/Data Read Register */
15
16#define SSTO (0x28) /* SSP Time Out Register */
17#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18#define SSTSA (0x30) /* SSP Tx Timeslot Active */
19#define SSRSA (0x34) /* SSP Rx Timeslot Active */
20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22
23/* Common PXA2xx bits first */
11#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ 24#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
12#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 25#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
13#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ 26#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
@@ -96,78 +109,4 @@
96#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ 109#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
97#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ 110#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
98 111
99#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
100#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
101#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
102#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
103#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
104
105/* Support existing PXA25x drivers */
106#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
107#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
108#define SSSR SSSR_P1 /* SSP Status Register */
109#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
110#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
111
112/* PXA27x ports */
113#if defined (CONFIG_PXA27x)
114#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
115#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
116#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
117#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
118#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
119#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
120#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
121#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
122#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
123#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
124#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
125#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
126#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
127#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
128#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
129#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
130#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
131#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
132#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
133#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
134#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
135#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
136#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
137#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
138#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
139#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
140#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
141#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
142#else /* PXA255 (only port 2) and PXA26x ports*/
143#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
144#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
145#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
146#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
147#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
148#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
149#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
150#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
151#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
152#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
153#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
154#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
155#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
156#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
157#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
158#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
159#endif
160
161#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
162#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
163#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
164#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
165#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
166#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
167#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
168#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
169#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
170#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
171#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
172
173#endif /* __ASM_ARCH_REGS_SSP_H */ 112#endif /* __ASM_ARCH_REGS_SSP_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 08:57:33 -0500